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([2001:288:7001:2703:afa:5db4:54e4:f59c]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7405902167csm7433788b3a.98.2025.05.05.11.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 May 2025 11:43:45 -0700 (PDT) From: I Hsin Cheng To: neil.armstrong@linaro.org Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, christophe.jaillet@wanadoo.fr, skhan@linuxfoundation.org, dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, I Hsin Cheng Subject: [PATCH v2] drm/meson: Use 1000ULL when operating with mode->clock Date: Tue, 6 May 2025 02:43:38 +0800 Message-ID: <20250505184338.678540-1-richard120310@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Coverity scan reported the usage of "mode->clock * 1000" may lead to integer overflow. Use "1000ULL" instead of "1000" when utilizing it to avoid potential integer overflow issue. Link: https://scan5.scan.coverity.com/#/project-view/10074/10063?selectedIs= sue=3D1646759 Signed-off-by: I Hsin Cheng Reviewed-by: Martin Blumenstingl --- Changelog: v1 -> v2: - Use 1000ULL instead of casting the type of "mode->clock" - Refine commit title and message - Fix the issue for the evaluation inside drm_mode_status meson_encoder_hdmi_mode_valid() as well Christophe, Thanks for your review and your suggestion, I think I should add a tag for you,too, but I'm not sure what should I add, if you would be so kind please let me know how should I tag you in the patch. Best regards, I Hsin Cheng --- drivers/gpu/drm/meson/meson_encoder_hdmi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/m= eson/meson_encoder_hdmi.c index 7752d8ac85f0..c08fa93e50a3 100644 --- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c +++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c @@ -75,7 +75,7 @@ static void meson_encoder_hdmi_set_vclk(struct meson_enco= der_hdmi *encoder_hdmi, unsigned long long venc_freq; unsigned long long hdmi_freq; =20 - vclk_freq =3D mode->clock * 1000; + vclk_freq =3D mode->clock * 1000ULL; =20 /* For 420, pixel clock is half unlike venc clock */ if (encoder_hdmi->output_bus_fmt =3D=3D MEDIA_BUS_FMT_UYYVYY8_0_5X24) @@ -123,7 +123,7 @@ static enum drm_mode_status meson_encoder_hdmi_mode_val= id(struct drm_bridge *bri struct meson_encoder_hdmi *encoder_hdmi =3D bridge_to_meson_encoder_hdmi(= bridge); struct meson_drm *priv =3D encoder_hdmi->priv; bool is_hdmi2_sink =3D display_info->hdmi.scdc.supported; - unsigned long long clock =3D mode->clock * 1000; + unsigned long long clock =3D mode->clock * 1000ULL; unsigned long long phy_freq; unsigned long long vclk_freq; unsigned long long venc_freq; --=20 2.43.0