From nobody Sat Feb 7 17:09:32 2026 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5300D1F8EFA; Mon, 5 May 2025 09:26:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746437176; cv=none; b=aNbMLVSaXLRIgC0TqioROaWMjYzwG1nn01M4mbwlKtnL9jGwmtgzVZrWm5MVaZKDCfsTArSnOBTHUZXEZgdPDwH5Q84XDj02IekEolPT8+YfsF+X/QwRblb+F6IybE2+AxLwfcoX9Pzc31sXxQc7P1SuNWjeqhyPZT665RFwHPw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746437176; c=relaxed/simple; bh=VcxrNFNvV5qkzN/vdC9DutWce0TlEARCPSacWBiEjIY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=C5OGRL+kLvsWwpvvagUv4F5KORB/C+rKB+x1TWTYFxBRRFleRA0/XsOuKLUbxCn/Jhj2f02xbPAIUaFz8hHIPv2IRAFYrSBTps3iAX20Ac+b5uoNic8Eryg+RHfs4kMuPiODlUfobD0atvMi09trkor7D1paH6rVv0Y4PuTbBX4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HdDskr8l; arc=none smtp.client-ip=209.85.210.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HdDskr8l" Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-736c3e7b390so4635288b3a.2; Mon, 05 May 2025 02:26:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1746437174; x=1747041974; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MLGuD3xRhpiNjbF9lD28o0yTJb2ESY0QZYYAMoZGQLc=; b=HdDskr8lWFY91DoNgwy7qyCqjI9infmzYlM3OqA2LCATvXJX+snles/rxv2yeh3UxM 9lHvhjxY8iA8cIWjNijmuP0Eqg3FZkts96KiULO+BpGobDVAsdj6SNkyKvJ/m3tFdPOg wu7vX/kXfIOgEQXcV5MZYe1RRrfTm80VtXSm2AThq6grJtT755jcVaBnEWTpIMN3ke/T R8QInYrhSOKAk/wcCu4Erf9jnBx1GkkyaNys3k/yRsfQgAH9gpIUIqXRwArlfkB6MiTi CZoyD0Hw5j9uasY/AnI0mPvUJz12MyzLvEamtd5c0B9abmYGguI7lJ0IYrTELgAe9TnH 5Khw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746437174; x=1747041974; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MLGuD3xRhpiNjbF9lD28o0yTJb2ESY0QZYYAMoZGQLc=; b=OI2t7dATIbIUEIyTN+nRjP14SUGNlC61aMIABC73Bh/BPinVu7berYJo6t8gGxnCqM GtD7UjQD7AMwB2mw6nuAoYs44/gSiGBVE1LUHGsWgZfL6cvcv9gd2UuMQ9ovQpwqNpJW MKJr3W4gsj7xLSPEFmlMzYtHsdiY7LqihH81G+/dpiiIaTLG3s5keXt8t7xEJ5W3Faoc AP+DjelMoBAtEZdGH6m3/XuBZwfHOac82SRQuScb9rp59c97q40rX11fKblZODglz1nN I/cpauU0d4BhqRSsKH7vCnOhYnmFwlVYrL3e5F/tcN1/XoyIB4IXYMNTujXfQMKXQcNI RthA== X-Forwarded-Encrypted: i=1; AJvYcCV3yCwM9nz6OBjmFFNvLPVeaGfLUb4qp8Lr+tUdanopVZdWpkX18a9F6OLKAGhlAOe4RV+q4EYXq2luzbgj@vger.kernel.org, AJvYcCVE3s1oNo/In3tHkOyJFNUaPpbINNf4IxTuoMpwtYGu4eCSXVWcspL0XHcTaIBEopksB3wvqUtwRlMe@vger.kernel.org X-Gm-Message-State: AOJu0YyfsaU0JlejKciioWRFOwIhMyXr8sqfZmUbBzWitC5c2kmayJBf OqTFGaoIXf7UX1qHAdK9b3HU04kodCSzn2XlyjeCPy0+DBY6FDLo X-Gm-Gg: ASbGncvhlbwM5N+Y2OSoRh2EGW8oEC5HbKGmuLAccUmYN8HoxIe4wOVPPAay+JYqm6d jZKyyxlUINgMRpN6C4YQgj8EJIAMs9naAcJa1OFwTCtVUEzsqlMuNbVh8kV8rsocMO/3EotHWkd RZK65KK77ZFQV6t/EU5nhoMp5ElsGEnpJH3NC2mYxN1zSqEnFEwOKVAyDpypakmNGX8yg26RcdC CnsvXcuBByLm+yroz3nO/j5Grcgzu/v9Ptmx/PBVZh2tVisaq+Elya/jxJhOdIY5q82Iu1fVTev QrMJexSyXIga0i5PV31xoRTzqENg1Cds5OyUBaOpvnXZ54PFjZ2bglBKT+wFTglwsfuj2cZ+ X-Google-Smtp-Source: AGHT+IFxQpvSEmSqpcGYUGW3Me/lHf7Yaq2JWQSrw+dnvf3a/IO/7+aAFj1v7bzMF9hjdbbZVyzozA== X-Received: by 2002:a05:6a00:6c90:b0:73f:ff25:90b3 with SMTP id d2e1a72fcca58-7406f1b08b6mr10857175b3a.24.1746437174451; Mon, 05 May 2025 02:26:14 -0700 (PDT) Received: from openbmc.. (211-23-34-211.hinet-ip.hinet.net. [211.23.34.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74058df2a6csm6288000b3a.81.2025.05.05.02.26.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 May 2025 02:26:13 -0700 (PDT) From: Eason Yang To: jic23@kernel.org, lars@metafoo.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, javier.carrasco.cruz@gmail.com, alisadariana@gmail.com, olivier.moysan@foss.st.com, tgamblin@baylibre.com, eblanc@baylibre.com, antoniu.miclaus@analog.com, andriy.shevchenko@linux.intel.com, gstols@baylibre.com, ramona.nechita@analog.com, matteomartelli3@gmail.com, marcelo.schmitt@analog.com, chanh@os.amperecomputing.com, KWLIU@nuvoton.com, yhyang2@nuvoton.com Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Eason Yang , Krzysztof Kozlowski Subject: [PATCH v9 1/2] dt-bindings: iio: adc: add NCT7201 ADCs Date: Mon, 5 May 2025 17:25:59 +0800 Message-Id: <20250505092600.962675-2-j2anfernee@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250505092600.962675-1-j2anfernee@gmail.com> References: <20250505092600.962675-1-j2anfernee@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a binding specification for the Nuvoton NCT7201/NCT7202 up to 12-bit ADCs with I2C interface. Signed-off-by: Eason Yang Reviewed-by: Krzysztof Kozlowski --- .../bindings/iio/adc/nuvoton,nct7201.yaml | 70 +++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/nuvoton,nct72= 01.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,nct7201.yaml= b/Documentation/devicetree/bindings/iio/adc/nuvoton,nct7201.yaml new file mode 100644 index 000000000000..8ce7d415d956 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,nct7201.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/nuvoton,nct7201.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton nct7201 and similar ADCs + +maintainers: + - Eason Yang + +description: | + The NCT7201/NCT7202 is a Nuvoton Hardware Monitor IC, contains up to 12 + voltage monitoring channels, with SMBus interface, and up to 4 sets SMBus + address selection by ADDR connection. It also provides ALERT# signal for + event notification and reset input RSTIN# to recover it from a fault + condition. + + NCT7201 contains 8 voltage monitor inputs (VIN1~VIN8). + NCT7202 contains 12 voltage monitor inputs (VIN1~VIN12). + +properties: + compatible: + enum: + - nuvoton,nct7201 + - nuvoton,nct7202 + + reg: + maxItems: 1 + + vdd-supply: + description: + A 3.3V to supply that powers the chip. + + vref-supply: + description: + The regulator supply for the ADC reference voltage. + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1d { + compatible =3D "nuvoton,nct7202"; + reg =3D <0x1d>; + vdd-supply =3D <&vdd>; + vref-supply =3D <&vref>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <30 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&gpio3 28 GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 69511c3b2b76..85b031ad7082 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17373,6 +17373,12 @@ F: drivers/nubus/ F: include/linux/nubus.h F: include/uapi/linux/nubus.h =20 +NUVOTON NCT7201 IIO DRIVER +M: Eason Yang +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/iio/adc/nuvoton,nct7201.yaml + NVIDIA (rivafb and nvidiafb) FRAMEBUFFER DRIVER M: Antonino Daplas L: linux-fbdev@vger.kernel.org --=20 2.34.1 From nobody Sat Feb 7 17:09:32 2026 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA0761FCCEB; Mon, 5 May 2025 09:26:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746437182; cv=none; b=qSyBMNe33iEXDu0vrUgplGPyg9eO8Lc2ARREU1y8Tk5gkUfjoqR0lDtJZ/oFYalw0330iyiX3zO1jjxdpWzRSO8bovOuDAJ53hUExiFpv1g+inofqOst6WTpZPg3hvyr0i3BTc9kVWJSBkZeEfJWMIZaGjGskq27/bpwt8eThj8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746437182; c=relaxed/simple; bh=EscBnXa8nXSjGAUpqCXxtkw5zu7KZXSI4RfgXONjgmA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FdQDKgMkuG+cmUF99k+/HhX9pjVfJhaPw82k0LDOsDrh0XWobXhrGUlfl0U5nqZ7aootvneLSWHmkmZ/XGzJSNBKk3bZNG+uOumkkUxTfobAH1QwI5HGF243JuatZc4yts7V5F/1q5cleyce+c5WBXka3uwKqCjxu08U2SIkv4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=cqO0aS/v; arc=none smtp.client-ip=209.85.210.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cqO0aS/v" Received: by mail-pf1-f170.google.com with SMTP id d2e1a72fcca58-73bf5aa95e7so3705547b3a.1; Mon, 05 May 2025 02:26:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1746437179; x=1747041979; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rRuczPaanXNoCiZXXgSmksKq4bBjgAg6rdE6FPnlhPs=; b=cqO0aS/vq3GVqIt/6tg6Wj1agWfBcPwrVZiyq/FHhD/xnvMaMeYUr6ztx349+3FNIg c3GKhk1ToaV8cE1rQcSy+kZpwCJwNtoiOrpfqj9gRHpPuVrBpZ70Ik7CIlWutkPhJE2c 1SZELnFf5zP18EgLXODCOyDsrykhSZbO0l108ysZ9iYGJPiyXB/jynUvmTsGWkSytSEE 9UtqiFRrIpbBErBgeQQIVRYtZMhzqHcaTj1yJvNVOUvTr8VNdAe/BQ9RtNBZa/TOZ7Zk pqTy4CGsynTNU/w8X8AckzZu66p93eK8ECSJS1WNn3l+FtOX9KIT8nm9LL0j/9c2By66 S6Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746437179; x=1747041979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rRuczPaanXNoCiZXXgSmksKq4bBjgAg6rdE6FPnlhPs=; b=TEj0fXcykKd4s60s7dZhrjKhiaHgZyBMwkdrC+jmzuw7gzmwYzyEFpdFcnxAxlXdAg oKyxwl5mmiwk1Gei9Cw4jxVPOpDETBysHkMgBaUuknGYvJiSLGvBBdAkf0F9SuqND7RZ kFFRzdNGxg3xrRUXdgWLmjAhvOERnIO5beuuy+6bo5kUbJdA6tD+7rkFQzhBd31orEgq uqUBQ2heEj2gZ+15Eo3D5dObi6PGB3FYN6xvlXRgTEDsJSzSxEKwAQTePaUV3k8Ul5VQ hHYXD3ynDO6dt3AdZ298JnfG3dI33a65SEC6IEudyC3hBA6wTb8d+YQ5r4QtA9mL3m7b XFcA== X-Forwarded-Encrypted: i=1; AJvYcCWIuLrcivpk0+SSvQ1StY39wMeEhSxGBz8CQMKhu2QthGM6q4Y9ZefPrCK1tijqPJozSJyQTCT3zssg@vger.kernel.org, AJvYcCWfZtJosCH0d4joXwFRGSablt1MvTMCThKsUFXC7EHHEStsdc+IUD/JMgP8Rbjakm5qqkjQcFtgClcNhnzm@vger.kernel.org X-Gm-Message-State: AOJu0YznRbszyNW+JlWlRZs12ALZ9Esyme05opyl4xUBx/5gmnxGRF2f USYs+xGz3K3pLhafBtuFPXz5P0cWJSTCshnXhwhCS4lGKpSIREtx X-Gm-Gg: ASbGncsy9UGS0oEqkAsXu36QmtjxiJiyoc69aJ9MAqpayS2dLDFOZJKiQpV+mgoa1Wm iHfX4HezAUEwkZ+/VPU24bU++nwk0OfltF7UtcGeVag3Ppp8t2zBuPX1T7TUScLcCS/T4JwNmpk X3gnj61bNsnu/gfT0nr/le3mRgnwkjBahHq4dEGZV3vEjbPTLp/F8HM+HF6r5S/7g21dOqFYsU4 Wm1iR42BDxCKMnKSB+5nNKWqAasUlBVxdNBgud8Q8Xvjmw527y+GDGfbetmGKnQMxqCaybbaBJD S17s6/SbjD+URG4InThkzvq+nk4oGrTegpEsp21IdMTD1pgf/JdPd0PyIoolBKpfen2BWRPp X-Google-Smtp-Source: AGHT+IE//A74MiCfvlRozj884hLnVKjqLJLLiM6q7KOBLPZ5MmzcrlQ0UBeJeGNu6oqdQB7vI9s7uw== X-Received: by 2002:a05:6a00:2792:b0:739:4723:c4d7 with SMTP id d2e1a72fcca58-7406f1a5d85mr8762267b3a.22.1746437178936; Mon, 05 May 2025 02:26:18 -0700 (PDT) Received: from openbmc.. (211-23-34-211.hinet-ip.hinet.net. [211.23.34.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74058df2a6csm6288000b3a.81.2025.05.05.02.26.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 May 2025 02:26:18 -0700 (PDT) From: Eason Yang To: jic23@kernel.org, lars@metafoo.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, javier.carrasco.cruz@gmail.com, alisadariana@gmail.com, olivier.moysan@foss.st.com, tgamblin@baylibre.com, eblanc@baylibre.com, antoniu.miclaus@analog.com, andriy.shevchenko@linux.intel.com, gstols@baylibre.com, ramona.nechita@analog.com, matteomartelli3@gmail.com, marcelo.schmitt@analog.com, chanh@os.amperecomputing.com, KWLIU@nuvoton.com, yhyang2@nuvoton.com Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Eason Yang Subject: [PATCH v9 2/2] iio: adc: add support for Nuvoton NCT7201 Date: Mon, 5 May 2025 17:26:00 +0800 Message-Id: <20250505092600.962675-3-j2anfernee@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250505092600.962675-1-j2anfernee@gmail.com> References: <20250505092600.962675-1-j2anfernee@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Nuvoton NCT7201/NCT7202 system voltage monitor 12-bit ADC driver NCT7201/NCT7202 supports up to 12 analog voltage monitor inputs and up to 4 SMBus addresses by ADDR pin. Meanwhile, ALERT# hardware event pins for independent alarm signals, and all the threshold values could be set for system protection without any timing delay. It also supports reset input RSTIN# to recover system from a fault condition. Currently, only single-edge mode conversion and threshold events are supported. Signed-off-by: Eason Yang --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 11 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/nct7201.c | 462 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 475 insertions(+) create mode 100644 drivers/iio/adc/nct7201.c diff --git a/MAINTAINERS b/MAINTAINERS index 85b031ad7082..065202ab8fe7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17378,6 +17378,7 @@ M: Eason Yang L: linux-iio@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/iio/adc/nuvoton,nct7201.yaml +F: drivers/iio/adc/nct7201.c =20 NVIDIA (rivafb and nvidiafb) FRAMEBUFFER DRIVER M: Antonino Daplas diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 6529df1a498c..6d6af1b51b5e 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1092,6 +1092,17 @@ config NAU7802 To compile this driver as a module, choose M here: the module will be called nau7802. =20 +config NCT7201 + tristate "Nuvoton Instruments NCT7201 and NCT7202 Power Monitor" + depends on I2C + select REGMAP_I2C + help + If you say yes here you get support for the Nuvoton NCT7201 and + NCT7202 Voltage Monitor. + + This driver can also be built as a module. If so, the module + will be called nct7201. + config NPCM_ADC tristate "Nuvoton NPCM ADC driver" depends on ARCH_NPCM || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 3e918c3eec69..54e8a7541af6 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_MESON_SARADC) +=3D meson_saradc.o obj-$(CONFIG_MP2629_ADC) +=3D mp2629_adc.o obj-$(CONFIG_MXS_LRADC_ADC) +=3D mxs-lradc-adc.o obj-$(CONFIG_NAU7802) +=3D nau7802.o +obj-$(CONFIG_NCT7201) +=3D nct7201.o obj-$(CONFIG_NPCM_ADC) +=3D npcm_adc.o obj-$(CONFIG_PAC1921) +=3D pac1921.o obj-$(CONFIG_PAC1934) +=3D pac1934.o diff --git a/drivers/iio/adc/nct7201.c b/drivers/iio/adc/nct7201.c new file mode 100644 index 000000000000..0dadf699162a --- /dev/null +++ b/drivers/iio/adc/nct7201.c @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for Nuvoton nct7201 and nct7202 power monitor chips. + * + * Copyright (c) 2024-2025 Nuvoton Technology corporation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define NCT7201_REG_INTERRUPT_STATUS_1 0x0C +#define NCT7201_REG_INTERRUPT_STATUS_2 0x0D +#define NCT7201_REG_VOLT_LOW_BYTE 0x0F +#define NCT7201_REG_CONFIGURATION 0x10 +#define NCT7201_BIT_CONFIGURATION_START BIT(0) +#define NCT7201_BIT_CONFIGURATION_ALERT_MSK BIT(1) +#define NCT7201_BIT_CONFIGURATION_CONV_RATE BIT(2) +#define NCT7201_BIT_CONFIGURATION_RESET BIT(7) + +#define NCT7201_REG_ADVANCED_CONFIGURATION 0x11 +#define NCT7201_BIT_ADVANCED_CONF_MOD_ALERT BIT(0) +#define NCT7201_BIT_ADVANCED_CONF_MOD_STS BIT(1) +#define NCT7201_BIT_ADVANCED_CONF_FAULT_QUEUE BIT(2) +#define NCT7201_BIT_ADVANCED_CONF_EN_DEEP_SHUTDOWN BIT(4) +#define NCT7201_BIT_ADVANCED_CONF_EN_SMB_TIMEOUT BIT(5) +#define NCT7201_BIT_ADVANCED_CONF_MOD_RSTIN BIT(7) + +#define NCT7201_REG_CHANNEL_INPUT_MODE 0x12 +#define NCT7201_REG_CHANNEL_ENABLE 0x13 +#define NCT7201_REG_INTERRUPT_MASK_1 0x15 +#define NCT7201_REG_INTERRUPT_MASK_2 0x16 +#define NCT7201_REG_BUSY_STATUS 0x1E +#define NCT7201_BIT_BUSY BIT(0) +#define NCT7201_BIT_PWR_UP BIT(1) +#define NCT7201_REG_ONE_SHOT 0x1F +#define NCT7201_REG_SMUS_ADDRESS 0xFC +#define NCT7201_REG_VIN_MASK GENMASK(15, 3) + +#define NCT7201_REG_VIN(i) (0x00 + i) +#define NCT7201_REG_VIN_HIGH_LIMIT(i) (0x20 + (i) * 2) +#define NCT7201_REG_VIN_LOW_LIMIT(i) (0x21 + (i) * 2) +#define NCT7201_MAX_CHANNEL 12 + +static const struct regmap_range nct7201_read_reg_range[] =3D { + regmap_reg_range(NCT7201_REG_INTERRUPT_STATUS_1, NCT7201_REG_BUSY_STATUS), + regmap_reg_range(NCT7201_REG_SMUS_ADDRESS, NCT7201_REG_SMUS_ADDRESS), +}; + +static const struct regmap_access_table nct7201_readable_regs_tbl =3D { + .yes_ranges =3D nct7201_read_reg_range, + .n_yes_ranges =3D ARRAY_SIZE(nct7201_read_reg_range), +}; + +static const struct regmap_range nct7201_write_reg_range[] =3D { + regmap_reg_range(NCT7201_REG_CONFIGURATION, NCT7201_REG_INTERRUPT_MASK_2), + regmap_reg_range(NCT7201_REG_ONE_SHOT, NCT7201_REG_ONE_SHOT), +}; + +static const struct regmap_access_table nct7201_writeable_regs_tbl =3D { + .yes_ranges =3D nct7201_write_reg_range, + .n_yes_ranges =3D ARRAY_SIZE(nct7201_write_reg_range), +}; + +static const struct regmap_range nct7201_read_vin_reg_range[] =3D { + regmap_reg_range(NCT7201_REG_VIN(0), NCT7201_REG_VIN(NCT7201_MAX_CHANNEL = - 1)), + regmap_reg_range(NCT7201_REG_VIN_HIGH_LIMIT(0), + NCT7201_REG_VIN_LOW_LIMIT(NCT7201_MAX_CHANNEL - 1)), +}; + +static const struct regmap_access_table nct7201_readable_vin_regs_tbl =3D { + .yes_ranges =3D nct7201_read_vin_reg_range, + .n_yes_ranges =3D ARRAY_SIZE(nct7201_read_vin_reg_range), +}; + +static const struct regmap_range nct7201_write_vin_reg_range[] =3D { + regmap_reg_range(NCT7201_REG_VIN_HIGH_LIMIT(0), + NCT7201_REG_VIN_LOW_LIMIT(NCT7201_MAX_CHANNEL - 1)), +}; + +static const struct regmap_access_table nct7201_writeable_vin_regs_tbl =3D= { + .yes_ranges =3D nct7201_write_vin_reg_range, + .n_yes_ranges =3D ARRAY_SIZE(nct7201_write_vin_reg_range), +}; + +static const struct regmap_config nct7201_regmap8_config =3D { + .name =3D "vin-data-read-byte", + .reg_bits =3D 8, + .val_bits =3D 8, + .use_single_read =3D true, + .use_single_write =3D true, + .max_register =3D 0xff, + .rd_table =3D &nct7201_readable_regs_tbl, + .wr_table =3D &nct7201_writeable_regs_tbl, +}; + +static const struct regmap_config nct7201_regmap16_config =3D { + .name =3D "vin-data-read-word", + .reg_bits =3D 8, + .val_bits =3D 16, + .max_register =3D 0xff, + .rd_table =3D &nct7201_readable_vin_regs_tbl, + .wr_table =3D &nct7201_writeable_vin_regs_tbl, +}; + +struct nct7201_chip_info { + struct regmap *regmap; + struct regmap *regmap16; + int num_vin_channels; + __le16 vin_mask; +}; + +struct nct7201_adc_model_data { + const char *model_name; + const struct iio_chan_spec *channels; + unsigned int num_channels; + int num_vin_channels; +}; + +static const struct iio_event_spec nct7201_events[] =3D { + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_RISING, + .mask_separate =3D BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_ENABLE), + }, { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_FALLING, + .mask_separate =3D BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_ENABLE), + }, +}; + +#define NCT7201_VOLTAGE_CHANNEL(num) \ + { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D num + 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ + .address =3D num, \ + .event_spec =3D nct7201_events, \ + .num_event_specs =3D ARRAY_SIZE(nct7201_events), \ + } + +static const struct iio_chan_spec nct7201_channels[] =3D { + NCT7201_VOLTAGE_CHANNEL(0), + NCT7201_VOLTAGE_CHANNEL(1), + NCT7201_VOLTAGE_CHANNEL(2), + NCT7201_VOLTAGE_CHANNEL(3), + NCT7201_VOLTAGE_CHANNEL(4), + NCT7201_VOLTAGE_CHANNEL(5), + NCT7201_VOLTAGE_CHANNEL(6), + NCT7201_VOLTAGE_CHANNEL(7), +}; + +static const struct iio_chan_spec nct7202_channels[] =3D { + NCT7201_VOLTAGE_CHANNEL(0), + NCT7201_VOLTAGE_CHANNEL(1), + NCT7201_VOLTAGE_CHANNEL(2), + NCT7201_VOLTAGE_CHANNEL(3), + NCT7201_VOLTAGE_CHANNEL(4), + NCT7201_VOLTAGE_CHANNEL(5), + NCT7201_VOLTAGE_CHANNEL(6), + NCT7201_VOLTAGE_CHANNEL(7), + NCT7201_VOLTAGE_CHANNEL(8), + NCT7201_VOLTAGE_CHANNEL(9), + NCT7201_VOLTAGE_CHANNEL(10), + NCT7201_VOLTAGE_CHANNEL(11), +}; + +static int nct7201_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct nct7201_chip_info *chip =3D iio_priv(indio_dev); + unsigned int value; + int err; + + if (chan->type !=3D IIO_VOLTAGE) + return -EOPNOTSUPP; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + err =3D regmap_read(chip->regmap16, NCT7201_REG_VIN(chan->address), &val= ue); + if (err) + return err; + *val =3D FIELD_GET(NCT7201_REG_VIN_MASK, value); + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + /* From the datasheet, we have to multiply by 0.0004995 */ + *val =3D 0; + *val2 =3D 499500; + return IIO_VAL_INT_PLUS_NANO; + default: + return -EINVAL; + } +} + +static int nct7201_read_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int *val, int *val2) +{ + struct nct7201_chip_info *chip =3D iio_priv(indio_dev); + unsigned int value; + int err; + + if (chan->type !=3D IIO_VOLTAGE) + return -EOPNOTSUPP; + + if (info !=3D IIO_EV_INFO_VALUE) + return -EINVAL; + + if (dir =3D=3D IIO_EV_DIR_FALLING) + err =3D regmap_read(chip->regmap16, NCT7201_REG_VIN_LOW_LIMIT(chan->addr= ess), + &value); + else + err =3D regmap_read(chip->regmap16, NCT7201_REG_VIN_HIGH_LIMIT(chan->add= ress), + &value); + if (err) + return err; + + *val =3D FIELD_GET(NCT7201_REG_VIN_MASK, value); + + return IIO_VAL_INT; +} + +static int nct7201_write_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int val, int val2) +{ + struct nct7201_chip_info *chip =3D iio_priv(indio_dev); + int err; + + if (chan->type !=3D IIO_VOLTAGE) + return -EOPNOTSUPP; + + if (info !=3D IIO_EV_INFO_VALUE) + return -EOPNOTSUPP; + + if (dir =3D=3D IIO_EV_DIR_FALLING) + err =3D regmap_write(chip->regmap16, NCT7201_REG_VIN_LOW_LIMIT(chan->add= ress), + FIELD_PREP(NCT7201_REG_VIN_MASK, val)); + else + err =3D regmap_write(chip->regmap16, NCT7201_REG_VIN_HIGH_LIMIT(chan->ad= dress), + FIELD_PREP(NCT7201_REG_VIN_MASK, val)); + + return err; +} + +static int nct7201_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct nct7201_chip_info *chip =3D iio_priv(indio_dev); + + if (chan->type !=3D IIO_VOLTAGE) + return -EOPNOTSUPP; + + return !!(le16_to_cpu(chip->vin_mask) & BIT(chan->address)); +} + +static int nct7201_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + bool state) +{ + struct nct7201_chip_info *chip =3D iio_priv(indio_dev); + __le16 mask =3D cpu_to_le16(BIT(chan->address)); + int err; + + if (chan->type !=3D IIO_VOLTAGE) + return -EOPNOTSUPP; + + if (state) + chip->vin_mask |=3D mask; + else + chip->vin_mask &=3D ~mask; + + if (chip->num_vin_channels <=3D 8) + err =3D regmap_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE, + le16_to_cpu(chip->vin_mask)); + else + err =3D regmap_bulk_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE, + &chip->vin_mask, sizeof(chip->vin_mask)); + + return err; +} + +static const struct iio_info nct7201_info =3D { + .read_raw =3D nct7201_read_raw, + .read_event_config =3D nct7201_read_event_config, + .write_event_config =3D nct7201_write_event_config, + .read_event_value =3D nct7201_read_event_value, + .write_event_value =3D nct7201_write_event_value, +}; + +static const struct iio_info nct7201_info_no_irq =3D { + .read_raw =3D nct7201_read_raw, +}; + +static const struct nct7201_adc_model_data nct7201_model_data =3D { + .model_name =3D "nct7201", + .channels =3D nct7201_channels, + .num_channels =3D ARRAY_SIZE(nct7201_channels), + .num_vin_channels =3D 8, +}; + +static const struct nct7201_adc_model_data nct7202_model_data =3D { + .model_name =3D "nct7202", + .channels =3D nct7202_channels, + .num_channels =3D ARRAY_SIZE(nct7202_channels), + .num_vin_channels =3D 12, +}; + +static int nct7201_init_chip(struct nct7201_chip_info *chip) +{ + struct device *dev =3D regmap_get_device(chip->regmap); + __le16 data =3D cpu_to_le16(GENMASK(chip->num_vin_channels - 1, 0)); + unsigned int value; + int err; + + err =3D regmap_write(chip->regmap, NCT7201_REG_CONFIGURATION, + NCT7201_BIT_CONFIGURATION_RESET); + if (err) + return dev_err_probe(dev, err, "Failed to reset chip\n"); + + /* + * After about 25 msecs, the device should be ready and then the power-up + * bit will be set to 1. If not, wait for it. + */ + fsleep(25 * USEC_PER_MSEC); + + err =3D regmap_read(chip->regmap, NCT7201_REG_BUSY_STATUS, &value); + if (err) + return dev_err_probe(dev, err, "Failed to read busy status\n"); + if (!(value & NCT7201_BIT_PWR_UP)) + return dev_err_probe(dev, -EIO, "Failed to power up after reset\n"); + + /* Enable Channels */ + if (chip->num_vin_channels <=3D 8) + err =3D regmap_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE, + le16_to_cpu(data)); + else + err =3D regmap_bulk_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE, + &data, sizeof(data)); + if (err) + return dev_err_probe(dev, err, "Failed to enable channels\n"); + + err =3D regmap_bulk_read(chip->regmap, NCT7201_REG_CHANNEL_ENABLE, + &chip->vin_mask, sizeof(chip->vin_mask)); + if (err) + return dev_err_probe(dev, err, + "Failed to read channel enable register\n"); + + /* Start monitoring if needed */ + err =3D regmap_set_bits(chip->regmap, NCT7201_REG_CONFIGURATION, + NCT7201_BIT_CONFIGURATION_START); + if (err) + return dev_err_probe(dev, err, "Failed to start monitoring\n"); + + return 0; +} + +static int nct7201_probe(struct i2c_client *client) +{ + const struct nct7201_adc_model_data *model_data; + struct device *dev =3D &client->dev; + struct nct7201_chip_info *chip; + struct iio_dev *indio_dev; + int ret; + + model_data =3D i2c_get_match_data(client); + if (!model_data) + return -ENODEV; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*chip)); + if (!indio_dev) + return -ENOMEM; + chip =3D iio_priv(indio_dev); + + chip->regmap =3D devm_regmap_init_i2c(client, &nct7201_regmap8_config); + if (IS_ERR(chip->regmap)) + return dev_err_probe(dev, PTR_ERR(chip->regmap), + "Failed to init regmap\n"); + + chip->regmap16 =3D devm_regmap_init_i2c(client, &nct7201_regmap16_config); + if (IS_ERR(chip->regmap16)) + return dev_err_probe(dev, PTR_ERR(chip->regmap16), + "Failed to init regmap16\n"); + + chip->num_vin_channels =3D model_data->num_vin_channels; + + ret =3D nct7201_init_chip(chip); + if (ret) + return ret; + + indio_dev->name =3D model_data->model_name; + indio_dev->channels =3D model_data->channels; + indio_dev->num_channels =3D model_data->num_channels; + if (client->irq) + indio_dev->info =3D &nct7201_info; + else + indio_dev->info =3D &nct7201_info_no_irq; + indio_dev->modes =3D INDIO_DIRECT_MODE; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct i2c_device_id nct7201_id[] =3D { + { .name =3D "nct7201", .driver_data =3D (kernel_ulong_t)&nct7201_model_da= ta }, + { .name =3D "nct7202", .driver_data =3D (kernel_ulong_t)&nct7202_model_da= ta }, + { } +}; +MODULE_DEVICE_TABLE(i2c, nct7201_id); + +static const struct of_device_id nct7201_of_match[] =3D { + { + .compatible =3D "nuvoton,nct7201", + .data =3D &nct7201_model_data, + }, + { + .compatible =3D "nuvoton,nct7202", + .data =3D &nct7202_model_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, nct7201_of_match); + +static struct i2c_driver nct7201_driver =3D { + .driver =3D { + .name =3D "nct7201", + .of_match_table =3D nct7201_of_match, + }, + .probe =3D nct7201_probe, + .id_table =3D nct7201_id, +}; +module_i2c_driver(nct7201_driver); + +MODULE_AUTHOR("Eason Yang "); +MODULE_DESCRIPTION("Nuvoton NCT7201 voltage monitor driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1