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Mon, 05 May 2025 14:39:39 -0700 (PDT) From: Atish Patra Date: Mon, 05 May 2025 14:39:29 -0700 Subject: [PATCH 4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250505-kvm_lazy_enable_stateen-v1-4-3bfc4008373c@rivosinc.com> References: <20250505-kvm_lazy_enable_stateen-v1-0-3bfc4008373c@rivosinc.com> In-Reply-To: <20250505-kvm_lazy_enable_stateen-v1-0-3bfc4008373c@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-42535 SENVCFG and SSTATEEN CSRs are controlled by HSENVCFG(62) and SSTATEEN0(63) bits in hstateen. Enable them lazily at runtime instead of bootime. Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_insn.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index c46907bfe42f..ed6302b1992b 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -256,9 +256,37 @@ int kvm_riscv_vcpu_hstateen_lazy_enable(struct kvm_vcp= u *vcpu, unsigned int csr_ return KVM_INSN_CONTINUE_SAME_SEPC; } =20 +static int kvm_riscv_vcpu_hstateen_enable_senvcfg(struct kvm_vcpu *vcpu, + unsigned int csr_num, + unsigned long *val, + unsigned long new_val, + unsigned long wr_mask) +{ + return kvm_riscv_vcpu_hstateen_lazy_enable(vcpu, csr_num, SMSTATEEN0_HSEN= VCFG); +} + +static int kvm_riscv_vcpu_hstateen_enable_stateen(struct kvm_vcpu *vcpu, + unsigned int csr_num, + unsigned long *val, + unsigned long new_val, + unsigned long wr_mask) +{ + const unsigned long *isa =3D vcpu->arch.isa; + + if (riscv_isa_extension_available(isa, SMSTATEEN)) + return kvm_riscv_vcpu_hstateen_lazy_enable(vcpu, csr_num, SMSTATEEN0_SST= ATEEN0); + else + return KVM_INSN_EXIT_TO_USER_SPACE; +} + +#define KVM_RISCV_VCPU_STATEEN_CSR_FUNCS \ +{ .base =3D CSR_SENVCFG, .count =3D 1, .func =3D kvm_riscv_vcpu_hstatee= n_enable_senvcfg }, \ +{ .base =3D CSR_SSTATEEN0, .count =3D 1, .func =3D kvm_riscv_vcpu_hstatee= n_enable_stateen },\ + static const struct csr_func csr_funcs[] =3D { KVM_RISCV_VCPU_AIA_CSR_FUNCS KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS + KVM_RISCV_VCPU_STATEEN_CSR_FUNCS { .base =3D CSR_SEED, .count =3D 1, .func =3D seed_csr_rmw }, #ifdef CONFIG_32BIT KVM_RISCV_VCPU_AIA_CSR_32BIT_FUNCS --=20 2.43.0