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Mon, 05 May 2025 14:39:38 -0700 (PDT) From: Atish Patra Date: Mon, 05 May 2025 14:39:28 -0700 Subject: [PATCH 3/5] RISC-V: KVM: Support lazy enabling of siselect and aia bits Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250505-kvm_lazy_enable_stateen-v1-3-3bfc4008373c@rivosinc.com> References: <20250505-kvm_lazy_enable_stateen-v1-0-3bfc4008373c@rivosinc.com> In-Reply-To: <20250505-kvm_lazy_enable_stateen-v1-0-3bfc4008373c@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-42535 Smstateen extension controls the SISELECT and SIPH/SIEH register through hstateen.AIA bit (58). Add lazy enabling support for those bits. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_aia.h | 13 ++++++++++++- arch/riscv/kvm/aia.c | 34 ++++++++++++++++++++++++++++++++++ arch/riscv/kvm/vcpu_insn.c | 3 +++ 3 files changed, 49 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/kvm_aia.h b/arch/riscv/include/asm/kvm_= aia.h index 760a1aef09f7..9e39b0e15169 100644 --- a/arch/riscv/include/asm/kvm_aia.h +++ b/arch/riscv/include/asm/kvm_aia.h @@ -142,12 +142,23 @@ int kvm_riscv_vcpu_aia_rmw_topei(struct kvm_vcpu *vcp= u, unsigned long *val, unsigned long new_val, unsigned long wr_mask); +int kvm_riscv_vcpu_aia_hstateen_enable(struct kvm_vcpu *vcpu, + unsigned int csr_num, unsigned long *val, + unsigned long new_val, unsigned long wr_mask); +int kvm_riscv_vcpu_aia_rmw_isel(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, unsigned long *val, + unsigned long new_val, unsigned long wr_mask); int kvm_riscv_vcpu_aia_rmw_ireg(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, unsigned long *val, unsigned long new_val, unsigned long wr_mask); #define KVM_RISCV_VCPU_AIA_CSR_FUNCS \ { .base =3D CSR_SIREG, .count =3D 1, .func =3D kvm_riscv_vcpu_aia_rmw= _ireg }, \ -{ .base =3D CSR_STOPEI, .count =3D 1, .func =3D kvm_riscv_vcpu_aia_rmw= _topei }, +{ .base =3D CSR_SISELECT, .count =3D 1, .func =3D kvm_riscv_vcpu_aia_rmw= _isel }, \ +{ .base =3D CSR_STOPEI, .count =3D 1, .func =3D kvm_riscv_vcpu_aia_rmw= _topei }, \ +{ .base =3D CSR_STOPI, .count =3D 1, .func =3D kvm_riscv_vcpu_aia_hst= ateen_enable }, \ + +#define KVM_RISCV_VCPU_AIA_CSR_32BIT_FUNCS \ +{ .base =3D CSR_SIPH, .count =3D 1, .func =3D kvm_riscv_vcpu_aia_hstatee= n_enable }, \ +{ .base =3D CSR_SIEH, .count =3D 1, .func =3D kvm_riscv_vcpu_aia_hstatee= n_enable }, \ =20 int kvm_riscv_vcpu_aia_update(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_aia_reset(struct kvm_vcpu *vcpu); diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c index 1e0d2217ade7..3dfabf51a4d2 100644 --- a/arch/riscv/kvm/aia.c +++ b/arch/riscv/kvm/aia.c @@ -235,6 +235,40 @@ int kvm_riscv_vcpu_aia_set_csr(struct kvm_vcpu *vcpu, return 0; } =20 +int kvm_riscv_vcpu_aia_hstateen_enable(struct kvm_vcpu *vcpu, + unsigned int csr_num, + unsigned long *val, + unsigned long new_val, + unsigned long wr_mask) +{ + /* If AIA not available then redirect trap */ + if (!kvm_riscv_aia_available()) + return KVM_INSN_ILLEGAL_TRAP; + + /* If AIA not initialized then forward to user space */ + if (!kvm_riscv_aia_initialized(vcpu->kvm)) + return KVM_INSN_EXIT_TO_USER_SPACE; + + return kvm_riscv_vcpu_hstateen_lazy_enable(vcpu, csr_num, SMSTATEEN0_AIA); +} + +int kvm_riscv_vcpu_aia_rmw_isel(struct kvm_vcpu *vcpu, + unsigned int csr_num, + unsigned long *val, + unsigned long new_val, + unsigned long wr_mask) +{ + /* If AIA not available then redirect trap */ + if (!kvm_riscv_aia_available()) + return KVM_INSN_ILLEGAL_TRAP; + + /* If AIA not initialized then forward to user space */ + if (!kvm_riscv_aia_initialized(vcpu->kvm)) + return KVM_INSN_EXIT_TO_USER_SPACE; + + return kvm_riscv_vcpu_hstateen_lazy_enable(vcpu, csr_num, SMSTATEEN0_AIA_= ISEL); +} + int kvm_riscv_vcpu_aia_rmw_topei(struct kvm_vcpu *vcpu, unsigned int csr_num, unsigned long *val, diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index 3bc39572b79d..c46907bfe42f 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -260,6 +260,9 @@ static const struct csr_func csr_funcs[] =3D { KVM_RISCV_VCPU_AIA_CSR_FUNCS KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS { .base =3D CSR_SEED, .count =3D 1, .func =3D seed_csr_rmw }, +#ifdef CONFIG_32BIT + KVM_RISCV_VCPU_AIA_CSR_32BIT_FUNCS +#endif }; =20 /** --=20 2.43.0