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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54ea94ce656sm1454066e87.105.2025.05.04.17.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 May 2025 17:15:07 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 05 May 2025 03:14:48 +0300 Subject: [PATCH v5 04/13] drm/msm/hdmi: simplify extp clock handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250505-fd-hdmi-hpd-v5-4-48541f76318c@oss.qualcomm.com> References: <20250505-fd-hdmi-hpd-v5-0-48541f76318c@oss.qualcomm.com> In-Reply-To: <20250505-fd-hdmi-hpd-v5-0-48541f76318c@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jessica Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6078; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=LnFkmu2jUxjoORgRsclE+weSQh+e+mvrliRGfmUM560=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoGAL71Ad5wzmGBcA8VFE7DMRBOvRLx8dxrUs4z ufIjtAOA5aJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaBgC+wAKCRCLPIo+Aiko 1dB3B/wO2n/Jj+8+fzMeoCUmZO35ugj4pPICfzq+pGY21TBlDhk6XwBQ+bSYWUjkqExpqq5P6TT dE+HyOW7coWIirnhFz1W81mJ9PA+jtr34B72UqGTJ1upQveyTw0dM8ZBsCighxmvP4tmz4RWFGS YowEdaVv3uOgWAmC0+PxhDaCc/ZXPnKdsW+QnSBd5sbSuGhLJmBeYxDQwzbqlFQ+gbizHdcEtpW mp0dE1JsvV4rTuzx5quTpd7comXMTQ5mvYwSR9mk/HyB6+QIC0BAv+SftitCfBTPu5MCnXlu4n+ Xf3mZJA84P7lqM9EW+Bv8O1n00KilJndpoz7nuk3hvseEvZ0 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: uL8RlVuqCxdfVsRwXyVC-hjgAaIeb8SI X-Proofpoint-GUID: uL8RlVuqCxdfVsRwXyVC-hjgAaIeb8SI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA1MDAwMCBTYWx0ZWRfXyuojyctrYXzJ 6MDfwU0smdxLbSWYvKw4LMTAUI7B7YosYh5/A8yE7ttyOc6nL6Lc377G83ftaLWdGpNOu6SXacI qQ09/vt9lcq94U+ccPpnGhBqFUY6yC2P9v2o51bru2oO1C0Z6m3X25vaNfCqUU1KgiibOQPgbts M9hIntyjd9+Zbh3WHNLkcVQB9FpE6KdBMhmRKpcJ5Ss6hWLRTNjsd5dFTwY4zEIzwIdDiuhO3LO MVF71SWheUFDFN6w3sUnDyWgOLEO4LHY2Zm+OSG51m9P/0KZ271S+bUPfWD2WHhl8M2+Pp9yIU8 Sdk2bh8+TBc/zhmzHb+C/zDBLgnMYtDyBgeF8d+PLVfh+l5r3GkFDGr4pXjIv9YZzOc1UGOdLiB ysl/Y6Md+dtii54GySLmtcd1hkUTGVapMVgsIj3QWfZDk3Kzd/l6WShqndLurMlavtkZGEiP X-Authority-Analysis: v=2.4 cv=AfqxH2XG c=1 sm=1 tr=0 ts=6818030e cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=-xysCvM_RUkaYHfiAagA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-04_09,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 phishscore=0 impostorscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505050000 From: Dmitry Baryshkov With the extp being the only "power" clock left, remove the surrounding loops and handle the extp clock directly. Reviewed-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 24 ++++-------------------- drivers/gpu/drm/msm/hdmi/hdmi.h | 6 +----- drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 33 +++++++++++++-----------------= --- 3 files changed, 18 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdm= i.c index ebf9d8162c6e5759a3780c74354b6c159598750f..104f9cefa14834d04fb957eb487= 77e605d1e29a5 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -233,13 +233,11 @@ static const struct hdmi_platform_config hdmi_tx_8960= _config =3D { }; =20 static const char * const pwr_reg_names_8x74[] =3D {"core-vdda", "core-vcc= "}; -static const char * const pwr_clk_names_8x74[] =3D {"extp"}; static const char * const hpd_clk_names_8x74[] =3D {"iface", "core", "mdp_= core", "alt_iface"}; static unsigned long hpd_clk_freq_8x74[] =3D {0, 19200000, 0, 0}; =20 static const struct hdmi_platform_config hdmi_tx_8974_config =3D { HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(pwr_clk, 8x74), HDMI_CFG(hpd_clk, 8x74), .hpd_freq =3D hpd_clk_freq_8x74, }; @@ -369,24 +367,10 @@ static int msm_hdmi_dev_probe(struct platform_device = *pdev) hdmi->hpd_clks[i] =3D clk; } =20 - hdmi->pwr_clks =3D devm_kcalloc(&pdev->dev, - config->pwr_clk_cnt, - sizeof(hdmi->pwr_clks[0]), - GFP_KERNEL); - if (!hdmi->pwr_clks) - return -ENOMEM; - - for (i =3D 0; i < config->pwr_clk_cnt; i++) { - struct clk *clk; - - clk =3D msm_clk_get(pdev, config->pwr_clk_names[i]); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), - "failed to get pwr clk: %s\n", - config->pwr_clk_names[i]); - - hdmi->pwr_clks[i] =3D clk; - } + hdmi->extp_clk =3D devm_clk_get_optional(&pdev->dev, "extp"); + if (IS_ERR(hdmi->extp_clk)) + return dev_err_probe(dev, PTR_ERR(hdmi->extp_clk), + "failed to get extp clock\n"); =20 hdmi->hpd_gpiod =3D devm_gpiod_get_optional(&pdev->dev, "hpd", GPIOD_IN); /* This will catch e.g. -EPROBE_DEFER */ diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdm= i.h index 381f957b34305494cb4da0b7dccb73b6ac3a1377..3314bb8a09d6bea7e34ad905097= 0bf43c64d1558 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h @@ -50,7 +50,7 @@ struct hdmi { struct regulator_bulk_data *hpd_regs; struct regulator_bulk_data *pwr_regs; struct clk **hpd_clks; - struct clk **pwr_clks; + struct clk *extp_clk; =20 struct gpio_desc *hpd_gpiod; =20 @@ -95,10 +95,6 @@ struct hdmi_platform_config { const char * const *hpd_clk_names; const long unsigned *hpd_freq; int hpd_clk_cnt; - - /* clks that need to be on for screen pwr (ie pixel clk): */ - const char * const *pwr_clk_names; - int pwr_clk_cnt; }; =20 struct hdmi_bridge { diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/h= dmi/hdmi_bridge.c index 9f1191e4c02081c99caa75e1c9c99051f7cd14d1..e7997e4a741c3b27c9086651efe= 6b79dbba6bf88 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -19,7 +19,7 @@ static void msm_hdmi_power_on(struct drm_bridge *bridge) struct hdmi_bridge *hdmi_bridge =3D to_hdmi_bridge(bridge); struct hdmi *hdmi =3D hdmi_bridge->hdmi; const struct hdmi_platform_config *config =3D hdmi->config; - int i, ret; + int ret; =20 pm_runtime_get_sync(&hdmi->pdev->dev); =20 @@ -27,21 +27,15 @@ static void msm_hdmi_power_on(struct drm_bridge *bridge) if (ret) DRM_DEV_ERROR(dev->dev, "failed to enable pwr regulator: %d\n", ret); =20 - if (config->pwr_clk_cnt > 0) { + if (hdmi->extp_clk) { DBG("pixclock: %lu", hdmi->pixclock); - ret =3D clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock); - if (ret) { - DRM_DEV_ERROR(dev->dev, "failed to set pixel clk: %s (%d)\n", - config->pwr_clk_names[0], ret); - } - } + ret =3D clk_set_rate(hdmi->extp_clk, hdmi->pixclock); + if (ret) + DRM_DEV_ERROR(dev->dev, "failed to set extp clk rate: %d\n", ret); =20 - for (i =3D 0; i < config->pwr_clk_cnt; i++) { - ret =3D clk_prepare_enable(hdmi->pwr_clks[i]); - if (ret) { - DRM_DEV_ERROR(dev->dev, "failed to enable pwr clk: %s (%d)\n", - config->pwr_clk_names[i], ret); - } + ret =3D clk_prepare_enable(hdmi->extp_clk); + if (ret) + DRM_DEV_ERROR(dev->dev, "failed to enable extp clk: %d\n", ret); } } =20 @@ -51,15 +45,15 @@ static void power_off(struct drm_bridge *bridge) struct hdmi_bridge *hdmi_bridge =3D to_hdmi_bridge(bridge); struct hdmi *hdmi =3D hdmi_bridge->hdmi; const struct hdmi_platform_config *config =3D hdmi->config; - int i, ret; + int ret; =20 /* TODO do we need to wait for final vblank somewhere before * cutting the clocks? */ mdelay(16 + 4); =20 - for (i =3D 0; i < config->pwr_clk_cnt; i++) - clk_disable_unprepare(hdmi->pwr_clks[i]); + if (hdmi->extp_clk) + clk_disable_unprepare(hdmi->extp_clk); =20 ret =3D regulator_bulk_disable(config->pwr_reg_cnt, hdmi->pwr_regs); if (ret) @@ -438,7 +432,6 @@ static enum drm_mode_status msm_hdmi_bridge_tmds_char_r= ate_valid(const struct dr { struct hdmi_bridge *hdmi_bridge =3D to_hdmi_bridge(bridge); struct hdmi *hdmi =3D hdmi_bridge->hdmi; - const struct hdmi_platform_config *config =3D hdmi->config; struct msm_drm_private *priv =3D bridge->dev->dev_private; struct msm_kms *kms =3D priv->kms; long actual; @@ -451,8 +444,8 @@ static enum drm_mode_status msm_hdmi_bridge_tmds_char_r= ate_valid(const struct dr actual =3D kms->funcs->round_pixclk(kms, tmds_rate, hdmi_bridge->hdmi->encoder); - else if (config->pwr_clk_cnt > 0) - actual =3D clk_round_rate(hdmi->pwr_clks[0], tmds_rate); + else if (hdmi->extp_clk) + actual =3D clk_round_rate(hdmi->extp_clk, tmds_rate); else actual =3D tmds_rate; =20 --=20 2.39.5