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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad1891a26bdsm306050266b.43.2025.05.04.02.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 May 2025 02:23:46 -0700 (PDT) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/3] dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114+ Date: Sun, 4 May 2025 12:23:22 +0300 Message-ID: <20250504092324.10802-2-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250504092324.10802-1-clamor95@gmail.com> References: <20250504092324.10802-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current EPP, ISP and MPE schemas are largely compatible with Tegra114+, requiring only minor adjustments. Additionally, the TSEC schema for the Security engine, which is available from Tegra114 onwards, is included. Signed-off-by: Svyatoslav Ryhel --- .../display/tegra/nvidia,tegra114-tsec.yaml | 79 +++++++++++++++++++ .../display/tegra/nvidia,tegra20-epp.yaml | 14 +++- .../display/tegra/nvidia,tegra20-isp.yaml | 15 +++- .../display/tegra/nvidia,tegra20-mpe.yaml | 18 +++-- 4 files changed, 113 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,= tegra114-tsec.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra11= 4-tsec.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra1= 14-tsec.yaml new file mode 100644 index 000000000000..ed0a5a8a091b --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.= yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Security co-processor + +maintainers: + - Svyatoslav Ryhel + - Thierry Reding + +description: Tegra Security co-processor, an embedded security processor u= sed + mainly to manage the HDCP encryption and keys on the HDMI link. + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra114-tsec + - nvidia,tegra124-tsec + - nvidia,tegra210-tsec + + - items: + - const: nvidia,tegra132-tsec + - const: nvidia,tegra124-tsec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: tsec + + resets: + maxItems: 1 + + reset-names: + items: + - const: tsec + + iommus: + maxItems: 1 + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the core power domain + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + +examples: + - | + #include + #include + + tsec@54500000 { + compatible =3D "nvidia,tegra114-tsec"; + reg =3D <0x54500000 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_TSEC>; + resets =3D <&tegra_car TEGRA114_CLK_TSEC>; + reset-names =3D "tsec"; + }; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20= -epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-= epp.yaml index 3c095a5491fe..334f5531b243 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.ya= ml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.ya= ml @@ -15,10 +15,16 @@ properties: pattern: "^epp@[0-9a-f]+$" =20 compatible: - enum: - - nvidia,tegra20-epp - - nvidia,tegra30-epp - - nvidia,tegra114-epp + oneOf: + - enum: + - nvidia,tegra20-epp + - nvidia,tegra30-epp + - nvidia,tegra114-epp + - nvidia,tegra124-epp + + - items: + - const: nvidia,tegra132-epp + - const: nvidia,tegra124-epp =20 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20= -isp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-= isp.yaml index 3bc3b22e98e1..ee25b5e6f1a2 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.ya= ml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.ya= ml @@ -12,10 +12,17 @@ maintainers: =20 properties: compatible: - enum: - - nvidia,tegra20-isp - - nvidia,tegra30-isp - - nvidia,tegra210-isp + oneOf: + - enum: + - nvidia,tegra20-isp + - nvidia,tegra30-isp + - nvidia,tegra114-isp + - nvidia,tegra124-isp + - nvidia,tegra210-isp + + - items: + - const: nvidia,tegra132-isp + - const: nvidia,tegra124-isp =20 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20= -mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-= mpe.yaml index 2cd3e60cd0a8..36b76fa8f525 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.ya= ml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.ya= ml @@ -12,13 +12,21 @@ maintainers: =20 properties: $nodename: - pattern: "^mpe@[0-9a-f]+$" + oneOf: + - pattern: "^mpe@[0-9a-f]+$" + - pattern: "^msenc@[0-9a-f]+$" =20 compatible: - enum: - - nvidia,tegra20-mpe - - nvidia,tegra30-mpe - - nvidia,tegra114-mpe + oneOf: + - enum: + - nvidia,tegra20-mpe + - nvidia,tegra30-mpe + - nvidia,tegra114-msenc + - nvidia,tegra124-msenc + + - items: + - const: nvidia,tegra132-msenc + - const: nvidia,tegra124-msenc =20 reg: maxItems: 1 --=20 2.48.1