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Sat, 03 May 2025 17:44:45 -0700 (PDT) From: Inochi Amaoto To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Niklas Cassel , Johan Hovold , Shradha Todi , Thippeswamy Havalige , Shashank Babu Chinta Venkata Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Yixun Lan , Longbin Li Subject: [PATCH v3 1/2] dt-bindings: pci: Add Sophgo SG2044 PCIe host Date: Sun, 4 May 2025 08:44:18 +0800 Message-ID: <20250504004420.202685-2-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250504004420.202685-1-inochiama@gmail.com> References: <20250504004420.202685-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The pcie controller on the SG2044 is designware based with custom app registers. Add binding document for SG2044 PCIe host controller. Signed-off-by: Inochi Amaoto Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/sophgo,sg2044-pcie.yaml | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2044-pci= e.yaml diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml = b/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml new file mode 100644 index 000000000000..ff1133bae3ba --- /dev/null +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sophgo,sg2044-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe Root Complex controller on Sophgo SoCs + +maintainers: + - Inochi Amaoto + +description: + SG2044 SoC PCIe Root Complex controller is based on the Synopsys DesignW= are + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie.yaml. + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: sophgo,sg2044-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: iATU registers + - description: Config registers + - description: Sophgo designed configuration registers + + reg-names: + items: + - const: dbi + - const: atu + - const: config + - const: app + + clocks: + items: + - description: core clk + + clock-names: + items: + - const: core + + interrupt-controller: + description: Interrupt controller node for handling legacy PCI interru= pts. + type: object + + properties: + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-controller: true + + interrupts: + items: + - description: combined legacy interrupt + + required: + - "#address-cells" + - "#interrupt-cells" + - interrupt-controller + - interrupts + + additionalProperties: false + + msi-parent: true + + ranges: + maxItems: 5 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@6c00400000 { + compatible =3D "sophgo,sg2044-pcie"; + reg =3D <0x6c 0x00400000 0x0 0x00001000>, + <0x6c 0x00700000 0x0 0x00004000>, + <0x40 0x00000000 0x0 0x00001000>, + <0x6c 0x00780c00 0x0 0x00000400>; + reg-names =3D "dbi", "atu", "config", "app"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x00 0xff>; + clocks =3D <&clk 0>; + clock-names =3D "core"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + msi-parent =3D <&msi>; + ranges =3D <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x002= 00000>, + <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000= 000>, + <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000= 000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000= 000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000= 000>; + + interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-parent =3D <&intc>; + interrupts =3D <64 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +... --=20 2.49.0 From nobody Sun Feb 8 14:21:24 2026 Received: from mail-qt1-f169.google.com (mail-qt1-f169.google.com [209.85.160.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0574925771; Sun, 4 May 2025 00:44:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746319492; cv=none; b=s7X1BxgZJlw+Wj3LIiYBzvWLnfjQ1GdbwYzVoXJG5AkTq2hnrxpX1M/v2GIRRx23mObZwGLgy4nP4csxyKW/YruCLGjiOgXHI3bgiyJikVyAiWQeuRT0seng0lYvjokodJtw2nmtE4txH46aAFQ5dUY2YZp1bqnQgm4RweNaOVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746319492; c=relaxed/simple; bh=yUYPRZNceFGQgxL2ceNChKMjrehxlJP8oyZRPIWJJTU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oR6Mejy6fvf12NERxhttjHlYQdiinJCi6ZJtfjqhhYMXb/c3i1zSgGyAEwNk8pRIcQQTQizvcqX+Ga9A9DwGk3ezuBttTvuUyvR8Us38hl+PgHzR4HiFOY3XcFjyE6bivKquyA5A3h8YGVg8QnnqWv9vOfHWSkRun5JPhqmreys= ARC-Authentication-Results: i=1; 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Sat, 03 May 2025 17:44:49 -0700 (PDT) From: Inochi Amaoto To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Niklas Cassel , Johan Hovold , Shradha Todi , Thippeswamy Havalige , Shashank Babu Chinta Venkata Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Yixun Lan , Longbin Li Subject: [PATCH v3 2/2] PCI: sophgo-dwc: Add Sophgo SG2044 PCIe driver Date: Sun, 4 May 2025 08:44:19 +0800 Message-ID: <20250504004420.202685-3-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250504004420.202685-1-inochiama@gmail.com> References: <20250504004420.202685-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for DesignWare-based PCIe controller in SG2044 SoC. Signed-off-by: Inochi Amaoto --- drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-dw-sophgo.c | 258 ++++++++++++++++++++ 3 files changed, 269 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-dw-sophgo.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index d9f0386396ed..b5b53e5a4cbf 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -402,6 +402,16 @@ config PCIE_UNIPHIER_EP Say Y here if you want PCIe endpoint controller support on UniPhier SoCs. This driver supports Pro5 SoC. =20 +config PCIE_SOPHGO_DW + bool "Sophgo DesignWare PCIe controller" + depends on ARCH_SOPHGO || COMPILE_TEST + depends on PCI_MSI + depends on OF + select PCIE_DW_HOST + help + Enables support for the DesignWare PCIe controller in the + Sophgo SoC. + config PCIE_SPEAR13XX bool "STMicroelectronics SPEAr PCIe controller" depends on ARCH_SPEAR13XX || COMPILE_TEST diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 908cb7f345db..510abb4e04c4 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_PCIE_QCOM_EP) +=3D pcie-qcom-ep.o obj-$(CONFIG_PCIE_ARMADA_8K) +=3D pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) +=3D pcie-artpec6.o obj-$(CONFIG_PCIE_ROCKCHIP_DW) +=3D pcie-dw-rockchip.o +obj-$(CONFIG_PCIE_SOPHGO_DW) +=3D pcie-dw-sophgo.o obj-$(CONFIG_PCIE_INTEL_GW) +=3D pcie-intel-gw.o obj-$(CONFIG_PCIE_KEEMBAY) +=3D pcie-keembay.o obj-$(CONFIG_PCIE_KIRIN) +=3D pcie-kirin.o diff --git a/drivers/pci/controller/dwc/pcie-dw-sophgo.c b/drivers/pci/cont= roller/dwc/pcie-dw-sophgo.c new file mode 100644 index 000000000000..89b22b3ac8d6 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-dw-sophgo.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo DesignWare based PCIe host controller driver + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_sophgo_pcie(x) dev_get_drvdata((x)->dev) + +#define PCIE_INT_SIGNAL 0xc48 +#define PCIE_INT_EN 0xca0 + +#define PCIE_INT_SIGNAL_INTX GENMASK(8, 5) + +#define PCIE_INT_EN_INTX GENMASK(4, 1) +#define PCIE_INT_EN_INT_MSI BIT(5) + +struct sophgo_pcie { + struct dw_pcie pci; + void __iomem *app_base; + struct clk_bulk_data *clks; + unsigned int clk_cnt; + struct irq_domain *irq_domain; +}; + +static int sophgo_pcie_readl_app(struct sophgo_pcie *sophgo, u32 reg) +{ + return readl_relaxed(sophgo->app_base + reg); +} + +static void sophgo_pcie_writel_app(struct sophgo_pcie *sophgo, u32 val, u3= 2 reg) +{ + writel_relaxed(val, sophgo->app_base + reg); +} + +static void sophgo_pcie_intx_handler(struct irq_desc *desc) +{ + struct dw_pcie_rp *pp =3D irq_desc_get_handler_data(desc); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct sophgo_pcie *sophgo =3D to_sophgo_pcie(pci); + unsigned long hwirq, reg; + + chained_irq_enter(chip, desc); + + reg =3D sophgo_pcie_readl_app(sophgo, PCIE_INT_SIGNAL); + reg =3D FIELD_GET(PCIE_INT_SIGNAL_INTX, reg); + + for_each_set_bit(hwirq, ®, PCI_NUM_INTX) + generic_handle_domain_irq(sophgo->irq_domain, hwirq); + + chained_irq_exit(chip, desc); +} + +static void sophgo_intx_irq_mask(struct irq_data *d) +{ + struct dw_pcie_rp *pp =3D irq_data_get_irq_chip_data(d); + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct sophgo_pcie *sophgo =3D to_sophgo_pcie(pci); + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&pp->lock, flags); + + val =3D sophgo_pcie_readl_app(sophgo, PCIE_INT_EN); + val &=3D ~FIELD_PREP(PCIE_INT_EN_INTX, BIT(d->hwirq)); + sophgo_pcie_writel_app(sophgo, val, PCIE_INT_EN); + + raw_spin_unlock_irqrestore(&pp->lock, flags); +}; + +static void sophgo_intx_irq_unmask(struct irq_data *d) +{ + struct dw_pcie_rp *pp =3D irq_data_get_irq_chip_data(d); + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct sophgo_pcie *sophgo =3D to_sophgo_pcie(pci); + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&pp->lock, flags); + + val =3D sophgo_pcie_readl_app(sophgo, PCIE_INT_EN); + val |=3D FIELD_PREP(PCIE_INT_EN_INTX, BIT(d->hwirq)); + sophgo_pcie_writel_app(sophgo, val, PCIE_INT_EN); + + raw_spin_unlock_irqrestore(&pp->lock, flags); +}; + +static struct irq_chip sophgo_intx_irq_chip =3D { + .name =3D "INTx", + .irq_mask =3D sophgo_intx_irq_mask, + .irq_unmask =3D sophgo_intx_irq_unmask, +}; + +static int sophgo_pcie_intx_map(struct irq_domain *domain, unsigned int ir= q, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &sophgo_intx_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops =3D { + .map =3D sophgo_pcie_intx_map, +}; + +static int sophgo_pcie_init_irq_domain(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct sophgo_pcie *sophgo =3D to_sophgo_pcie(pci); + struct device *dev =3D sophgo->pci.dev; + struct fwnode_handle *intc; + int irq; + + intc =3D device_get_named_child_node(dev, "interrupt-controller"); + if (!intc) { + dev_err(dev, "missing child interrupt-controller node\n"); + return -ENODEV; + } + + irq =3D fwnode_irq_get(intc, 0); + if (irq < 0) { + dev_err(dev, "failed to get INTx irq number\n"); + fwnode_handle_put(intc); + return irq; + } + + sophgo->irq_domain =3D irq_domain_create_linear(intc, PCI_NUM_INTX, + &intx_domain_ops, pp); + fwnode_handle_put(intc); + if (!sophgo->irq_domain) { + dev_err(dev, "failed to get a INTx irq domain\n"); + return -EINVAL; + } + + return irq; +} + +static void sophgo_pcie_msi_enable(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct sophgo_pcie *sophgo =3D to_sophgo_pcie(pci); + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&pp->lock, flags); + + val =3D sophgo_pcie_readl_app(sophgo, PCIE_INT_EN); + val |=3D PCIE_INT_EN_INT_MSI; + sophgo_pcie_writel_app(sophgo, val, PCIE_INT_EN); + + raw_spin_unlock_irqrestore(&pp->lock, flags); +} + +static int sophgo_pcie_host_init(struct dw_pcie_rp *pp) +{ + int irq; + + irq =3D sophgo_pcie_init_irq_domain(pp); + if (irq < 0) + return irq; + + irq_set_chained_handler_and_data(irq, sophgo_pcie_intx_handler, + pp); + + sophgo_pcie_msi_enable(pp); + + return 0; +} + +static const struct dw_pcie_host_ops sophgo_pcie_host_ops =3D { + .init =3D sophgo_pcie_host_init, +}; + +static int sophgo_pcie_clk_init(struct sophgo_pcie *sophgo) +{ + struct device *dev =3D sophgo->pci.dev; + int ret; + + ret =3D devm_clk_bulk_get_all_enabled(dev, &sophgo->clks); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get clocks\n"); + + sophgo->clk_cnt =3D ret; + + return 0; +} + +static int sophgo_pcie_resource_get(struct platform_device *pdev, + struct sophgo_pcie *sophgo) +{ + sophgo->app_base =3D devm_platform_ioremap_resource_byname(pdev, "app"); + if (IS_ERR(sophgo->app_base)) + return dev_err_probe(&pdev->dev, PTR_ERR(sophgo->app_base), + "failed to map app registers\n"); + + return 0; +} + +static int sophgo_pcie_configure_rc(struct sophgo_pcie *sophgo) +{ + struct dw_pcie_rp *pp; + + pp =3D &sophgo->pci.pp; + pp->ops =3D &sophgo_pcie_host_ops; + + return dw_pcie_host_init(pp); +} + +static int sophgo_pcie_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sophgo_pcie *sophgo; + int ret; + + sophgo =3D devm_kzalloc(dev, sizeof(*sophgo), GFP_KERNEL); + if (!sophgo) + return -ENOMEM; + + platform_set_drvdata(pdev, sophgo); + + sophgo->pci.dev =3D dev; + + ret =3D sophgo_pcie_resource_get(pdev, sophgo); + if (ret) + return ret; + + ret =3D sophgo_pcie_clk_init(sophgo); + if (ret) + return ret; + + return sophgo_pcie_configure_rc(sophgo); +} + +static const struct of_device_id sophgo_pcie_of_match[] =3D { + { .compatible =3D "sophgo,sg2044-pcie" }, + { } +}; +MODULE_DEVICE_TABLE(of, sophgo_pcie_of_match); + +static struct platform_driver sophgo_pcie_driver =3D { + .driver =3D { + .name =3D "sophgo-dw-pcie", + .of_match_table =3D sophgo_pcie_of_match, + .suppress_bind_attrs =3D true, + }, + .probe =3D sophgo_pcie_probe, +}; +builtin_platform_driver(sophgo_pcie_driver); --=20 2.49.0