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In some chipsets, it is also a requirement to support higher GPU frequencies. This patch adds support for GPU ACD by sending necessary data to GMU and AOSS. The feature support for the chipset is detected based on devicetree data. Tested-by: Maya Matuszczyk Tested-by: Anthony Ruhier Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 84 ++++++++++++++++++++++++++++++-= ---- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 36 +++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 21 +++++++++ 4 files changed, 132 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index c8711938a5f4478ea02e7a4b336291c91e591358..6bd6d7c67f98b38cb1d23f926b5= e6ccbd7f2ec53 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1064,14 +1064,6 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) =20 gmu->hung =3D false; =20 - /* Notify AOSS about the ACD state (unimplemented for now =3D> disable it= ) */ - if (!IS_ERR(gmu->qmp)) { - ret =3D qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}", - 0 /* Hardcode ACD to be disabled for now */); - if (ret) - dev_err(gmu->dev, "failed to send GPU ACD state\n"); - } - /* Turn on the resources */ pm_runtime_get_sync(gmu->dev); =20 @@ -1671,6 +1663,68 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu = *gmu) return a6xx_gmu_rpmh_votes_init(gmu); } =20 +static int a6xx_gmu_acd_probe(struct a6xx_gmu *gmu) +{ + struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); + struct a6xx_hfi_acd_table *cmd =3D &gmu->acd_table; + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; + int ret, i, cmd_idx =3D 0; + + cmd->version =3D 1; + cmd->stride =3D 1; + cmd->enable_by_level =3D 0; + + /* Skip freq =3D 0 and parse acd-level for rest of the OPPs */ + for (i =3D 1; i < gmu->nr_gpu_freqs; i++) { + struct dev_pm_opp *opp; + struct device_node *np; + unsigned long freq; + u32 val; + + freq =3D gmu->gpu_freqs[i]; + opp =3D dev_pm_opp_find_freq_exact(&gpu->pdev->dev, freq, true); + np =3D dev_pm_opp_get_of_node(opp); + + ret =3D of_property_read_u32(np, "qcom,opp-acd-level", &val); + of_node_put(np); + dev_pm_opp_put(opp); + if (ret =3D=3D -EINVAL) + continue; + else if (ret) { + DRM_DEV_ERROR(gmu->dev, "Unable to read acd level for freq %lu\n", freq= ); + return ret; + } + + cmd->enable_by_level |=3D BIT(i); + cmd->data[cmd_idx++] =3D val; + } + + cmd->num_levels =3D cmd_idx; + + /* It is a problem if qmp node is unavailable when ACD is required */ + if (cmd->enable_by_level && IS_ERR_OR_NULL(gmu->qmp)) { + DRM_DEV_ERROR(gmu->dev, "Unable to send ACD state to AOSS\n"); + return -EINVAL; + } + + /* Otherwise, nothing to do if qmp is unavailable */ + if (IS_ERR_OR_NULL(gmu->qmp)) + return 0; + + /* + * Notify AOSS about the ACD state. AOSS is supposed to assume that ACD i= s disabled on + * system reset. So it is harmless if we couldn't notify 'OFF' state + */ + ret =3D qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}", !!cmd->enab= le_by_level); + if (ret && cmd->enable_by_level) { + DRM_DEV_ERROR(gmu->dev, "Failed to send ACD state to AOSS\n"); + return ret; + } + + return 0; +} + static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) { int ret =3D devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); @@ -1992,7 +2046,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct d= evice_node *node) gmu->qmp =3D qmp_get(gmu->dev); if (IS_ERR(gmu->qmp) && adreno_is_a7xx(adreno_gpu)) { ret =3D PTR_ERR(gmu->qmp); - goto remove_device_link; + goto detach_gxpd; } =20 init_completion(&gmu->pd_gate); @@ -2008,6 +2062,10 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct = device_node *node) /* Get the power levels for the GMU and GPU */ a6xx_gmu_pwrlevels_probe(gmu); =20 + ret =3D a6xx_gmu_acd_probe(gmu); + if (ret) + goto detach_gxpd; + /* Set up the HFI queues */ a6xx_hfi_init(gmu); =20 @@ -2018,7 +2076,13 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct = device_node *node) =20 return 0; =20 -remove_device_link: +detach_gxpd: + if (!IS_ERR_OR_NULL(gmu->gxpd)) + dev_pm_domain_detach(gmu->gxpd, false); + + if (!IS_ERR_OR_NULL(gmu->qmp)) + qmp_put(gmu->qmp); + device_link_del(link); =20 detach_cxpd: diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 0c888b326cfb485400118f3601fa5f1949b03374..b2d4489b40249b1916ab4a42c89= e3f4bdc5c4af9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -93,6 +93,7 @@ struct a6xx_gmu { int nr_gpu_freqs; unsigned long gpu_freqs[GMU_MAX_GX_FREQS]; u32 gx_arc_votes[GMU_MAX_GX_FREQS]; + struct a6xx_hfi_acd_table acd_table; =20 int nr_gpu_bws; unsigned long gpu_bw_table[GMU_MAX_GX_FREQS]; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/ad= reno/a6xx_hfi.c index 0989aee3dd2cf9bc3405c3b25a595c22e6f06387..b256092596fbab86d4eb8c17ac7= c89cf94827105 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -748,6 +748,38 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) NULL, 0); } =20 +#define HFI_FEATURE_ACD 12 + +static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu) +{ + struct a6xx_hfi_acd_table *acd_table =3D &gmu->acd_table; + struct a6xx_hfi_msg_feature_ctrl msg =3D { + .feature =3D HFI_FEATURE_ACD, + .enable =3D 1, + .data =3D 0, + }; + int ret; + + if (!acd_table->enable_by_level) + return 0; + + /* Enable ACD feature at GMU */ + ret =3D a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), N= ULL, 0); + if (ret) { + DRM_DEV_ERROR(gmu->dev, "Unable to enable ACD (%d)\n", ret); + return ret; + } + + /* Send ACD table to GMU */ + ret =3D a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_ACD, acd_table, sizeof(*acd_ta= ble), NULL, 0); + if (ret) { + DRM_DEV_ERROR(gmu->dev, "Unable to ACD table (%d)\n", ret); + return ret; + } + + return 0; +} + static int a6xx_hfi_send_test(struct a6xx_gmu *gmu) { struct a6xx_hfi_msg_test msg =3D { 0 }; @@ -845,6 +877,10 @@ int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_stat= e) if (ret) return ret; =20 + ret =3D a6xx_hfi_enable_acd(gmu); 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So, increase the HFI response timeout to match the downstream driver. Tested-by: Maya Matuszczyk Tested-by: Anthony Ruhier Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/ad= reno/a6xx_hfi.c index b256092596fbab86d4eb8c17ac7c89cf94827105..d0ddae1617c3213a1bb2cb5c18b= 8653c5c1689e6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -109,7 +109,7 @@ static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, = u32 id, u32 seqnum, =20 /* Wait for a response */ ret =3D gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, - val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 5000); + val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 1000000); =20 if (ret) { DRM_DEV_ERROR(gmu->dev, --=20 2.48.1 From nobody Fri Dec 19 06:38:51 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A2751A5B99; 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Correctly handle probe defer for A6x GPUs 2. Ignore other errors because those are okay when GPU ACD is not required. They are checked again during gpu acd probe. Reviewed-by: Konrad Dybcio Tested-by: Maya Matuszczyk Tested-by: Anthony Ruhier Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 6bd6d7c67f98b38cb1d23f926b5e6ccbd7f2ec53..48b4ca8894ba38176481b62b7fd= 1406472369df1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2043,9 +2043,10 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct = device_node *node) goto detach_cxpd; } =20 + /* Other errors are handled during GPU ACD probe */ gmu->qmp =3D qmp_get(gmu->dev); - if (IS_ERR(gmu->qmp) && adreno_is_a7xx(adreno_gpu)) { - ret =3D PTR_ERR(gmu->qmp); + if (PTR_ERR_OR_ZERO(gmu->qmp) =3D=3D -EPROBE_DEFER) { + ret =3D -EPROBE_DEFER; goto detach_gxpd; } =20 --=20 2.48.1 From nobody Fri Dec 19 06:38:51 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9DE31AA1D2; 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Tested-by: Maya Matuszczyk Tested-by: Anthony Ruhier Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++++++ drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 48b4ca8894ba38176481b62b7fd1406472369df1..38c0f8ef85c3d260864541d83ab= e43e49c772c52 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1670,6 +1670,13 @@ static int a6xx_gmu_acd_probe(struct a6xx_gmu *gmu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; int ret, i, cmd_idx =3D 0; + extern bool disable_acd; + + /* Skip ACD probe if requested via module param */ + if (disable_acd) { + DRM_DEV_ERROR(gmu->dev, "Skipping GPU ACD probe\n"); + return 0; + } =20 cmd->version =3D 1; cmd->stride =3D 1; diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 236b25c094cd5d462f4b6653de7b7910985cccb6..f5e1490d07c1868fa21cddb38de= 44c28af5ca0d5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -24,6 +24,10 @@ int enable_preemption =3D -1; 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The new property called "qcom,opp-acd-level" carries a u32 value recommended for each opp needs to be shared to GMU during runtime. Also, update MAINTAINERS file include the new opp-v2-qcom-adreno.yaml. Cc: Rob Clark Tested-by: Maya Matuszczyk Tested-by: Anthony Ruhier Reviewed-by: Krzysztof Kozlowski Signed-off-by: Akhil P Oommen --- .../bindings/opp/opp-v2-qcom-adreno.yaml | 96 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 97 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml = b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a27ba7b663d456f964628a91a66= 1b51a684de1be --- /dev/null +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/opp/opp-v2-qcom-adreno.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno compatible OPP supply + +description: + Adreno GPUs present in Qualcomm's Snapdragon chipsets uses an OPP specif= ic + ACD related information tailored for the specific chipset. This binding + provides the information needed to describe such a hardware value. + +maintainers: + - Rob Clark + +allOf: + - $ref: opp-v2-base.yaml# + +properties: + compatible: + contains: + const: operating-points-v2-adreno + +patternProperties: + '^opp-[0-9]+$': + type: object + additionalProperties: false + + properties: + opp-hz: true + + opp-level: true + + opp-peak-kBps: true + + opp-supported-hw: true + + qcom,opp-acd-level: + description: | + A positive value representing the ACD (Adaptive Clock Distributi= on, + a fancy name for clk throttling during voltage droop) level asso= ciated + with this OPP node. This value is shared to a co-processor insid= e GPU + (called Graphics Management Unit a.k.a GMU) during wake up. It m= ay not + be present for some OPPs and GMU will disable ACD while transiti= oning + to that OPP. This value encodes a voltage threshold, delay cycle= s & + calibration margins which are identified by characterization of = the + SoC. So, it doesn't have any unit. This data is passed to GMU fi= rmware + via 'HFI_H2F_MSG_ACD' packet. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - opp-hz + - opp-level + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2-adreno", "operating-points-v2"; + + opp-687000000 { + opp-hz =3D /bits/ 64 <687000000>; + opp-level =3D ; + opp-peak-kBps =3D <8171875>; + qcom,opp-acd-level =3D <0x882e5ffd>; + }; + + opp-550000000 { + opp-hz =3D /bits/ 64 <550000000>; + opp-level =3D ; + opp-peak-kBps =3D <6074219>; + qcom,opp-acd-level =3D <0xc0285ffd>; + }; + + opp-390000000 { + opp-hz =3D /bits/ 64 <390000000>; + opp-level =3D ; + opp-peak-kBps =3D <3000000>; + qcom,opp-acd-level =3D <0xc0285ffd>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-level =3D ; + opp-peak-kBps =3D <2136719>; + /* Intentionally left out qcom,opp-acd-level property here */ + }; + + }; diff --git a/MAINTAINERS b/MAINTAINERS index c59316109e3f8feacf9628fd1065ed551c4250d5..2d055c8135d1e3dbbf29fe9a552= ac0ee98a8a2a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7512,6 +7512,7 @@ S: Maintained B: https://gitlab.freedesktop.org/drm/msm/-/issues T: git https://gitlab.freedesktop.org/drm/msm.git F: Documentation/devicetree/bindings/display/msm/gpu.yaml +F: Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml F: drivers/gpu/drm/msm/adreno/ F: drivers/gpu/drm/msm/msm_gpu.* F: drivers/gpu/drm/msm/msm_gpu_devfreq.* --=20 2.48.1 From nobody Fri Dec 19 06:38:51 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE4D01A5B99; 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Reviewed-by: Konrad Dybcio Tested-by: Maya Matuszczyk Tested-by: Anthony Ruhier Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 4936fa5b98ff7a9a009e3106f4dba90131251971..a9c8cca1c6356393962cef856b3= dbd9420733999 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3752,60 +3752,69 @@ zap-shader { }; =20 gpu_opp_table: opp-table { - compatible =3D "operating-points-v2"; + compatible =3D "operating-points-v2-adreno", "operating-points-v2"; =20 opp-1100000000 { opp-hz =3D /bits/ 64 <1100000000>; opp-level =3D ; opp-peak-kBps =3D <16500000>; + qcom,opp-acd-level =3D <0xa82a5ffd>; }; =20 opp-1000000000 { opp-hz =3D /bits/ 64 <1000000000>; opp-level =3D ; opp-peak-kBps =3D <14398438>; + qcom,opp-acd-level =3D <0xa82b5ffd>; }; =20 opp-925000000 { opp-hz =3D /bits/ 64 <925000000>; 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Reviewed-by: Konrad Dybcio Tested-by: Maya Matuszczyk Tested-by: Anthony Ruhier Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index a9c8cca1c6356393962cef856b3dbd9420733999..8eddf0c9609871b8660587a22b0= 08212a67604b3 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3754,10 +3754,24 @@ zap-shader { gpu_opp_table: opp-table { compatible =3D "operating-points-v2-adreno", "operating-points-v2"; =20 + opp-1250000000 { + opp-hz =3D /bits/ 64 <1250000000>; + opp-level =3D ; + opp-peak-kBps =3D <16500000>; + qcom,opp-acd-level =3D <0xa82a5ffd>; + }; + + opp-1175000000 { + opp-hz =3D /bits/ 64 <1175000000>; + opp-level =3D ; + opp-peak-kBps =3D <14398438>; + qcom,opp-acd-level =3D <0xa82a5ffd>; + }; + opp-1100000000 { opp-hz =3D /bits/ 64 <1100000000>; opp-level =3D ; - opp-peak-kBps =3D <16500000>; + opp-peak-kBps =3D <14398438>; qcom,opp-acd-level =3D <0xa82a5ffd>; }; =20 --=20 2.48.1