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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2025 15:46:39.4936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d7e51e0-71de-4541-1ee3-08dd89908766 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPF864563BFB Content-Type: text/plain; charset="utf-8" Add SoundWire wake interrupt handling for ACP7.0 & ACP7.1 platforms. Signed-off-by: Vijendar Mukunda Reviewed-by: Ranjani Sridharan Reviewed-by: Bard Liao --- sound/soc/sof/amd/acp-dsp-offset.h | 4 ++ sound/soc/sof/amd/acp.c | 73 +++++++++++++++++++++++++++++- sound/soc/sof/amd/acp.h | 4 ++ 3 files changed, 79 insertions(+), 2 deletions(-) diff --git a/sound/soc/sof/amd/acp-dsp-offset.h b/sound/soc/sof/amd/acp-dsp= -offset.h index e77554f74c20..08583a91afbc 100644 --- a/sound/soc/sof/amd/acp-dsp-offset.h +++ b/sound/soc/sof/amd/acp-dsp-offset.h @@ -135,5 +135,9 @@ #define ACP70_SW0_WAKE_EN 0x1458 #define ACP70_SW1_WAKE_EN 0x1460 #define ACP70_SDW_HOST_WAKE_MASK 0x0C00000 +#define ACP70_SDW0_HOST_WAKE_STAT BIT(24) +#define ACP70_SDW1_HOST_WAKE_STAT BIT(25) +#define ACP70_SDW0_PME_STAT BIT(26) +#define ACP70_SDW1_PME_STAT BIT(27) =20 #endif diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index d62ba4f75e4f..ec904482a294 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -386,6 +386,69 @@ static int acp_memory_init(struct snd_sof_dev *sdev) return 0; } =20 +static void amd_sof_handle_acp70_sdw_wake_event(struct acp_dev_data *adata) +{ + struct amd_sdw_manager *amd_manager; + + if (adata->acp70_sdw0_wake_event) { + amd_manager =3D dev_get_drvdata(&adata->sdw->pdev[0]->dev); + if (amd_manager) + pm_request_resume(amd_manager->dev); + adata->acp70_sdw0_wake_event =3D 0; + } + + if (adata->acp70_sdw1_wake_event) { + amd_manager =3D dev_get_drvdata(&adata->sdw->pdev[1]->dev); + if (amd_manager) + pm_request_resume(amd_manager->dev); + adata->acp70_sdw1_wake_event =3D 0; + } +} + +static int amd_sof_check_and_handle_acp70_sdw_wake_irq(struct snd_sof_dev = *sdev) +{ + const struct sof_amd_acp_desc *desc =3D get_chip_info(sdev->pdata); + struct acp_dev_data *adata =3D sdev->pdata->hw_pdata; + u32 ext_intr_stat1; + int irq_flag =3D 0; + bool sdw_wake_irq =3D false; + + ext_intr_stat1 =3D snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_sta= t1); + if (ext_intr_stat1 & ACP70_SDW0_HOST_WAKE_STAT) { + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, + ACP70_SDW0_HOST_WAKE_STAT); + adata->acp70_sdw0_wake_event =3D true; + sdw_wake_irq =3D true; + } + + if (ext_intr_stat1 & ACP70_SDW1_HOST_WAKE_STAT) { + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, + ACP70_SDW1_HOST_WAKE_STAT); + adata->acp70_sdw1_wake_event =3D true; + sdw_wake_irq =3D true; + } + + if (ext_intr_stat1 & ACP70_SDW0_PME_STAT) { + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN, 0); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW0_PM= E_STAT); + adata->acp70_sdw0_wake_event =3D true; + sdw_wake_irq =3D true; + } + + if (ext_intr_stat1 & ACP70_SDW1_PME_STAT) { + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN, 0); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW1_PM= E_STAT); + adata->acp70_sdw1_wake_event =3D true; + sdw_wake_irq =3D true; + } + + if (sdw_wake_irq) { + amd_sof_handle_acp70_sdw_wake_event(adata); + irq_flag =3D 1; + } + return irq_flag; +} + static irqreturn_t acp_irq_thread(int irq, void *context) { struct snd_sof_dev *sdev =3D context; @@ -418,7 +481,7 @@ static irqreturn_t acp_irq_handler(int irq, void *dev_i= d) struct acp_dev_data *adata =3D sdev->pdata->hw_pdata; unsigned int base =3D desc->dsp_intr_base; unsigned int val; - int irq_flag =3D 0; + int irq_flag =3D 0, wake_irq_flag =3D 0; =20 val =3D snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSE= T); if (val & ACP_DSP_TO_HOST_IRQ) { @@ -456,8 +519,14 @@ static irqreturn_t acp_irq_handler(int irq, void *dev_= id) schedule_work(&amd_manager->amd_sdw_irq_thread); irq_flag =3D 1; } + switch (adata->pci_rev) { + case ACP70_PCI_ID: + case ACP71_PCI_ID: + wake_irq_flag =3D amd_sof_check_and_handle_acp70_sdw_wake_irq(sdev); + break; + } } - if (irq_flag) + if (irq_flag || wake_irq_flag) return IRQ_HANDLED; else return IRQ_NONE; diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index 097454f2b48b..d3c5b2386cdf 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -263,6 +263,10 @@ struct acp_dev_data { bool is_dram_in_use; bool is_sram_in_use; bool sdw_en_stat; + /* acp70_sdw0_wake_event flag set to true when wake irq asserted for SW0 = instance */ + bool acp70_sdw0_wake_event; + /* acp70_sdw1_wake_event flag set to true when wake irq asserted for SW1 = instance */ + bool acp70_sdw1_wake_event; unsigned int pci_rev; }; =20 --=20 2.45.2