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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2025 15:46:12.9478 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fbd304e8-40b3-498d-c0d8-08dd89907791 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8779 Content-Type: text/plain; charset="utf-8" Below mentioned register sequence should be part of acp init sequence. 1) Set ACP clock mux selection register to ACP_ACLK clock source. 2) Enable ACP global interrupt enable register 3) Enable ACP error interrupt mask. ACP reset sequence should contain code related to asserting acp soft reset and release the soft reset. Move the rest of the registers programming to acp init sequence. Signed-off-by: Vijendar Mukunda Reviewed-by: Ranjani Sridharan Reviewed-by: Bard Liao --- sound/soc/sof/amd/acp.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index 615ed7ff3846..2ad5fbf43c8a 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -511,7 +511,6 @@ static int acp_power_on(struct snd_sof_dev *sdev) =20 static int acp_reset(struct snd_sof_dev *sdev) { - const struct sof_amd_acp_desc *desc =3D get_chip_info(sdev->pdata); unsigned int val; int ret; =20 @@ -532,14 +531,6 @@ static int acp_reset(struct snd_sof_dev *sdev) if (ret < 0) dev_err(sdev->dev, "timeout in releasing reset\n"); =20 - if (desc->acp_clkmux_sel) - snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACL= K); - - if (desc->ext_intr_enb) - snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); - - if (desc->ext_intr_cntl) - snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_= MASK); return ret; } =20 @@ -570,6 +561,7 @@ static int acp_dsp_reset(struct snd_sof_dev *sdev) =20 static int acp_init(struct snd_sof_dev *sdev) { + const struct sof_amd_acp_desc *desc =3D get_chip_info(sdev->pdata); struct acp_dev_data *acp_data; int ret; =20 @@ -586,6 +578,16 @@ static int acp_init(struct snd_sof_dev *sdev) ret =3D acp_reset(sdev); if (ret) return ret; + + if (desc->acp_clkmux_sel) + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACL= K); + + if (desc->ext_intr_enb) + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); + + if (desc->ext_intr_cntl) + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_= MASK); + switch (acp_data->pci_rev) { case ACP70_PCI_ID: case ACP71_PCI_ID: --=20 2.45.2