From nobody Sat Feb 7 10:08:23 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67D3C254AF8 for ; Fri, 2 May 2025 12:31:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746189119; cv=none; b=I/SUZc64bNrrxxTQ5n2mrDkXGCP2DbLgSYszeDhf085ryAxAjmVN4kKlPyHDBqQlymaCq7gqREka+y2HJL0O/J3yKd1VuYLrUPIaGoucIFgYsd+BvGCreC6rEKlaqJaHyeho3P81eF9ATDinyl6XVfm8rWk219KsOwqyLBoXtes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746189119; c=relaxed/simple; bh=4nbbHAkkGAtKI9mh8scHvE2TT8W67/3O7vP/JzptVKQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kxkmYwm2guNsKiN1sxSAj3Ez4JRfvA19fNtO76rNN16MZdom9Ix4tAnfDLlBEFAIVBYhfJGnE3m/hg1kq9K5WPaUDL4UFLBaGqeDn1rxphlvRG4zRa4+XTn8ak6Rnp2V7FvMgLHJrIBDR19knYKfdIzy+OLxhEFcJkrQW+25woU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MBEotoHW; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MBEotoHW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746189117; x=1777725117; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4nbbHAkkGAtKI9mh8scHvE2TT8W67/3O7vP/JzptVKQ=; b=MBEotoHWpBWEq2PBIQ5dyN3FljMXHEUPNunrIS2XsPdUYPfw1cHwLDRb al+QoeaLAv9EoorpD5QcM65IYBmX+P6QK1XRywjVAhdcvP7IYFKj3+Hgx 355S2splpxBPu85c3s/r2vbR7wCGE97hi6nfdj/xhpH1ldSFEzbdyzAFU BVdUaEEkqvNSoo1lxbvWnyl4iTmghusOCfB9pJTE7W3GuDnW91GdnKcsT 8DxwD4Z/tVRE2ebiO03Y5nvd75xkJe8Dn6PHHvlFtCKSmLlcxiqwEzJxJ vjldQnDjCuhOLUCr/LmvVokNfT9SakkzxEak8VMhMekC+8WiUN18J6epP Q==; X-CSE-ConnectionGUID: AlN9ERehTCm872kzHmEiTw== X-CSE-MsgGUID: VMVEBqKlRmi2dqJKgQ6/mA== X-IronPort-AV: E=McAfee;i="6700,10204,11421"; a="47955302" X-IronPort-AV: E=Sophos;i="6.15,256,1739865600"; d="scan'208";a="47955302" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2025 05:31:52 -0700 X-CSE-ConnectionGUID: O2/EIfQ4SHijfel5IupSXQ== X-CSE-MsgGUID: EG+iCQXwT0KdGMpLk0HSkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,256,1739865600"; d="scan'208";a="135592036" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa009.fm.intel.com with ESMTP; 02 May 2025 05:31:50 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id ED9A811C; Fri, 02 May 2025 15:31:47 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Ashish Kalra , "Kirill A. Shutemov" , linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , David Woodhouse , Denis Mukhin Subject: [PATCH v1 1/6] x86/boot: Convert early_serial_base to unsigned long Date: Fri, 2 May 2025 15:29:37 +0300 Message-ID: <20250502123145.4066635-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> References: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As a preparatory of adding flexible serial I/O accessors, convert early_serial_base to unsigned long to cover all possible bus addresses on the system. No functional change intended. Signed-off-by: Andy Shevchenko --- arch/x86/boot/boot.h | 2 +- arch/x86/boot/compressed/early_serial_console.c | 2 +- arch/x86/boot/compressed/misc.h | 4 ++-- arch/x86/boot/early_serial_console.c | 6 +++--- arch/x86/boot/tty.c | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h index 38f17a1e1e36..753f429b28cb 100644 --- a/arch/x86/boot/boot.h +++ b/arch/x86/boot/boot.h @@ -274,7 +274,7 @@ int check_knl_erratum(void); int validate_cpu(void); =20 /* early_serial_console.c */ -extern int early_serial_base; +extern unsigned long early_serial_base; void console_init(void); =20 /* edd.c */ diff --git a/arch/x86/boot/compressed/early_serial_console.c b/arch/x86/boo= t/compressed/early_serial_console.c index 70a8d1706d0f..5b8db03f40ad 100644 --- a/arch/x86/boot/compressed/early_serial_console.c +++ b/arch/x86/boot/compressed/early_serial_console.c @@ -1,6 +1,6 @@ #include "misc.h" =20 /* This might be accessed before .bss is cleared, so use .data instead. */ -int early_serial_base __section(".data"); +unsigned long early_serial_base __section(".data"); =20 #include "../early_serial_console.c" diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/mis= c.h index dd8d1a85f671..f083360c84c1 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -127,10 +127,10 @@ extern unsigned char _pgtable[]; =20 #ifdef CONFIG_EARLY_PRINTK /* early_serial_console.c */ -extern int early_serial_base; +extern unsigned long early_serial_base; void console_init(void); #else -static const int early_serial_base; +static const unsigned long early_serial_base; static inline void console_init(void) { } #endif diff --git a/arch/x86/boot/early_serial_console.c b/arch/x86/boot/early_ser= ial_console.c index 023bf1c3de8b..7a7766fa16e5 100644 --- a/arch/x86/boot/early_serial_console.c +++ b/arch/x86/boot/early_serial_console.c @@ -23,7 +23,7 @@ =20 #define DEFAULT_BAUD 9600 =20 -static void early_serial_init(int port, int baud) +static void early_serial_init(unsigned long port, int baud) { unsigned char c; unsigned divisor; @@ -46,9 +46,9 @@ static void early_serial_init(int port, int baud) static void parse_earlyprintk(void) { int baud =3D DEFAULT_BAUD; + unsigned long port =3D 0; char arg[32]; int pos =3D 0; - int port =3D 0; =20 if (cmdline_find_option("earlyprintk", arg, sizeof(arg)) > 0) { char *e; @@ -118,7 +118,7 @@ static void parse_console_uart8250(void) { char optstr[64], *options; int baud =3D DEFAULT_BAUD; - int port =3D 0; + unsigned long port =3D 0; =20 /* * console=3Duart8250,io,0x3f8,115200n8 diff --git a/arch/x86/boot/tty.c b/arch/x86/boot/tty.c index f7eb976b0a4b..e2ab8b8076ef 100644 --- a/arch/x86/boot/tty.c +++ b/arch/x86/boot/tty.c @@ -13,7 +13,7 @@ =20 #include "boot.h" =20 -int early_serial_base; +unsigned long early_serial_base; =20 #define XMTRDY 0x20 =20 --=20 2.47.2 From nobody Sat Feb 7 10:08:23 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26A47211A1E for ; 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X-CSE-ConnectionGUID: gRhHLC7qS7Sg5wCPSFkRFw== X-CSE-MsgGUID: 5PMv0oCsSsGomMqnIjg02g== X-IronPort-AV: E=McAfee;i="6700,10204,11421"; a="47955275" X-IronPort-AV: E=Sophos;i="6.15,256,1739865600"; d="scan'208";a="47955275" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2025 05:31:52 -0700 X-CSE-ConnectionGUID: PYbp9R1zStqGHKMBoxcwTA== X-CSE-MsgGUID: NyyDGcFqTzqmvce4LPpK1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,256,1739865600"; d="scan'208";a="135592033" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa009.fm.intel.com with ESMTP; 02 May 2025 05:31:50 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 0D81A1AE; Fri, 02 May 2025 15:31:48 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Ashish Kalra , "Kirill A. Shutemov" , linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , David Woodhouse , Denis Mukhin Subject: [PATCH v1 2/6] x86/boot: Introduce helpers for serial I/O Date: Fri, 2 May 2025 15:29:38 +0300 Message-ID: <20250502123145.4066635-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> References: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As preparatory to enable earlyprintk on non-standard ports on x86, introduce serial_in() and serial_out() helpers to perform serial I/O. No functional change intended. Signed-off-by: Andy Shevchenko --- arch/x86/boot/boot.h | 2 + .../boot/compressed/early_serial_console.c | 3 + arch/x86/boot/compressed/misc.c | 4 +- arch/x86/boot/compressed/misc.h | 4 ++ arch/x86/boot/early_serial_console.c | 63 +++++++++++++------ arch/x86/boot/tty.c | 7 ++- 6 files changed, 61 insertions(+), 22 deletions(-) diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h index 753f429b28cb..6688c2053707 100644 --- a/arch/x86/boot/boot.h +++ b/arch/x86/boot/boot.h @@ -274,6 +274,8 @@ int check_knl_erratum(void); int validate_cpu(void); =20 /* early_serial_console.c */ +extern unsigned int (*serial_in)(unsigned long addr, int offset); +extern void (*serial_out)(unsigned long addr, int offset, int value); extern unsigned long early_serial_base; void console_init(void); =20 diff --git a/arch/x86/boot/compressed/early_serial_console.c b/arch/x86/boo= t/compressed/early_serial_console.c index 5b8db03f40ad..a5e0459c3d2f 100644 --- a/arch/x86/boot/compressed/early_serial_console.c +++ b/arch/x86/boot/compressed/early_serial_console.c @@ -1,5 +1,8 @@ #include "misc.h" =20 +unsigned int (*serial_in)(unsigned long addr, int offset); +void (*serial_out)(unsigned long addr, int offset, int value); + /* This might be accessed before .bss is cleared, so use .data instead. */ unsigned long early_serial_base __section(".data"); =20 diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/mis= c.c index 94b5991da001..056fa5f01598 100644 --- a/arch/x86/boot/compressed/misc.c +++ b/arch/x86/boot/compressed/misc.c @@ -109,10 +109,10 @@ static void serial_putchar(int ch) { unsigned timeout =3D 0xffff; =20 - while ((inb(early_serial_base + LSR) & XMTRDY) =3D=3D 0 && --timeout) + while ((serial_in(early_serial_base, LSR) & XMTRDY) =3D=3D 0 && --timeout) cpu_relax(); =20 - outb(ch, early_serial_base + TXR); + serial_out(early_serial_base, TXR, ch); } =20 void __putstr(const char *s) diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/mis= c.h index f083360c84c1..a70e5f31765b 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -127,9 +127,13 @@ extern unsigned char _pgtable[]; =20 #ifdef CONFIG_EARLY_PRINTK /* early_serial_console.c */ +extern unsigned int (*serial_in)(unsigned long addr, int offset); +extern void (*serial_out)(unsigned long addr, int offset, int value); extern unsigned long early_serial_base; void console_init(void); #else +static unsigned int (*serial_in)(unsigned long addr, int offset); +static void (*serial_out)(unsigned long addr, int offset, int value); static const unsigned long early_serial_base; static inline void console_init(void) { } diff --git a/arch/x86/boot/early_serial_console.c b/arch/x86/boot/early_ser= ial_console.c index 7a7766fa16e5..f52a14284854 100644 --- a/arch/x86/boot/early_serial_console.c +++ b/arch/x86/boot/early_serial_console.c @@ -23,22 +23,45 @@ =20 #define DEFAULT_BAUD 9600 =20 -static void early_serial_init(unsigned long port, int baud) +static unsigned int io_serial_in(unsigned long addr, int offset) +{ + return inb(addr + offset); +} + +static void io_serial_out(unsigned long addr, int offset, int value) +{ + outb(value, addr + offset); +} + +static void early_serial_configure(unsigned long port, int baud) { unsigned char c; unsigned divisor; =20 - outb(0x3, port + LCR); /* 8n1 */ - outb(0, port + IER); /* no interrupt */ - outb(0, port + FCR); /* no fifo */ - outb(0x3, port + MCR); /* DTR + RTS */ + serial_out(port, LCR, 0x3); /* 8n1 */ + serial_out(port, IER, 0); /* no interrupt */ + serial_out(port, FCR, 0); /* no fifo */ + serial_out(port, MCR, 0x3); /* DTR + RTS */ =20 divisor =3D 115200 / baud; - c =3D inb(port + LCR); - outb(c | DLAB, port + LCR); - outb(divisor & 0xff, port + DLL); - outb((divisor >> 8) & 0xff, port + DLH); - outb(c & ~DLAB, port + LCR); + c =3D serial_in(port, LCR); + serial_out(port, LCR, c | DLAB); + serial_out(port, DLL, divisor & 0xff); + serial_out(port, DLH, (divisor >> 8) & 0xff); + serial_out(port, LCR, c & ~DLAB); +} + +/* Assign serial I/O accessors */ +static void early_serial_use_io_accessors(void) +{ + /* These will always be IO based ports */ + serial_in =3D io_serial_in; + serial_out =3D io_serial_out; +} + +static void early_serial_init(unsigned long port, int baud) +{ + early_serial_configure(port, baud); =20 early_serial_base =3D port; } @@ -73,6 +96,7 @@ static void parse_earlyprintk(void) port =3D DEFAULT_SERIAL_PORT; else pos =3D e - arg; + early_serial_use_io_accessors(); } else if (!strncmp(arg + pos, "ttyS", 4)) { static const int bases[] =3D { 0x3f8, 0x2f8 }; int idx =3D 0; @@ -84,6 +108,7 @@ static void parse_earlyprintk(void) idx =3D 1; =20 port =3D bases[idx]; + early_serial_use_io_accessors(); } =20 if (arg[pos] =3D=3D ',') @@ -104,11 +129,11 @@ static unsigned int probe_baud(int port) unsigned char lcr, dll, dlh; unsigned int quot; =20 - lcr =3D inb(port + LCR); - outb(lcr | DLAB, port + LCR); - dll =3D inb(port + DLL); - dlh =3D inb(port + DLH); - outb(lcr, port + LCR); + lcr =3D serial_in(port, LCR); + serial_out(port, LCR, lcr | DLAB); + dll =3D serial_in(port, DLL); + dlh =3D serial_in(port, DLH); + serial_out(port, LCR, lcr); quot =3D (dlh << 8) | dll; =20 return BASE_BAUD / quot; @@ -129,11 +154,13 @@ static void parse_console_uart8250(void) =20 options =3D optstr; =20 - if (!strncmp(options, "uart8250,io,", 12)) + if (!strncmp(options, "uart8250,io,", 12)) { port =3D simple_strtoull(options + 12, &options, 0); - else if (!strncmp(options, "uart,io,", 8)) + early_serial_use_io_accessors(); + } else if (!strncmp(options, "uart,io,", 8)) { port =3D simple_strtoull(options + 8, &options, 0); - else + early_serial_use_io_accessors(); + } else return; =20 if (options && (options[0] =3D=3D ',')) diff --git a/arch/x86/boot/tty.c b/arch/x86/boot/tty.c index e2ab8b8076ef..eb0eacd88db7 100644 --- a/arch/x86/boot/tty.c +++ b/arch/x86/boot/tty.c @@ -13,6 +13,9 @@ =20 #include "boot.h" =20 +unsigned int (*serial_in)(unsigned long addr, int offset); +void (*serial_out)(unsigned long addr, int offset, int value); + unsigned long early_serial_base; =20 #define XMTRDY 0x20 @@ -29,10 +32,10 @@ static void __section(".inittext") serial_putchar(int c= h) { unsigned timeout =3D 0xffff; =20 - while ((inb(early_serial_base + LSR) & XMTRDY) =3D=3D 0 && --timeout) + while ((serial_in(early_serial_base, LSR) & XMTRDY) =3D=3D 0 && --timeout) cpu_relax(); =20 - outb(ch, early_serial_base + TXR); + serial_out(early_serial_base, TXR, ch); } =20 static void __section(".inittext") bios_putchar(int ch) --=20 2.47.2 From nobody Sat Feb 7 10:08:23 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D342B252914 for ; Fri, 2 May 2025 12:31:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746189117; cv=none; b=qeMlDb31JnExsWAMUXmnXNhOQFW7rlUFLIt792CkZyonfrK0dRtKt8zT0z+O2eQmxul6pVTNgKIAJ9Rkga8Ek3isP671vBJet5mhEsYG41+mqQcVUqqaCPxcr/LUvTGStYgKUK/Yjr7sTI4Lw5Cb+YI54gzN4FSNdXHuugM8dC8= ARC-Message-Signature: i=1; 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d="scan'208";a="135592034" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa009.fm.intel.com with ESMTP; 02 May 2025 05:31:50 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 17F771D2; Fri, 02 May 2025 15:31:48 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Ashish Kalra , "Kirill A. Shutemov" , linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , David Woodhouse , Denis Mukhin Subject: [PATCH v1 3/6] x86/boot: Split out parse_serial_port() helper for earlyprintk Date: Fri, 2 May 2025 15:29:39 +0300 Message-ID: <20250502123145.4066635-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> References: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The newly introduced helper will be used later on to parse serial port in different type of earlyprintk command line arguments. No functional change intended. Signed-off-by: Andy Shevchenko --- arch/x86/boot/early_serial_console.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/x86/boot/early_serial_console.c b/arch/x86/boot/early_ser= ial_console.c index f52a14284854..fa6520719a1e 100644 --- a/arch/x86/boot/early_serial_console.c +++ b/arch/x86/boot/early_serial_console.c @@ -66,6 +66,20 @@ static void early_serial_init(unsigned long port, int ba= ud) early_serial_base =3D port; } =20 +static unsigned long parse_serial_port(const char *arg, int off, int *pos) +{ + unsigned long port; + char *e; + + port =3D simple_strtoull(arg + off, &e, 16); + if (port =3D=3D 0 || arg + off =3D=3D e) + port =3D DEFAULT_SERIAL_PORT; + else + *pos =3D e - arg; + + return port; +} + static void parse_earlyprintk(void) { int baud =3D DEFAULT_BAUD; @@ -91,11 +105,7 @@ static void parse_earlyprintk(void) * "ttyS0,115200" */ if (pos =3D=3D 7 && !strncmp(arg + pos, "0x", 2)) { - port =3D simple_strtoull(arg + pos, &e, 16); - if (port =3D=3D 0 || arg + pos =3D=3D e) - port =3D DEFAULT_SERIAL_PORT; - else - pos =3D e - arg; + port =3D parse_serial_port(arg, pos + 0, &pos); early_serial_use_io_accessors(); } else if (!strncmp(arg + pos, "ttyS", 4)) { static const int bases[] =3D { 0x3f8, 0x2f8 }; --=20 2.47.2 From nobody Sat Feb 7 10:08:23 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5DB1251782 for ; Fri, 2 May 2025 12:31:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746189115; cv=none; b=XvWLSKTXGPFqo4kivDOHQJwV7VjBj5DxiQs51IOqTOZLtTP/XXHg60EKbyGnubIQD1h+6dIZB56VhO0ASyvTBYx48rE5SVtVsCIEZEuuX2ZPdxwui1T1Ryv0WM2iHhjwuUTO3SoH2++MtneItISt2Dt+6PRBexDDg+4npzcIodI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746189115; c=relaxed/simple; bh=SfEf/D6DeVLe4pFODRIksQjIcj8tNq2k+CUGb0pzMjA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Rpp8Z3e1NKD+EY+Q4cNpX7TRcaUTlo3kBPoBav2WpQY3BMFvS3OoCMa2K0fSBjbHziX9OEPwGEf83z9AsTDYIG9RIwo/TxScvuw9dMzHgMYD8Z+FAR7gotc2i90ipdMzWQq3Y0cON7P3kF6AF94pK+cJ0KFSBPy2TeoVonYKxng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QNcRrK9s; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QNcRrK9s" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746189114; x=1777725114; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SfEf/D6DeVLe4pFODRIksQjIcj8tNq2k+CUGb0pzMjA=; b=QNcRrK9sae56bk4yR8Xqwa0g0kxuvkyoNUTPi6ez99XLPqdv6aUzL3hG 4n1r5Djy/0YumwqPBCEH4o4UA908XFO3zLh6u8aP0nimk9xcr+rNI13TZ WCKIhxBJEMyWabiefb55XjryNtUMq8b/M2bevamI4FGdiFlr3DomfGp+n uq4ovk8VG/mWk9IjTDkAzp4Exoggi0OHBYvhT/4y91jm+Ht4a+DGWxhHg c9hQC8Zqqie+uSNKaen00vjYBNUdPWcTDQ8ADB6S7/Mh6nUDTmayU80vf 1KV5MyIs7JakEa933+g5fYrvrKm2v8pPLAkVDV1jwTWJR5rXMiIAMM9ZN g==; X-CSE-ConnectionGUID: mFMrQUzzTtCDBSr73GsrJQ== X-CSE-MsgGUID: CAjU2obhS7Ozv0O1BRM3yw== X-IronPort-AV: E=McAfee;i="6700,10204,11421"; a="58078085" X-IronPort-AV: E=Sophos;i="6.15,256,1739865600"; d="scan'208";a="58078085" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2025 05:31:53 -0700 X-CSE-ConnectionGUID: YsU9gudVTGWtTVlfidaB4g== X-CSE-MsgGUID: GXFQTWjySWGPXxxcpw7myQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,256,1739865600"; d="scan'208";a="135613029" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa008.jf.intel.com with ESMTP; 02 May 2025 05:31:50 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 237E6224; Fri, 02 May 2025 15:31:48 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Ashish Kalra , "Kirill A. Shutemov" , linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , David Woodhouse , Denis Mukhin Subject: [PATCH v1 4/6] x86/boot: Allow longer parameter list for earlyprintk Date: Fri, 2 May 2025 15:29:40 +0300 Message-ID: <20250502123145.4066635-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> References: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow longer parameter list, up to 64 characters, for earlyprintk to support new coming parameters. If the parsed string is longer than this buffer it will be cut up by the buffer size. No functional change intended. Note, that 'console' case is already covered. Signed-off-by: Andy Shevchenko --- arch/x86/boot/early_serial_console.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/boot/early_serial_console.c b/arch/x86/boot/early_ser= ial_console.c index fa6520719a1e..6841f14346c2 100644 --- a/arch/x86/boot/early_serial_console.c +++ b/arch/x86/boot/early_serial_console.c @@ -84,7 +84,7 @@ static void parse_earlyprintk(void) { int baud =3D DEFAULT_BAUD; unsigned long port =3D 0; - char arg[32]; + char arg[64]; int pos =3D 0; =20 if (cmdline_find_option("earlyprintk", arg, sizeof(arg)) > 0) { --=20 2.47.2 From nobody Sat Feb 7 10:08:23 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 297F3253B50 for ; Fri, 2 May 2025 12:31:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746189117; cv=none; b=XUyEd7YjTIlDrOUjng6pHp3dl63jlN1wxo+pZpBhOjjudrAfOKm5q8wtkp6aUMuHX3Mv5BbM9/w0Cr3e57yA9JOW9cDsIdn+2t5IkxkEMdIcl7KQHbwgzWBTeHtexIl0ydSREGqdd3O9QzuQK5oS5UwCwO8CNAJEwR1rGWJ0EVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746189117; c=relaxed/simple; bh=HpVFos1tTHg5dfkSMhwdAOhwfisXCl7ONc0joAaTi6I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rroT6D9StfsUPBOuQpPyUmSotCZfvQPtZ8NfU+ePm3Prnk+eaADePzaQW70mG5hwLQwcBXT5vJl21fl6DeNMuG8MfndCTaoTu3UvvnithgV6Uj4rKXWbtU3uUUSz7izoC5Eqxa/dqpKi5Ak04NlCCyz3aoVq9XNjjBo6bTnLNNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QJhr988I; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QJhr988I" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746189117; x=1777725117; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HpVFos1tTHg5dfkSMhwdAOhwfisXCl7ONc0joAaTi6I=; b=QJhr988IJquduPrWrOoQ/CjpCG+B50Z3dUB/QGwY86aZlB0VqOe4YD38 ypQhl6vPjbqhjFpDa2xSBXJkMEKFVKxJwLL1trCTqVQS2zYCHHgBVY24U vsehaTXudnzVRpqGZcGYkz+OPqKDSld3Xs3RX1zAKSl0hxmFTpYM+Xh5e nJvHgaepKcqOKdFqZcqo1SkzIhuSSFPJWBZVATBQzFVA7+70ye5dFh2wa PkUz3cpp63JryKCQBRED1hz4SIa48qodopHKq8ERQK86PJaUUzzOyuhDI hr65l/RzolwJ3PEkTRav1VMmHbNxi0x52FoCbKosgjvTivmKyxa7hXkW8 Q==; X-CSE-ConnectionGUID: JFDTrVcIQ0O0ofspU7tDag== X-CSE-MsgGUID: /f+15D9FRZStZS9poH9Cgw== X-IronPort-AV: E=McAfee;i="6700,10204,11421"; a="58078092" X-IronPort-AV: E=Sophos;i="6.15,256,1739865600"; d="scan'208";a="58078092" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2025 05:31:56 -0700 X-CSE-ConnectionGUID: l2LEmdW9SEqXgRErr/ub/w== X-CSE-MsgGUID: 3/5nASF8QkOgB5TF5EeL+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,256,1739865600"; d="scan'208";a="135613043" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa008.jf.intel.com with ESMTP; 02 May 2025 05:31:53 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 33902260; Fri, 02 May 2025 15:31:48 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Ashish Kalra , "Kirill A. Shutemov" , linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , David Woodhouse , Denis Mukhin Subject: [PATCH v1 5/6] x86/boot: Also share MMIO accessors Date: Fri, 2 May 2025 15:29:41 +0300 Message-ID: <20250502123145.4066635-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> References: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the enabling an arbitrary MMIO for earlyprintk, share MMIO accessors with a boot code. Signed-off-by: Andy Shevchenko --- arch/x86/include/asm/io.h | 65 ------------------------------ arch/x86/include/asm/shared/io.h | 68 ++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 65 deletions(-) diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index e889c3bab5a2..e6ca50fbcbbf 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -44,71 +44,6 @@ #include #include =20 -#define build_mmio_read(name, size, type, reg, barrier) \ -static inline type name(const volatile void __iomem *addr) \ -{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \ -:"m" (*(volatile type __force *)addr) barrier); return ret; } - -#define build_mmio_write(name, size, type, reg, barrier) \ -static inline void name(type val, volatile void __iomem *addr) \ -{ asm volatile("mov" size " %0,%1": :reg (val), \ -"m" (*(volatile type __force *)addr) barrier); } - -build_mmio_read(readb, "b", unsigned char, "=3Dq", :"memory") -build_mmio_read(readw, "w", unsigned short, "=3Dr", :"memory") -build_mmio_read(readl, "l", unsigned int, "=3Dr", :"memory") - -build_mmio_read(__readb, "b", unsigned char, "=3Dq", ) -build_mmio_read(__readw, "w", unsigned short, "=3Dr", ) -build_mmio_read(__readl, "l", unsigned int, "=3Dr", ) - -build_mmio_write(writeb, "b", unsigned char, "q", :"memory") -build_mmio_write(writew, "w", unsigned short, "r", :"memory") -build_mmio_write(writel, "l", unsigned int, "r", :"memory") - -build_mmio_write(__writeb, "b", unsigned char, "q", ) -build_mmio_write(__writew, "w", unsigned short, "r", ) -build_mmio_write(__writel, "l", unsigned int, "r", ) - -#define readb readb -#define readw readw -#define readl readl -#define readb_relaxed(a) __readb(a) -#define readw_relaxed(a) __readw(a) -#define readl_relaxed(a) __readl(a) -#define __raw_readb __readb -#define __raw_readw __readw -#define __raw_readl __readl - -#define writeb writeb -#define writew writew -#define writel writel -#define writeb_relaxed(v, a) __writeb(v, a) -#define writew_relaxed(v, a) __writew(v, a) -#define writel_relaxed(v, a) __writel(v, a) -#define __raw_writeb __writeb -#define __raw_writew __writew -#define __raw_writel __writel - -#ifdef CONFIG_X86_64 - -build_mmio_read(readq, "q", u64, "=3Dr", :"memory") -build_mmio_read(__readq, "q", u64, "=3Dr", ) -build_mmio_write(writeq, "q", u64, "r", :"memory") -build_mmio_write(__writeq, "q", u64, "r", ) - -#define readq_relaxed(a) __readq(a) -#define writeq_relaxed(v, a) __writeq(v, a) - -#define __raw_readq __readq -#define __raw_writeq __writeq - -/* Let people know that we have them */ -#define readq readq -#define writeq writeq - -#endif - #define ARCH_HAS_VALID_PHYS_ADDR_RANGE extern int valid_phys_addr_range(phys_addr_t addr, size_t size); extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); diff --git a/arch/x86/include/asm/shared/io.h b/arch/x86/include/asm/shared= /io.h index 8009d781c2f9..35437ee26e21 100644 --- a/arch/x86/include/asm/shared/io.h +++ b/arch/x86/include/asm/shared/io.h @@ -31,4 +31,72 @@ BUILDIO(l, , u32) #define outw __outw #define outl __outl =20 +#define build_mmio_read(name, size, type, reg, barrier) \ +static inline type name(const volatile void __iomem *addr) \ +{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \ +:"m" (*(volatile type __force *)addr) barrier); return ret; } + +#define build_mmio_write(name, size, type, reg, barrier) \ +static inline void name(type val, volatile void __iomem *addr) \ +{ asm volatile("mov" size " %0,%1": :reg (val), \ +"m" (*(volatile type __force *)addr) barrier); } + +build_mmio_read(readb, "b", unsigned char, "=3Dq", :"memory") +build_mmio_read(readw, "w", unsigned short, "=3Dr", :"memory") +build_mmio_read(readl, "l", unsigned int, "=3Dr", :"memory") + +build_mmio_read(__readb, "b", unsigned char, "=3Dq", ) +build_mmio_read(__readw, "w", unsigned short, "=3Dr", ) +build_mmio_read(__readl, "l", unsigned int, "=3Dr", ) + +build_mmio_write(writeb, "b", unsigned char, "q", :"memory") +build_mmio_write(writew, "w", unsigned short, "r", :"memory") +build_mmio_write(writel, "l", unsigned int, "r", :"memory") + +build_mmio_write(__writeb, "b", unsigned char, "q", ) +build_mmio_write(__writew, "w", unsigned short, "r", ) +build_mmio_write(__writel, "l", unsigned int, "r", ) + +#define readb readb +#define readw readw +#define readl readl +#define readb_relaxed(a) __readb(a) +#define readw_relaxed(a) __readw(a) +#define readl_relaxed(a) __readl(a) +#define __raw_readb __readb +#define __raw_readw __readw +#define __raw_readl __readl + +#define writeb writeb +#define writew writew +#define writel writel +#define writeb_relaxed(v, a) __writeb(v, a) +#define writew_relaxed(v, a) __writew(v, a) +#define writel_relaxed(v, a) __writel(v, a) +#define __raw_writeb __writeb +#define __raw_writew __writew +#define __raw_writel __writel + +#ifdef CONFIG_X86_64 + +build_mmio_read(readq, "q", u64, "=3Dr", :"memory") +build_mmio_read(__readq, "q", u64, "=3Dr", ) +build_mmio_write(writeq, "q", u64, "r", :"memory") +build_mmio_write(__writeq, "q", u64, "r", ) + +#define readq_relaxed(a) __readq(a) +#define writeq_relaxed(v, a) __writeq(v, a) + +#define __raw_readq __readq +#define __raw_writeq __writeq + +/* Let people know that we have them */ +#define readq readq +#define writeq writeq + +#endif + +#undef build_mmio_write +#undef build_mmio_read + #endif --=20 2.47.2 From nobody Sat Feb 7 10:08:23 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDC3A2550B2 for ; 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X-CSE-ConnectionGUID: R+sJC4n3S+yxhAcY4rqG8g== X-CSE-MsgGUID: 8KcZTNDUR8uuPPg9Ppk9pg== X-IronPort-AV: E=McAfee;i="6700,10204,11421"; a="47955312" X-IronPort-AV: E=Sophos;i="6.15,256,1739865600"; d="scan'208";a="47955312" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2025 05:31:56 -0700 X-CSE-ConnectionGUID: sbJx785xQzanfS08EVNpwQ== X-CSE-MsgGUID: 5xTkwiscQK6sj942VCs+iw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,256,1739865600"; d="scan'208";a="135592037" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa009.fm.intel.com with ESMTP; 02 May 2025 05:31:54 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 3C3201AC; Fri, 02 May 2025 15:31:48 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Ashish Kalra , "Kirill A. Shutemov" , linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , David Woodhouse , Denis Mukhin Subject: [PATCH v1 6/6] x86/boot: Introduce MMIO accessors and their support in earlyprintk Date: Fri, 2 May 2025 15:29:42 +0300 Message-ID: <20250502123145.4066635-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> References: <20250502123145.4066635-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If user supplied serial base address via kernel command line and at the same time the word 'mmio' is present, use MMIO accessors. Signed-off-by: Andy Shevchenko --- arch/x86/boot/early_serial_console.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/x86/boot/early_serial_console.c b/arch/x86/boot/early_ser= ial_console.c index 6841f14346c2..fa8eb0b4542e 100644 --- a/arch/x86/boot/early_serial_console.c +++ b/arch/x86/boot/early_serial_console.c @@ -33,6 +33,20 @@ static void io_serial_out(unsigned long addr, int offset= , int value) outb(value, addr + offset); } =20 +static void mem8_serial_out(unsigned long addr, int offset, int value) +{ + u8 __iomem *vaddr =3D (u8 __iomem *)addr; + /* shift implied by pointer type */ + writeb(value, vaddr + offset); +} + +static unsigned int mem8_serial_in(unsigned long addr, int offset) +{ + u8 __iomem *vaddr =3D (u8 __iomem *)addr; + /* shift implied by pointer type */ + return readb(vaddr + offset); +} + static void early_serial_configure(unsigned long port, int baud) { unsigned char c; @@ -59,6 +73,13 @@ static void early_serial_use_io_accessors(void) serial_out =3D io_serial_out; } =20 +static void early_serial_use_mmio_accessors(void) +{ + /* It is memory mapped - assume 8-bit alignment */ + serial_in =3D mem8_serial_in; + serial_out =3D mem8_serial_out; +} + static void early_serial_init(unsigned long port, int baud) { early_serial_configure(port, baud); @@ -101,12 +122,16 @@ static void parse_earlyprintk(void) /* * make sure we have * "serial,0x3f8,115200" + * "serial,mmio,0xff010180,115200" * "serial,ttyS0,115200" * "ttyS0,115200" */ if (pos =3D=3D 7 && !strncmp(arg + pos, "0x", 2)) { port =3D parse_serial_port(arg, pos + 0, &pos); early_serial_use_io_accessors(); + } else if (pos =3D=3D 7 && !strncmp(arg + pos, "mmio,0x", 7)) { + port =3D parse_serial_port(arg, pos + 5, &pos); + early_serial_use_mmio_accessors(); } else if (!strncmp(arg + pos, "ttyS", 4)) { static const int bases[] =3D { 0x3f8, 0x2f8 }; int idx =3D 0; --=20 2.47.2