From nobody Sat Feb 7 08:53:14 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACC5822616C; Fri, 2 May 2025 08:59:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176381; cv=none; b=frIaeS+LJCik5doqjvTX/p4lf1ipnQUADBYeCOsgNSbI8+Q0xPl0+xpTGBiAGuqDYk2/WA/Ak6bnvhGNyg7GaQrE1ALWnva9rw+vblPuVf2KRi1TrjiBbWQsU9HlrVeKapXC7AfQKMxzPyAyJNrxGOmZAm6jvlhYvKYyWRQQZNU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176381; c=relaxed/simple; bh=WVpV3q0OYwMN+CjVI1AHM/Qbbb3lfPm8ySSP6xgS8o4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VKRDDeYdW/t6ziXtIA6ak/6IhX9l7hzP2RrbkuyGLfy1cur6OLVqRBqQCIGH1q7+kEaYIFb+EFrc/5vBpWCAEy7g/9UQ8Zs37KIaJxLAZue8NRUvsMminXtoBl7SfALRB/+M/7lYGv568+I5gFAnS9vjyj4hEQsFyS5QVak1qcs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=nuAhJU2F; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="nuAhJU2F" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5428JKRo008742; Fri, 2 May 2025 04:59:31 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=Kfh1I fHw0hy2pIBIku8y2ysi5iu0CKzYyyDT7gUbX1U=; b=nuAhJU2FTVOMopVsBNcTj Yu6+qZnE6kFu+1vtmG54NTA53bW1v8pj4Mc+YuLnYPI3YCuRsh7jJOY14yM3UoSC TfpbB9xUv07/woFTuyyaEfx0X3idGO5TePgkApTBqy0eslGGXZEDKBgx+apN0502 3fxNXjNDLgqZB6KsJfEGenC4JnCWVsRdnUAOe7dvQIdeFYu+Dfa22rGKqOr4e04j MwcwQJJqAdIsk3CcNSjBL8kK8ORTUf12luxMXfHakkfMEW/VYf07UX5aX4MlfzSo UR1A5s8lk+sGSBp7efbDtWvuliZEax7b2MJoipg9iJwa8fPrMK2GsMHFlinrZzQw A== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46b6u1kww6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 May 2025 04:59:31 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 5428xUsJ029942 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 May 2025 04:59:30 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:30 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 2 May 2025 04:59:29 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.211]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 5428xL7K015723; Fri, 2 May 2025 04:59:26 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= Subject: [PATCH v4 01/10] iio: backend: add support for filter config Date: Fri, 2 May 2025 11:58:56 +0300 Message-ID: <20250502085905.24926-2-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502085905.24926-1-antoniu.miclaus@analog.com> References: <20250502085905.24926-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=RuDFLDmK c=1 sm=1 tr=0 ts=68148973 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=UD3WkZFi8vOiteFn2FEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: LYlJPj8-SlyFvvS0nUBNUil8boUXJL8O X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDA2OSBTYWx0ZWRfX5+d/R3Wv7PsS +lxz7pV17a8MThKzUwqS1tQWCzFRmZXIGpXisJHyM16cSCr33v331RQ05O9S7Ub0dEQ5R/DrdPl i5NWet/o6bTN3NyKm1J2pjFN6b8f3aPrwLh/C2QDaU1VzpiH86bmKT1EPCMDP5Hk4aCk+Y/s+pg PfBljXEZew8dVtjhFtpj5F6UpGgwL7DckKUkJP4o3/PSkDqLM2XfekqYP1PKZ8IDGX8A36zrpqz lqeKHrpn39cziDnd2lGpZiG6VMP9TSuRZDks9vV0ydk6m0vNQ9xt55zZFdjzQdgW1Ge5l2MfNWO ZUWMbjEe0Y+vA2e8UQ05socAXtTP1cYWT3VU095p1hTme8xW22vzKLST6GHwdzQhBiflK7yvXQ9 6S5fW58Yg/6wZ3N3wmhw1WoC8kV7BnKBonV5ohUiEQu6ybGYBcDGtJw2nl4OuqOIaTjHC1Yy X-Proofpoint-ORIG-GUID: LYlJPj8-SlyFvvS0nUBNUil8boUXJL8O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 phishscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020069 Add backend support for digital filter type selection. This setting can be adjusted within the IP cores interfacing devices. The IP core can be configured based on the state of the actual digital filter configuration of the part. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- no changes in v4. drivers/iio/industrialio-backend.c | 18 ++++++++++++++++++ include/linux/iio/backend.h | 13 +++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index d4ad36f54090..038c9e1e2857 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -778,6 +778,24 @@ static int __devm_iio_backend_get(struct device *dev, = struct iio_backend *back) return 0; } =20 +/** + * iio_backend_filter_type_set - Set filter type + * @back: Backend device + * @type: Filter type. + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_filter_type_set(struct iio_backend *back, + enum iio_backend_filter_type type) +{ + if (type >=3D IIO_BACKEND_FILTER_TYPE_MAX) + return -EINVAL; + + return iio_backend_op_call(back, filter_type_set, type); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_filter_type_set, "IIO_BACKEND"); + /** * iio_backend_ddr_enable - Enable interface DDR (Double Data Rate) mode * @back: Backend device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index e45b7dfbec35..5526800f5d4a 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -76,6 +76,14 @@ enum iio_backend_interface_type { IIO_BACKEND_INTERFACE_MAX }; =20 +enum iio_backend_filter_type { + IIO_BACKEND_FILTER_TYPE_DISABLED, + IIO_BACKEND_FILTER_TYPE_SINC1, + IIO_BACKEND_FILTER_TYPE_SINC5, + IIO_BACKEND_FILTER_TYPE_SINC5_PLUS_COMP, + IIO_BACKEND_FILTER_TYPE_MAX +}; + /** * struct iio_backend_ops - operations structure for an iio_backend * @enable: Enable backend. @@ -100,6 +108,7 @@ enum iio_backend_interface_type { * @read_raw: Read a channel attribute from a backend device * @debugfs_print_chan_status: Print channel status into a buffer. * @debugfs_reg_access: Read or write register value of backend. + * @filter_type_set: Set filter type. * @ddr_enable: Enable interface DDR (Double Data Rate) mode. * @ddr_disable: Disable interface DDR (Double Data Rate) mode. * @data_stream_enable: Enable data stream. @@ -150,6 +159,8 @@ struct iio_backend_ops { size_t len); int (*debugfs_reg_access)(struct iio_backend *back, unsigned int reg, unsigned int writeval, unsigned int *readval); + int (*filter_type_set)(struct iio_backend *back, + enum iio_backend_filter_type type); int (*ddr_enable)(struct iio_backend *back); int (*ddr_disable)(struct iio_backend *back); int (*data_stream_enable)(struct iio_backend *back); @@ -190,6 +201,8 @@ int iio_backend_data_sample_trigger(struct iio_backend = *back, int devm_iio_backend_request_buffer(struct device *dev, struct iio_backend *back, struct iio_dev *indio_dev); +int iio_backend_filter_type_set(struct iio_backend *back, + enum iio_backend_filter_type type); int iio_backend_ddr_enable(struct iio_backend *back); int iio_backend_ddr_disable(struct iio_backend *back); int iio_backend_data_stream_enable(struct iio_backend *back); --=20 2.49.0 From nobody Sat Feb 7 08:53:14 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84C0022FACA; Fri, 2 May 2025 08:59:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176385; cv=none; b=ZilXHPEQdQxtwArnlGnDdjCINBh9yhipXkeSVSKWJuGTm2DSkwtvFtN48kplfYOwaJ19uG4n6UFXbKcNWgaaBfrRViNiXk4BfUpBp0XaQRwz8+ulLJnafhAW8RF4tWqLXe2QFN0YZy8V2R+G/f94p785D2eaya7Hdhma2Gvmkcw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176385; c=relaxed/simple; bh=yc7YZyiHg5pmKBbPHTB2Guyi6OVLmAtODC1e+TEK/xg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=btu67qFKLPGf4tR3j1JNbh/BEFtbD39vGdQCvxzTLS0ycuE1qmqCPJLmGtG7ChOHOAUlORagjLyFllyUG9BFTOYutnu95l5yXgYvCcH7DxMptJ3TE/xy9+MEJy5yDBVXxwcaexn0v9tP2HcacjR/MDu8WB/w1RMD6FxtgNW3Yv8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=zn4vNVXY; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="zn4vNVXY" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54270hfw030647; Fri, 2 May 2025 04:59:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=xxrIc nhBfRtd8cvn/u+XbD4N44DM53U8qi/bmtbLmhQ=; b=zn4vNVXYpds/okvU+gTGX Sfd89jJai3P4cLyM95Yb8nyzfwqxNmFibn8O4LSm7P/Byg1+8pUjZlxjWv1zPh5p +nfqcHCyw1xtLQ2SiOhlFk3BE3mzzzzDFCQikOoukhDTzfXYRI4QG1C3/0gW5rVE UldFSwLQ60u+hg4+0KV1KuJIo7CV7FFFDeorZIU02uDHDxo8XN6PIN7kFznIbA1l 22ob0JATjfroyLSMRO3EoM5USzXcgam0cZF0sFK/0EUFnV20CW1jr4DVkhst4n+y PdK0nT8Je+Pj0jZMRLrYW1knHk0iTNkvvmowFG58lnHtIoM49f0ASyFw6tTDdIkh A== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46b6tr3xq1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 May 2025 04:59:34 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 5428xXCp029951 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 May 2025 04:59:33 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:33 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 2 May 2025 04:59:33 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.211]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 5428xL7L015723; Fri, 2 May 2025 04:59:28 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v4 02/10] iio: backend: add support for data alignment Date: Fri, 2 May 2025 11:58:57 +0300 Message-ID: <20250502085905.24926-3-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502085905.24926-1-antoniu.miclaus@analog.com> References: <20250502085905.24926-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: lkHQs40aNrIuct8UvJOSjTW1UfE17onc X-Authority-Analysis: v=2.4 cv=TpTmhCXh c=1 sm=1 tr=0 ts=68148976 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=362gKwIBT9qLEHrmTkEA:9 X-Proofpoint-ORIG-GUID: lkHQs40aNrIuct8UvJOSjTW1UfE17onc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDA2OSBTYWx0ZWRfX0LVyNCkrkvDC HeE2Ej8PsL/1C/lJCnqJ/TjZQCAk91P/MnrJALHdvp42vaLN31lqQXlrdu6CjIiAFpK/g4rOlzZ YQcjmP7tFCN/pjcHzl8VAynCD21KtLLfUhnRDgOvgqog82BkqX3DDbovqHMyi4asa/8x1KivrHX p42EnIqhnPfOG2QTdknVRXe5x9AjgazivcRkPwUx/H0P7Km35OFdjIHHmQstwnp0LUaa8GGkUFT YLoUm5UgmPjaVMzKudvyO3UEijVe5paQJDCtz2Q6Fp/flnpwgvCwexVutt4F9TaSVpeQ3k1fF7d ZldH2eYx0e53nMvz921cMmknNVcuLltI9dwDiCPOf2OcWXC0+1bn+zVlSbUAcSjvpDc10LVZTPv fmK96H0KXS/s3mdbnDH+4E2N4hMGfCYX4OYuRp9AGmCpx3TrddN/0h1yEoIVa5DZ9++kdG2Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 impostorscore=0 suspectscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020069 Content-Type: text/plain; charset="utf-8" Add backend support for staring the capture synchronization. When activated, it initates a proccess that aligns the sample's most significant bit (MSB) based solely on the captured data, without considering any other external signals. Signed-off-by: Antoniu Miclaus --- changes in v4: - implement iio_backend_interface_data_align with timeout parameter. drivers/iio/industrialio-backend.c | 14 ++++++++++++++ include/linux/iio/backend.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index 038c9e1e2857..b7cbbc7a8fcd 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -796,6 +796,20 @@ int iio_backend_filter_type_set(struct iio_backend *ba= ck, } EXPORT_SYMBOL_NS_GPL(iio_backend_filter_type_set, "IIO_BACKEND"); =20 +/** + * iio_backend_data_align - Perform the data alignment process. + * @back: Backend device + * @timeout: Timeout value. + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_interface_data_align(struct iio_backend *back, u32 timeout) +{ + return iio_backend_op_call(back, interface_data_align, timeout); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_interface_data_align, "IIO_BACKEND"); + /** * iio_backend_ddr_enable - Enable interface DDR (Double Data Rate) mode * @back: Backend device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index 5526800f5d4a..452cb2838dad 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -109,6 +109,7 @@ enum iio_backend_filter_type { * @debugfs_print_chan_status: Print channel status into a buffer. * @debugfs_reg_access: Read or write register value of backend. * @filter_type_set: Set filter type. + * @interface_data_align: Perform the data alignment process. * @ddr_enable: Enable interface DDR (Double Data Rate) mode. * @ddr_disable: Disable interface DDR (Double Data Rate) mode. * @data_stream_enable: Enable data stream. @@ -161,6 +162,7 @@ struct iio_backend_ops { unsigned int writeval, unsigned int *readval); int (*filter_type_set)(struct iio_backend *back, enum iio_backend_filter_type type); + int (*interface_data_align)(struct iio_backend *back, u32 timeout); int (*ddr_enable)(struct iio_backend *back); int (*ddr_disable)(struct iio_backend *back); int (*data_stream_enable)(struct iio_backend *back); @@ -203,6 +205,7 @@ int devm_iio_backend_request_buffer(struct device *dev, struct iio_dev *indio_dev); int iio_backend_filter_type_set(struct iio_backend *back, enum iio_backend_filter_type type); +int iio_backend_interface_data_align(struct iio_backend *back, u32 timeout= ); int iio_backend_ddr_enable(struct iio_backend *back); int iio_backend_ddr_disable(struct iio_backend *back); int iio_backend_data_stream_enable(struct iio_backend *back); --=20 2.49.0 From nobody Sat Feb 7 08:53:14 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C4A122DFA7; Fri, 2 May 2025 08:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176384; cv=none; b=Wb6jSCnMKxxp3HQ5k1IV0vEcsp4JnzjWpJIoWWKAEYLyBKkAqbp1jCt4Mc8+ql+/5OSoZD0gMU5FzLptRizmsqrmUhiYpMgxWJ/rVfBNLM7pNMYMYrgnWz7D2SpZmRfv5lY9E1Dzu14bMJpAxNhUDCUyl0YvKVXJgSc0YAAQJgk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176384; c=relaxed/simple; bh=LM3ISJdPNjpaYVD/id7uVZyE9EZXVma+CN0TwsdfXtM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ALmrtaDeNyDFCYddkNi2tLBd+eR72oHSNUyDcOraVFigCOIURp/dGgnf8BCFBBjnyp8r3SMeiBMrtr20I6hzUFldGgKc4Y2OjFy8TjejwnCW+FitTZyOmD29qJMq/Xju9bTP7bre86qLFVS9CRVFWFCwXzLsR1cdlDo16rlWnn8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=FLkgmCLp; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="FLkgmCLp" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5426qvdG030837; Fri, 2 May 2025 04:59:34 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=TRLas Txx/1kDGYQyOgFNaUyOIo+ZeDqV5phFc6/7rEM=; b=FLkgmCLp6m5UoRD9i3zxz rfNXQwJeJrqBLz3J4n6YL9XT/boQ72DWkV+Aa3zN+0Ju+SSUumJfFxZ+k1Nim5fM GGBRNkKoMZSHcd572ozhzlnvCQF7NtCGRYZODxt2jkRQomSnmTMf8nmYygwjXc/b Gx4EXkLEkMkjUkKNUnRI/JrHkQ/otuKKMi3jEfuBI3/n9diWUb29/JCaDiezgAW0 WwNuwN9nHyBxj9O/XZUqI59KnfcEQtOdGq/7+z0tlC40NLo3pXyZae5265QrKH5z Nu4LINSOXMnfmcwsyQxhFa/lO7n5J/SmYkFQX9Wv0/NiQtKVPwHXT9IOpMcNaYr/ w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46b6tr3xq0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 May 2025 04:59:34 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 5428xXCY029948 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 May 2025 04:59:33 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:32 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 2 May 2025 04:59:32 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.211]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 5428xL7M015723; Fri, 2 May 2025 04:59:29 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= Subject: [PATCH v4 03/10] iio: backend: add support for number of lanes Date: Fri, 2 May 2025 11:58:58 +0300 Message-ID: <20250502085905.24926-4-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502085905.24926-1-antoniu.miclaus@analog.com> References: <20250502085905.24926-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: iGFygjxJJyk4SYVeiGntPh8gWuLimZzd X-Authority-Analysis: v=2.4 cv=TpTmhCXh c=1 sm=1 tr=0 ts=68148976 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=Ge_Sr372ckFWHCXdfyYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: iGFygjxJJyk4SYVeiGntPh8gWuLimZzd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDA2OSBTYWx0ZWRfX3WBUfKD602pW qaMxJwEYwESxzqQFNMePxzH1bk32jh/t7xfmQ60RmDBAMIOpV16ht2YaX/wc/8pLsmhF18u0onk ZRMF4cpsKeULtYOQ/VN25NiPUK8z2LrtPFpGNkBCmZwAOgIHKY5cIZqLCnDPDq1EVtqZfxqEsvy syniEzbpRpmq5JHNVy0AxgaMXDjFXIeCInXYdZ01+71t5NU3yRQv22zBrjHX77Cjjy05i4Zcfx2 SvgbcQg8dT9FlbRmQewb5OpnIqa/obVeX4GV99inaLnqNOFZwGpcpOQRF3osZ3OHBFl5hAS0czB QYZa20+Bq2lRzg3rEUvnNxscVhZrNRFNDZjMpzsvRE15j9KccaJ0DnSkeN5ylS6z3FQnObVFELv E5H6gRNoeFdebX7nlIgnPZxVyImIwZsLFyeWnkEE1pUTUPuQE0udZDUyTNBocyS7xf4U9xzH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 impostorscore=0 suspectscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020069 Add iio backend support for number of lanes to be enabled. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- no changes in v4. drivers/iio/industrialio-backend.c | 17 +++++++++++++++++ include/linux/iio/backend.h | 3 +++ 2 files changed, 20 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index b7cbbc7a8fcd..78a957d1fe92 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -810,6 +810,23 @@ int iio_backend_interface_data_align(struct iio_backen= d *back, u32 timeout) } EXPORT_SYMBOL_NS_GPL(iio_backend_interface_data_align, "IIO_BACKEND"); =20 +/** + * iio_backend_num_lanes_set - Number of lanes enabled. + * @back: Backend device + * @num_lanes: Number of lanes. + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_num_lanes_set(struct iio_backend *back, unsigned int num_l= anes) +{ + if (!num_lanes) + return -EINVAL; + + return iio_backend_op_call(back, num_lanes_set, num_lanes); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_num_lanes_set, "IIO_BACKEND"); + /** * iio_backend_ddr_enable - Enable interface DDR (Double Data Rate) mode * @back: Backend device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index 452cb2838dad..1ffb200eb3ff 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -110,6 +110,7 @@ enum iio_backend_filter_type { * @debugfs_reg_access: Read or write register value of backend. * @filter_type_set: Set filter type. * @interface_data_align: Perform the data alignment process. + * @num_lanes_set: Set the number of lanes enabled. * @ddr_enable: Enable interface DDR (Double Data Rate) mode. * @ddr_disable: Disable interface DDR (Double Data Rate) mode. * @data_stream_enable: Enable data stream. @@ -163,6 +164,7 @@ struct iio_backend_ops { int (*filter_type_set)(struct iio_backend *back, enum iio_backend_filter_type type); int (*interface_data_align)(struct iio_backend *back, u32 timeout); + int (*num_lanes_set)(struct iio_backend *back, unsigned int num_lanes); int (*ddr_enable)(struct iio_backend *back); int (*ddr_disable)(struct iio_backend *back); int (*data_stream_enable)(struct iio_backend *back); @@ -206,6 +208,7 @@ int devm_iio_backend_request_buffer(struct device *dev, int iio_backend_filter_type_set(struct iio_backend *back, enum iio_backend_filter_type type); int iio_backend_interface_data_align(struct iio_backend *back, u32 timeout= ); +int iio_backend_num_lanes_set(struct iio_backend *back, unsigned int num_l= anes); int iio_backend_ddr_enable(struct iio_backend *back); int iio_backend_ddr_disable(struct iio_backend *back); int iio_backend_data_stream_enable(struct iio_backend *back); --=20 2.49.0 From nobody Sat Feb 7 08:53:14 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84B4B22F773; Fri, 2 May 2025 08:59:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176386; cv=none; b=f5gKl1py6eSaWnourPifrH3XH/45LOttia+1cProviSFk6YlNDmRZPHTP45UKsWKCYM3QDs6mpcFggp4zAglGrDZWsRs0LBTNcXRPpZ2sCG5Khvvmx64G5Q/8e1jlX3pJ9u5SR17qAZsNvC6CsfcH3EJRnJMCOqeoC7AWYCCP9A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176386; c=relaxed/simple; bh=FpzKrezyyTo7ArFlozAg6JQ0WxUTyuPqW2frH46R4Uo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ejPYExfwQA21//RIIq6ZFdZtdesaMwE2v3jNX1rhxRo0T+zgDEfyTzcNvf30H+w0eNcKc8zoYuOVTEok0LyY36cVfiqgLKHuWjtF8//A+D8+pZVqs2RG8KwJQNZb26Nyb7eyrgluXcvgiLF+22+4BDEygAfiCR+ZnSXgkwRVzF0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=hCzHRVK0; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="hCzHRVK0" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5427SOp3020069; Fri, 2 May 2025 04:59:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=OznZr WrlZQen1axqbY+9g8lfWU8grjicI1djlcqMbhQ=; b=hCzHRVK0MeVmbHsP8bjgd ZII1ruBrTWJGrkFkzgIVvg5u1HFKPhMlhia4HSNda50ox4UtHXOazu9AuMQspql6 W6taZZtRWkmpoUgUfJCo9/N0rHOwtgVo9/yRaYwpUYGd2A5lc5s1lX/VHJV2SInC 9bXeQanQ7nB8UwPQAJ3aHduuKsW1XWTeDvdvZL/ZTgNNLk8J5jlRDgbwi/Ytk+Sh Dk95B0hgMdKMAWbyKQJLuBCSip6/jQRvHP/aYZUcXkmUwPz3GppMFY5Pv9lHC6/9 a4w7l710RqPC2yvONJp2afwgKQ5MkHbrUYSTy1le+dL3Z5uspCSlD9763t/K2ORG w== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 46cm5pskhx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 May 2025 04:59:34 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 5428xXnJ058964 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 May 2025 04:59:33 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:33 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 2 May 2025 04:59:33 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.211]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 5428xL7N015723; Fri, 2 May 2025 04:59:30 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v4 04/10] dt-bindings: iio: adc: add ad408x axi variant Date: Fri, 2 May 2025 11:58:59 +0300 Message-ID: <20250502085905.24926-5-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502085905.24926-1-antoniu.miclaus@analog.com> References: <20250502085905.24926-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: vey2Vp4jadPExRIFcJRxjiBOgk-G_nim X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDA2OSBTYWx0ZWRfX8Z0Y6qZifQAC EIX7NKAhcB4JRf0Elj6aWis+AEH+B7IyjIVGqlpaGiHVlKnKJblduqBvqW4pcFH1L3sbmWZVT5A mCRXpA7ymdhEE/OPK3T7x64MGnHMfoRKl1O2r5znlf9dU1Vv9Gz3/B9WER6ptfpjMhwy13jMNiB 8Ggx2ozsqNucBfJW1kmCHq/8tjEgGRo088IXttiHPkU4LwhT+YdOQjIVBpN+Uefrz5LtjtJJ5I7 WCm32SVM5dnquAiQMV/ycOAboS+849Jd6RNiV0NVusuXR6zaSD1hDs6uFsYszAwBlzlZocO1T8J 0qazDvgrz+7ijHBiZok3oMwxpCq6EXXN5U4ikEdT2uqRu29f2Movg7W0U7erWFhPdhEPRkbPn1x 4mwRw8D7osH95JCHcbOL6vBBxTDCPCAJQP/RGR2FKnO7VHUsKhdNgwoM0OAGLJupIVVJD+RM X-Proofpoint-GUID: vey2Vp4jadPExRIFcJRxjiBOgk-G_nim X-Authority-Analysis: v=2.4 cv=RYCQC0tv c=1 sm=1 tr=0 ts=68148976 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=wI1k2SEZAAAA:8 a=VwQbUJbxAAAA:8 a=q2Ulk47HLb923_f0sX4A:9 a=6HWbV-4b7c7AdzY24d_u:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 malwarescore=0 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020069 Content-Type: text/plain; charset="utf-8" Add a new compatible and related bindings for the fpga-based AD408x AXI IP core, a variant of the generic AXI ADC IP. The AXI AD408x IP is a very similar HDL (fpga) variant of the generic AXI ADC IP, intended to control ad408x familiy. Although there are some particularities added for extended control of the ad408x devices such as the filter configuration. Wildcard naming is used to match the naming of the published firmware. Reviewed-by: Rob Herring (Arm) Signed-off-by: Antoniu Miclaus --- no changes in v4. Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml b/D= ocumentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml index cf74f84d6103..e91e421a3d6b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml @@ -27,6 +27,7 @@ description: | the ad7606 family. =20 https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + https://analogdevicesinc.github.io/hdl/library/axi_ad408x/index.html https://analogdevicesinc.github.io/hdl/library/axi_ad485x/index.html http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html =20 @@ -34,6 +35,7 @@ properties: compatible: enum: - adi,axi-adc-10.0.a + - adi,axi-ad408x - adi,axi-ad7606x - adi,axi-ad485x =20 --=20 2.49.0 From nobody Sat Feb 7 08:53:14 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FCBC22B8AB; Fri, 2 May 2025 08:59:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176382; cv=none; b=ocvEOBX7j7vcd6Pv4HlgjGJg4mYvsZ4dWKwTnoIhd+xkJhgWmzqo57kyL1pTkMfl1gk+PIV/L13zSOkzlfC5tCuzr0g5VMhLUHk/w0lChsXYS10FpbEetcuLINgIp2E3wIC/qcVzij3xkCme/SGBOOeynm67WBmsEwutYHzaYd8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176382; c=relaxed/simple; bh=EvHlE5d8LCdBcTcU4Vrbhg9hruUVNcTrvSN0XUwTqg0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U+YAZYTGr5ygyFRrjQk6CvzVbYqnlqQo0f2zGQCAZPvVujR8lTKMgP5qZhPW0OcPfd708fF7q8rW1l76W9hgP4z5Uouh3D/WZ29l7sUigxLT/q9Hih0lKu0R9qVI1ulKFw+umMnWFNGVcPxbmwHYlVIoHzA0tA9nkz/AxreHi0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=eVZ3UfLl; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="eVZ3UfLl" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5427VDbT030805; Fri, 2 May 2025 04:59:38 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=WHCgg HzjGodYAEvbarEyaF35iS/lQgvtCblBcy74j10=; b=eVZ3UfLlJp5J2VlJ4PsON HGyYUhMOwEnk3QsxMI6vp0qBtMkSsQ41ycvx4xM8+CuvS6xt4XZzlACp8G80m1Ud nnBOSxWtpSCNQLeumhhQh+Ony4ukxmOeLL4Ee+Xr4McfwfUXw1xFONveFXJ8mLMS FpJrAwj3oO19UhNaHBpsGJT4kVtUVWmrj3iMaQrZfpnqEYtrkvno799vEKtbsspg 60GB2Fx1O2KancXZtm8larQasYXCbOVup+dc7GembESxGFy3Zc4i89CPhFQQxm6b paTrpTR//mAXQBYnraQQqKg7zyZgC7Gik1B1SlG3/YZ7JdYKZ2jVn1+FxITKq2Bk w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46b6tr3xq7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 May 2025 04:59:38 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 5428xbeg029959 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 May 2025 04:59:37 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:37 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:37 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 2 May 2025 04:59:37 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.211]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 5428xL7O015723; Fri, 2 May 2025 04:59:31 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v4 05/10] iio: adc: adi-axi-adc: add filter type config Date: Fri, 2 May 2025 11:59:00 +0300 Message-ID: <20250502085905.24926-6-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502085905.24926-1-antoniu.miclaus@analog.com> References: <20250502085905.24926-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: 6ZCRRPk0nB7k2xIxt6IPwbtbzCDAERDg X-Authority-Analysis: v=2.4 cv=TpTmhCXh c=1 sm=1 tr=0 ts=6814897a cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=Gqha4wrVLCtXpNfHMFMA:9 X-Proofpoint-ORIG-GUID: 6ZCRRPk0nB7k2xIxt6IPwbtbzCDAERDg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDA2OSBTYWx0ZWRfX/yqE4scoft+C KSez6b8Oe3qIAdoKXaMgNxjsRLhhZEcSR+H0Ta9GoWMfO4A7UadoHn/W6w+4Kam5qjvJ2tpMh/J PY9xeBFb/WkmoGir07NTy9BM/HnJjYwSscJN18aHnl1NOAN/B/XfReJTIqGqN265ZC2O0qBz9tv xzzc39TlVFNljkp3eogAqou8IZZsuEWAIM+PdcFTR3vIPmY9FmjRNXV4aHIx6hMzD3Zzn98+A9W lWHg9O5V91/U+5IBuFxHQGe56K6cz2v3KQtYPdro69kGN+h9fVi1Pej7Ss6Nn+/i3ZhSQz52EXV Qog4Sftw1AUoD4dbow0Vxn2A7LQHD8LRTt8p5xeGqZPITpwkaMgpBbCGV2lBRxYLUostEr/fpza JNRjumJ69L7nUjC7Hq6Z823ntZy4Bfn4bTY8w1PtDzoI6YBEKfaPnbojmwY/wID3KNzl8OOv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 impostorscore=0 suspectscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020069 Content-Type: text/plain; charset="utf-8" Add support for enabling/disabling filter based on the filter type provided. This feature is specific to the axi ad408x IP core, therefore add new compatible string and corresponding iio_backend_ops. Signed-off-by: Antoniu Miclaus Reviewed-by: Nuno S=C3=A1 --- changes in v4: - update commit message to state that the new compatible is added. - checking for max value is done in the iio_backend function. drivers/iio/adc/adi-axi-adc.c | 38 +++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 61ab7dce43be..2a3a6c3f5e59 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -52,6 +52,7 @@ #define AXI_AD485X_PACKET_FORMAT_20BIT 0x0 #define AXI_AD485X_PACKET_FORMAT_24BIT 0x1 #define AXI_AD485X_PACKET_FORMAT_32BIT 0x2 +#define AXI_AD408X_CNTRL_3_FILTER_EN_MSK BIT(0) =20 #define ADI_AXI_ADC_REG_DRP_STATUS 0x0074 #define ADI_AXI_ADC_DRP_LOCKED BIT(17) @@ -402,6 +403,19 @@ static int axi_adc_ad485x_oversampling_ratio_set(struc= t iio_backend *back, } } =20 +static int axi_adc_ad408x_filter_type_set(struct iio_backend *back, + enum iio_backend_filter_type type) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + + if (type) + return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, + AXI_AD408X_CNTRL_3_FILTER_EN_MSK); + + return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, + AXI_AD408X_CNTRL_3_FILTER_EN_MSK); +} + static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, struct iio_dev *indio_dev) { @@ -582,6 +596,24 @@ static const struct iio_backend_info axi_ad485x =3D { .ops =3D &adi_ad485x_ops, }; =20 +static const struct iio_backend_ops adi_ad408x_ops =3D { + .enable =3D axi_adc_enable, + .disable =3D axi_adc_disable, + .chan_enable =3D axi_adc_chan_enable, + .chan_disable =3D axi_adc_chan_disable, + .request_buffer =3D axi_adc_request_buffer, + .free_buffer =3D axi_adc_free_buffer, + .data_sample_trigger =3D axi_adc_data_sample_trigger, + .filter_type_set =3D axi_adc_ad408x_filter_type_set, + .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_adc_reg_access), + .debugfs_print_chan_status =3D iio_backend_debugfs_ptr(axi_adc_debugfs_pr= int_chan_status), +}; + +static const struct iio_backend_info axi_ad408x =3D { + .name =3D "axi-ad408x", + .ops =3D &adi_ad408x_ops, +}; + static int adi_axi_adc_probe(struct platform_device *pdev) { struct adi_axi_adc_state *st; @@ -697,9 +729,15 @@ static const struct axi_adc_info adc_ad7606 =3D { .has_child_nodes =3D true, }; =20 +static const struct axi_adc_info adi_axi_ad408x =3D { + .version =3D ADI_AXI_PCORE_VER(10, 0, 'a'), + .backend_info =3D &axi_ad408x, +}; + /* Match table for of_platform binding */ static const struct of_device_id adi_axi_adc_of_match[] =3D { { .compatible =3D "adi,axi-adc-10.0.a", .data =3D &adc_generic }, + { .compatible =3D "adi,axi-ad408x", .data =3D &adi_axi_ad408x }, { .compatible =3D "adi,axi-ad485x", .data =3D &adi_axi_ad485x }, { .compatible =3D "adi,axi-ad7606x", .data =3D &adc_ad7606 }, { /* end of list */ } --=20 2.49.0 From nobody Sat Feb 7 08:53:14 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84C7522FACE; Fri, 2 May 2025 08:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176385; cv=none; b=CF31/GYurw53vg7fuq0tUF8Hgb0JeRURSajQzP5BAITkgov17k5eG+eILpR3Ni5p0W4P45zj/b1U8EhwWM9vOJvaZRnLqtXog/9ifuRCPx879as3ScNW9MesI0vSc1jbyvwD4bpqg7sMj8XdT1Dwqy87ku86FxoIGb1hEMcr9Ws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176385; c=relaxed/simple; bh=HQlFKESXhCugNeJbPQgUHHoNvkvtnaIx8WN7c9H+O2o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o1QlX8YgZ55H7E9sgYcS8Cfi7fa73bJM5qH9rPviXlrXixTwT37O9vb3Z9M9C/N1+jkbY/5l6bSyeakJjxHYTuLqzE6B3LoY27ASrBoYuyIJJ0emCgzLFk/DYH0JbPhGHEJ1URno234FFl3yovIGvpZLbUxYLZ3xf0ruxtvcKzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=p4jQyDlT; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="p4jQyDlT" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54265IAt019278; Fri, 2 May 2025 04:59:40 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=DQvFt 7jhsX/mMZgNf+GaA+RvkOV+brvoK/N9mztZONU=; b=p4jQyDlT3pZw6MFrqmj8A PPTLLA/vSpGqXB/02tsD5mVwaV2FFiDyrbeKsx5NQ9T4Se4vOKzjeJhCQfAidFMz tUuPM9/cx0fpRltCa/m9xtgFiYIC4AvX79XVdguhFbjqoXSZaiSN92ENiKwXaykP nniGmeUY3rE/OHnoqJTYl8oPFcPffmheQiIOndGVlKotM9BzAXyyuQKZ5pDqxA6d 9zl/fFW9lfeuJt6P9ARXDG4vR6tofrn/ef7t2VedKUZQRLOZSUSZgpJAFiAtKWNe 4V6xSP7mOQuBFDcTEAwSEK0uO8FWtCEnmlMdJTrnRlFq+7azJorvRarDcu16z4Nx A== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 46cm5pskjb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 May 2025 04:59:39 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 5428xcqX058974 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 May 2025 04:59:38 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:38 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 2 May 2025 04:59:38 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.211]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 5428xL7P015723; Fri, 2 May 2025 04:59:32 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v4 06/10] iio: adc: adi-axi-adc: add data align process Date: Fri, 2 May 2025 11:59:01 +0300 Message-ID: <20250502085905.24926-7-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502085905.24926-1-antoniu.miclaus@analog.com> References: <20250502085905.24926-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: kf1Jnci-Y1eGEXbud8pewrtOy21BW94R X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDA2OSBTYWx0ZWRfX57UZUzKM4TCx I4RPtVAQ7RkXrprYdMWVpdIddGanJZu8cZSE571cyEXsGtd4rg4ow2qZN+4NQDAu5Tvu3lh0ghK x3dzul8rUxHbjrRBXCEJFSuWDiZPURn1Zyl+Dtp8e8iUf0V5+J0GAvGCexw3+NzCqLq8S8BQuV1 1SAB86oNnqtblnHpmuh9C8Gi6RjhBxqmA9cLfmByDnnxkhqrlJv/jl6X6N5vS5Ve0kQc9N6Ky9L ex/bVdJ2H1wWkUTQ22swjTvPBos/HkcHptz1TG0ODr0cx7iU5Xg12rLehc/mvmm55ltGdc5SaX2 p2wykp7PePbY88Uox7YxuCybJPuQsLyqR+NqfPi8ecBfLFKF+IhzUgenMBM1fjOqwcI7OcSht8y dlxfLT5hwigE0FttNbx8L9Og2vECY+OXTDU8H6yyqYvLpIJ4jQU+N82W8iNd/h44TCFHG2hD X-Proofpoint-GUID: kf1Jnci-Y1eGEXbud8pewrtOy21BW94R X-Authority-Analysis: v=2.4 cv=RYCQC0tv c=1 sm=1 tr=0 ts=6814897b cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=wxM4B6g2en942FlrxLsA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 malwarescore=0 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020069 Content-Type: text/plain; charset="utf-8" Add support for starting the sync process used for data capture alignment. Signed-off-by: Antoniu Miclaus --- changes in v4: - rework data_align function. - rename bit definitions/functions. drivers/iio/adc/adi-axi-adc.c | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 2a3a6c3f5e59..2a79c043c0de 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -44,6 +44,7 @@ #define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) =20 #define ADI_AXI_ADC_REG_CTRL 0x0044 +#define ADI_AXI_ADC_CTRL_SYNC_MSK BIT(3) #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) =20 #define ADI_AXI_ADC_REG_CNTRL_3 0x004c @@ -54,6 +55,9 @@ #define AXI_AD485X_PACKET_FORMAT_32BIT 0x2 #define AXI_AD408X_CNTRL_3_FILTER_EN_MSK BIT(0) =20 +#define ADI_AXI_ADC_REG_SYNC_STATUS 0x0068 +#define ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK BIT(0) + #define ADI_AXI_ADC_REG_DRP_STATUS 0x0074 #define ADI_AXI_ADC_DRP_LOCKED BIT(17) =20 @@ -416,6 +420,38 @@ static int axi_adc_ad408x_filter_type_set(struct iio_b= ackend *back, AXI_AD408X_CNTRL_3_FILTER_EN_MSK); } =20 +static int axi_adc_ad408x_interface_data_align(struct iio_backend *back, + u32 timeout) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + bool sync_en; + u32 val; + int ret; + + ret =3D regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, + ADI_AXI_ADC_CTRL_SYNC_MSK); + if (ret) + return ret; + + do { + ret =3D regmap_read(st->regmap, ADI_AXI_ADC_REG_SYNC_STATUS, &val); + if (ret) + return ret; + + sync_en =3D FIELD_GET(ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK, val); + + if (!sync_en) + dev_dbg(st->dev, "Not Locked: Running Bit Slip\n"); + + fsleep(500); + } while (--timeout && !sync_en); + + if (!timeout) + return -ETIMEDOUT; + + return 0; +} + static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, struct iio_dev *indio_dev) { @@ -605,6 +641,7 @@ static const struct iio_backend_ops adi_ad408x_ops =3D { .free_buffer =3D axi_adc_free_buffer, .data_sample_trigger =3D axi_adc_data_sample_trigger, .filter_type_set =3D axi_adc_ad408x_filter_type_set, + .interface_data_align =3D axi_adc_ad408x_interface_data_align, .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_adc_reg_access), .debugfs_print_chan_status =3D iio_backend_debugfs_ptr(axi_adc_debugfs_pr= int_chan_status), }; --=20 2.49.0 From nobody Sat Feb 7 08:53:14 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B9CB23BD06; Fri, 2 May 2025 08:59:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176387; cv=none; b=HuloIo9CVTgBK2eLoWtExZRbyjt26aZD759XAnJOB4s/c8BMqp3WwK2DVN5P19OBeBpb/q3popn/x5/Tn2Ne8F7NQ/sikIxJ5VFc/TYYD9zEE9aAK6H7SRqaH7B+lzyy/278q/eiPf+xgG3675DpETem4ag+evCXVYgpX0ZbQ5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176387; c=relaxed/simple; bh=5Njg+X3lk57SOnUa5y2vPu2VFKsInRFRYmteG379BnM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Xr6EqRNgewht2htffGBnluCgyJMhXugaudrdAJMGv7ggDuSWdPNLdi8Nlk0OKXvIM3+LFIg1SMqq0nAOJCm0Bw9vN1duvTRK96aP+I3YgL59nuXQRBsXbc6x7LbdUrNSyz3MXUoOP2t7bNXWOlpuasdAMqZrNaOEkVafn+B9yq4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=SpURWTBJ; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="SpURWTBJ" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54265IAu019278; Fri, 2 May 2025 04:59:40 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=Gtwie b1q/RKDj57tnBTHrdi5jSfPp6vexNmKB4LUpb8=; b=SpURWTBJzrBuNwr4bXgKm hfGYxhedn/EMjuMh3swczBF/9MgvkWiC9AdfsXgFAH93qHawgrCM5jNFA8sGq7bV vSpoebjFMMNgy752Dcw3u8fBsWGhn0t/hYAOh+O3D+LrjZmDUZETg+qa/nJKpoVP TVQ2iqtqih4y38kw6MpV7EZeXqSrKUO4lBoJAG76p7jeiKwNlQA3RbFyjsGA5zES kyZ6O2v0y225qazXmevcgmN8alspyv2nYrrf3EjprT0Fn9d92Mgb172ySKLNW4Ei 1YgTA6L7ziaxmLkLITWMvsH4caQDcSM4gpnth9q2dAjntew3M+KqtvAPLTor2rkK w== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 46cm5pskjc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 May 2025 04:59:40 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 5428xdBw058981 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 May 2025 04:59:39 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:39 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 2 May 2025 04:59:39 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.211]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 5428xL7Q015723; Fri, 2 May 2025 04:59:33 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= Subject: [PATCH v4 07/10] iio: adc: adi-axi-adc: add num lanes support Date: Fri, 2 May 2025 11:59:02 +0300 Message-ID: <20250502085905.24926-8-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502085905.24926-1-antoniu.miclaus@analog.com> References: <20250502085905.24926-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: fOOcAsCxKZgZJp56SHSnRioR9zkupNv4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDA2OSBTYWx0ZWRfXzB7A6/3JFq4o DgyzrAf+8Dets/yjiKv2yXQPMefmCZxOcw4nM29Qm3x3lw0GPg9XZpu7viGLCJRltgAJ1fWP3Uz hq4RAXfxrD4+aIJT5UKw+xmy8dQSCk/eVjmCwAekXy81wb3nsFVDuxFX0yN8V6fj+cMSP0kC8BT e9MgEDeQUByEJZN78LbkEGWZM+VsxEr0w0NX4fnNgkCgazvdcNK2J+1Lldc/KO9wzuMmI8Cv3+i TPNZCHEDtJZUJ3byeCfYu11QphsQpU/q6n1s49uuLJNe9l9PWdmThTLhU952fNo8uX0S8Sljv+5 z0JFFhbG+EWJuMpF9Q5M2C3cL2HcnZ1c+hsYxPQOAkjqM/MsvBSGxKSAf8+sHffGrviev7RpxsI JsT0KLjJYLdqtWDLP5W3ICO4r2KwNG57OG2chWPF8dW7Fe+2i9DulWhxQfOog471cK1UnFcg X-Proofpoint-GUID: fOOcAsCxKZgZJp56SHSnRioR9zkupNv4 X-Authority-Analysis: v=2.4 cv=RYCQC0tv c=1 sm=1 tr=0 ts=6814897c cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=LVysS0whcD1go9EkdQUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 malwarescore=0 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020069 Add support for setting the number of lanes enabled. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- changes in v4: - drop function assignment in axi_adc generic ops. - rename bit definitions. drivers/iio/adc/adi-axi-adc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 2a79c043c0de..64cf72f1c223 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -44,6 +44,7 @@ #define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) =20 #define ADI_AXI_ADC_REG_CTRL 0x0044 +#define ADI_AXI_ADC_CTRL_NUM_LANES_MSK GENMASK(12, 8) #define ADI_AXI_ADC_CTRL_SYNC_MSK BIT(3) #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) =20 @@ -452,6 +453,19 @@ static int axi_adc_ad408x_interface_data_align(struct = iio_backend *back, return 0; } =20 +static int axi_adc_num_lanes_set(struct iio_backend *back, + unsigned int num_lanes) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + + if (!num_lanes) + return -EINVAL; + + return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, + ADI_AXI_ADC_CTRL_NUM_LANES_MSK, + FIELD_PREP(ADI_AXI_ADC_CTRL_NUM_LANES_MSK, num_lanes)); +} + static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, struct iio_dev *indio_dev) { @@ -642,6 +656,7 @@ static const struct iio_backend_ops adi_ad408x_ops =3D { .data_sample_trigger =3D axi_adc_data_sample_trigger, .filter_type_set =3D axi_adc_ad408x_filter_type_set, .interface_data_align =3D axi_adc_ad408x_interface_data_align, + .num_lanes_set =3D axi_adc_num_lanes_set, .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_adc_reg_access), .debugfs_print_chan_status =3D iio_backend_debugfs_ptr(axi_adc_debugfs_pr= int_chan_status), }; --=20 2.49.0 From nobody Sat Feb 7 08:53:14 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C4FD22DFAA; Fri, 2 May 2025 08:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176384; cv=none; b=IXwc3ah5xaqiPd3GM3NgHKsv9C/MWPfm0+4DysCTQaz/xq0TGlyZw+GrtwYH4+BmPmg3AVOLADmRaWSc/Nc1C7SoiNpcw7t6hFb81QlJydNA9fmNMuT6pmjTgoRAH7He1j3PFOY7BO61lxNQ/y7dmii7UNYlgQv+xEz2p80Fib8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176384; c=relaxed/simple; bh=+L9TdB69Fenku1dq/7kJ8upSIBITWqDJqSf7ikOY2oI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Z8r6CXoQR+HrfhWwfW0792Y2JlnC6aO2uwDkImAYzjQbNgA5/go89Oy83eo4sMSLmwCz14ynnJnxtdIm5V/FHtIj0Q1s4gRINPPIzifNOnGKgPzJSFUrlkB1PLVyFiWbUkEs+mWv5TVQwWOqTYBvLQXuap2+TPOzJMyDaKYO1/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=XvELZt0O; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="XvELZt0O" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5426mqti008008; Fri, 2 May 2025 04:59:40 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=sB6E7 pZJ0yf4niDXJ7YeapOtQBSYppJHAjgfKPErpWI=; b=XvELZt0OAwpEIyL70duuT egZBGFmy83fUqy5/oxvpqBbMORqDqbMoI4908n1zgUTGyMSDjXafwrWlAYOA9P+Y H2MqpxAQJGjNNo+DdvVyk8Xef2xYA6IMockfgyB8tsP8SIKuAQZzCvjZMZ9uiIyL 5l/oT4A1i2OXxASl1FUeA9FTzbFE+jvxQBdyBVYq/bNJGCoKLt4ZTu5EwWJPw+sG zdHAhaPF6nDZWfg8Q3V+XlSIzk5jW9pwSYFDPXUO9APWrn6rgPykedVTqTgQzWoC fsdISFQr9Kc7/Ou9or6LkNnppuZfZscgsMfVaa70uPriIoe4bzmgoLbGTQm4AYgM A== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46b6u1kwwp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 May 2025 04:59:39 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 5428xcV0029965 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 May 2025 04:59:38 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:38 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 2 May 2025 04:59:38 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.211]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 5428xL7R015723; Fri, 2 May 2025 04:59:35 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v4 08/10] dt-bindings: iio: adc: add ad4080 Date: Fri, 2 May 2025 11:59:03 +0300 Message-ID: <20250502085905.24926-9-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502085905.24926-1-antoniu.miclaus@analog.com> References: <20250502085905.24926-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=RuDFLDmK c=1 sm=1 tr=0 ts=6814897b cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=dt9VzEwgFbYA:10 a=gEfo2CItAAAA:8 a=gAnH3GRIAAAA:8 a=VwQbUJbxAAAA:8 a=tzrCRXNhpX36lL6KDSgA:9 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: IGXk4EEUCEd1doQ67Sqs5AyELOmDxPRa X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDA2OSBTYWx0ZWRfX4Owx/H5yAmLy PzAdBN0jZWExE7PEtmtJ14p6Me6vMdM1MDCrmhJfqG3gWfHIyM5iGDf713mv7JA4XBgmeiN9Xgo MHX6ZNY9RvLYcV0GofMP3giQuFUJvmO1VhSGbO1vb1G6dw2zNJaksi5SbxylrZG8Wk3RLfUEDyt QAwh+//pwX246/jrDCqJD9ICFzIfazwnKEyi/zSORWgtEke4nylNBW5Z3RPleLyegcv4xWZVstS 1Fw8gC/hxgmpAjzo75o7x3sTEcG/581ihI5mlbKa+qOK9k/RM0pA68p96CAb2CUiA83Jw8VsIUH GuqMZEQxYDmF3IYmxKvqqRq5seD0ccgQkikqrvCdj0nvxLmX3PuqlARMS2dxFl5rrqWsaDsyOU8 kbHj0+Bf43teLA5bqW4f3gM88PEqRIubDjyVriicxjoDgdRKOwSUogPqCb0m0zkbJOKt6BI6 X-Proofpoint-ORIG-GUID: IGXk4EEUCEd1doQ67Sqs5AyELOmDxPRa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 phishscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020069 Content-Type: text/plain; charset="utf-8" Add devicetree bindings for ad4080 family. Reviewed-by: Rob Herring (Arm) Signed-off-by: Antoniu Miclaus --- no changes in v4. .../bindings/iio/adc/adi,ad4080.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4080.ya= ml diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4080.yaml new file mode 100644 index 000000000000..ed849ba1b77b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4080.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4080 20-Bit, 40 MSPS, Differential SAR ADC + +maintainers: + - Antoniu Miclaus + +description: | + The AD4080 is a high speed, low noise, low distortion, 20-bit, Easy Driv= e, + successive approximation register (SAR) analog-to-digital converter (ADC= ). + Maintaining high performance (signal-to-noise and distortion (SINAD) rat= io + > 90 dBFS) at signal frequencies in excess of 1 MHz enables the AD4080 to + service a wide variety of precision, wide bandwidth data acquisition + applications. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ad40= 80.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4080 + + reg: + maxItems: 1 + + spi-max-frequency: + description: Configuration of the SPI bus. + maximum: 50000000 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: cnv + + vdd33-supply: true + + vdd11-supply: true + + vddldo-supply: true + + iovdd-supply: true + + vrefin-supply: true + + io-backends: + maxItems: 1 + + adi,lvds-cnv-enable: + description: Enable the LVDS signal type on the CNV pin. Default is CM= OS. + type: boolean + + adi,num-lanes: + description: + Number of lanes on which the data is sent on the output (DA, DB pins= ). + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + default: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - vdd33-supply + - vrefin-supply + +additionalProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4080"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + vdd33-supply =3D <&vdd33>; + vddldo-supply =3D <&vddldo>; + vrefin-supply =3D <&vrefin>; + clocks =3D <&cnv>; + clock-names =3D "cnv"; + io-backends =3D <&iio_backend>; + }; + }; +... --=20 2.49.0 From nobody Sat Feb 7 08:53:14 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B925123E355; Fri, 2 May 2025 08:59:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176389; cv=none; b=AbqJZh96xFWQAX6HKxtIwPpxxOd0JTwaaWKZP5kCxs/NFM9MGjS4QNdwh5JbShgrywcpBX9acooWuCNn2a3AgMut7ute7temTCLhgq/Qtl8kp/B9J8Ky0o8AAq2F9c8oy7bk7dmHlMMWf7AFte0exIhHmL8KX7L235mUzvLZ1ok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176389; c=relaxed/simple; bh=wKrYqIMpG9qFN9QLm7Wkkrg7C4pDtBCfxty8DTL5EOw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PlA/Yjo6F9WlCrLTOCgz+pPv1+QhLgive+pDF2DMy2LAT4Kz4Eh3w5MipfGrp6Q8X7KMqAzCvcsXYkTVekls8h9odhW9iCY7KBznlokFMN8EBQNk9DbPWJ6reL5BR6RG7evaSJMx1GJLA2R3aTDzgQyjqs3pcja83crBBtkFeEI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=EscIQM/+; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="EscIQM/+" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5428LRXM007984; Fri, 2 May 2025 04:59:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=Fe8pH 4/kS0jr84xB8LMTahqV6lY3QxfCulibsKKDoQc=; b=EscIQM/+Vw31Sa2u4O0NM 1AoOIXbeheKVT42vVlrqmbGFzkruebfrhzSwFqovnhwhY34+LUm4NXrcAny+JiYe SgUdYHCEW9UmO93IOAtOb9Q9zUwGg55iU/mkFpakJxUQj/kSlypzF/2NG/2qYHe9 q7RmDpyAa7yUGXgYUH4j53FjMno8xg15qQ6GKFOJi2AVN7+frCubI08qjsIBkSBI hSQ3EFyN4D66mvku7QH4uRBiXA8XRlEFeNlAXHteN19LQUKSXie/ZydPkTDn9XzU m3TjAcNaYdI00Xr5UvVupHtuSH6euHYCGUy6uSTSMQDkUQgkdB0CcTqMDdkt7NfA w== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46b6u1kwwu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 May 2025 04:59:43 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 5428xg5j058989 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 May 2025 04:59:42 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:42 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 2 May 2025 04:59:42 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 2 May 2025 04:59:42 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.211]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 5428xL7S015723; Fri, 2 May 2025 04:59:36 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v4 09/10] iio: adc: ad4080: add driver support Date: Fri, 2 May 2025 11:59:04 +0300 Message-ID: <20250502085905.24926-10-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502085905.24926-1-antoniu.miclaus@analog.com> References: <20250502085905.24926-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=RuDFLDmK c=1 sm=1 tr=0 ts=6814897f cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=VwQbUJbxAAAA:8 a=1JhV2NT8v1zTVgKiQkIA:9 X-Proofpoint-GUID: U5EI3aK0BKJ4xYarRC_U3QN_eXkiG_P3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDA2OSBTYWx0ZWRfX65s39BCtApGn VOh1x826dNnWoewyj+Ug7TNuhta5ICLswO1ViTLGEP3jAuhcGQoAbrq9Vqj16utHrzY16Pj+oyu 53jglik+V07rNpMrJ+keuQoYZfv2c3zOhkqDPwIEP+OdhVi9RJCI1hz8i4xJlz2zAFRafYuxb7I kXc+fLp2vROpKgww0Th1+40D6LkvWdMpRoC0x5WpUhUNQkUwpsV6bH8iuxU48LdYt3Afiph9zI4 VOO6GI8E5hnop41W5awEyU/tVDYJKLJtb+mi2FYMeqs1dE+7ZiBDWxQnbLHClHC7PWlyDatWcDH Z116BqmjSjWrCQyfewpzW90mRNaxlQB3CTIqGQRkeEOGz/dsLK8hHdO0yIDCMnCmN5NqPMsoMJe JZdKjyzUgf7g43JvGJKM3q/WCkhRPn1YGMH3kjUTEGUGKOrbnD3hZaAxevilN3mgl5uygkij X-Proofpoint-ORIG-GUID: U5EI3aK0BKJ4xYarRC_U3QN_eXkiG_P3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 phishscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020069 Content-Type: text/plain; charset="utf-8" Add support for AD4080 high-speed, low noise, low distortion, 20-bit, Easy Drive, successive approximation register (SAR) analog-to-digital converter (ADC). Signed-off-by: Antoniu Miclaus --- changes in v4: - drop _MSK postfix for bit definitions - add space before } - drop writing reserved bit. - use regmap_set_bits/regmap_clear_bits instead of regmap_write - use dev_dbg() where applies - use dev_err() where applies - use FIELD_PREP when _MSK defines are implied. - drop explicit statement `.shift =3D 0` - get clk_rate during probe. - handle IIO_CHAN_INFO_SCALE and IIO_CHAN_INFO_SAMP_FREQ in default. - use the new iio_backend_interface_data_align function - drop redundant else. - drop redundat mutex guards. - rearrange includes. - rename sinc5+pf1 - use regmap_get_device - drop outermost () - check mode for < 2 - drop st->dec_rate and use functions inline. - drop ad4080_channels[] and use ad4080_channel instead - drop redundat if statement for num_lanes. - use - instead of _ for device properties. - drop reduandant assignement - drop indio_dev->modes =3D INDIO_DIRECT_MODE; - rename filter_disabled to filter_none. MAINTAINERS | 8 + drivers/iio/adc/Kconfig | 14 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4080.c | 570 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 593 insertions(+) create mode 100644 drivers/iio/adc/ad4080.c diff --git a/MAINTAINERS b/MAINTAINERS index bd04375ab4a2..0038f7a078ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1317,6 +1317,14 @@ F: Documentation/devicetree/bindings/iio/adc/adi,ad4= 030.yaml F: Documentation/iio/ad4030.rst F: drivers/iio/adc/ad4030.c =20 +ANALOG DEVICES INC AD4080 DRIVER +M: Antoniu Miclaus +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +F: drivers/iio/adc/ad4080.c + ANALOG DEVICES INC AD4130 DRIVER M: Cosmin Tanislav L: linux-iio@vger.kernel.org diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 27413516216c..17df328f5322 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -47,6 +47,20 @@ config AD4030 To compile this driver as a module, choose M here: the module will be called ad4030. =20 +config AD4080 + tristate "Analog Devices AD4080 high speed ADC" + depends on SPI + select REGMAP_SPI + select IIO_BACKEND + help + Say yes here to build support for Analog Devices AD4080 + high speed, low noise, low distortion, 20-bit, Easy Drive, + successive approximation register (SAR) analog-to-digital + converter (ADC). Supports iio_backended devices for AD4080. + + To compile this driver as a module, choose M here: the module will be + called ad4080. + config AD4130 tristate "Analog Device AD4130 ADC Driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 9f26d5eca822..e6efed5b4e7a 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_AB8500_GPADC) +=3D ab8500-gpadc.o obj-$(CONFIG_AD_SIGMA_DELTA) +=3D ad_sigma_delta.o obj-$(CONFIG_AD4000) +=3D ad4000.o obj-$(CONFIG_AD4030) +=3D ad4030.o +obj-$(CONFIG_AD4080) +=3D ad4080.o obj-$(CONFIG_AD4130) +=3D ad4130.o obj-$(CONFIG_AD4695) +=3D ad4695.o obj-$(CONFIG_AD4851) +=3D ad4851.o diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c new file mode 100644 index 000000000000..9168dee9323e --- /dev/null +++ b/drivers/iio/adc/ad4080.c @@ -0,0 +1,570 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices AD4080 SPI ADC driver + * + * Copyright 2025 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register Definition */ +#define AD4080_REG_INTERFACE_CONFIG_A 0x00 +#define AD4080_REG_INTERFACE_CONFIG_B 0x01 +#define AD4080_REG_DEVICE_CONFIG 0x02 +#define AD4080_REG_CHIP_TYPE 0x03 +#define AD4080_REG_PRODUCT_ID_L 0x04 +#define AD4080_REG_PRODUCT_ID_H 0x05 +#define AD4080_REG_CHIP_GRADE 0x06 +#define AD4080_REG_SCRATCH_PAD 0x0A +#define AD4080_REG_SPI_REVISION 0x0B +#define AD4080_REG_VENDOR_L 0x0C +#define AD4080_REG_VENDOR_H 0x0D +#define AD4080_REG_STREAM_MODE 0x0E +#define AD4080_REG_TRANSFER_CONFIG 0x0F +#define AD4080_REG_INTERFACE_CONFIG_C 0x10 +#define AD4080_REG_INTERFACE_STATUS_A 0x11 +#define AD4080_REG_DEVICE_STATUS 0x14 +#define AD4080_REG_ADC_DATA_INTF_CONFIG_A 0x15 +#define AD4080_REG_ADC_DATA_INTF_CONFIG_B 0x16 +#define AD4080_REG_ADC_DATA_INTF_CONFIG_C 0x17 +#define AD4080_REG_PWR_CTRL 0x18 +#define AD4080_REG_GPIO_CONFIG_A 0x19 +#define AD4080_REG_GPIO_CONFIG_B 0x1A +#define AD4080_REG_GPIO_CONFIG_C 0x1B +#define AD4080_REG_GENERAL_CONFIG 0x1C +#define AD4080_REG_FIFO_WATERMARK_LSB 0x1D +#define AD4080_REG_FIFO_WATERMARK_MSB 0x1E +#define AD4080_REG_EVENT_HYSTERESIS_LSB 0x1F +#define AD4080_REG_EVENT_HYSTERESIS_MSB 0x20 +#define AD4080_REG_EVENT_DETECTION_HI_LSB 0x21 +#define AD4080_REG_EVENT_DETECTION_HI_MSB 0x22 +#define AD4080_REG_EVENT_DETECTION_LO_LSB 0x23 +#define AD4080_REG_EVENT_DETECTION_LO_MSB 0x24 +#define AD4080_REG_OFFSET_LSB 0x25 +#define AD4080_REG_OFFSET_MSB 0x26 +#define AD4080_REG_GAIN_LSB 0x27 +#define AD4080_REG_GAIN_MSB 0x28 +#define AD4080_REG_FILTER_CONFIG 0x29 + +/* AD4080_REG_INTERFACE_CONFIG_A Bit Definition */ +#define AD4080_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0)) +#define AD4080_INTERFACE_CONFIG_A_ADDR_ASC BIT(5) +#define AD4080_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4) + +/* AD4080_REG_INTERFACE_CONFIG_B Bit Definition */ +#define AD4080_INTERFACE_CONFIG_B_SINGLE_INST BIT(7) +#define AD4080_INTERFACE_CONFIG_B_SHORT_INST BIT(3) + +/* AD4080_REG_DEVICE_CONFIG Bit Definition */ +#define AD4080_DEVICE_CONFIG_OPERATING_MODES_MSK GENMASK(1, 0) + +/* AD4080_REG_TRANSFER_CONFIG Bit Definition */ +#define AD4080_TRANSFER_CONFIG_KEEP_STREAM_LENGTH_VAL BIT(2) + +/* AD4080_REG_INTERFACE_CONFIG_C Bit Definition */ +#define AD4080_INTERFACE_CONFIG_C_STRICT_REG_ACCESS BIT(5) + +/* AD4080_REG_ADC_DATA_INTF_CONFIG_A Bit Definition */ +#define AD4080_ADC_DATA_INTF_CONFIG_A_RESERVED_CONFIG_A BIT(6) +#define AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN BIT(4) +#define AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES BIT(2) +#define AD4080_ADC_DATA_INTF_CONFIG_A_DATA_INTF_MODE BIT(0) + +/* AD4080_REG_ADC_DATA_INTF_CONFIG_B Bit Definition */ +#define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK GENMASK(7, 4) +#define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_SELF_CLK_MODE BIT(3) +#define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN BIT(0) + +/* AD4080_REG_ADC_DATA_INTF_CONFIG_C Bit Definition */ +#define AD4080_ADC_DATA_INTF_CONFIG_C_LVDS_VOD_MSK GENMASK(6, 4) + +/* AD4080_REG_PWR_CTRL Bit Definition */ +#define AD4080_PWR_CTRL_ANA_DIG_LDO_PD BIT(1) +#define AD4080_PWR_CTRL_INTF_LDO_PD BIT(0) + +/* AD4080_REG_GPIO_CONFIG_A Bit Definition */ +#define AD4080_GPIO_CONFIG_A_GPO_1_EN BIT(1) +#define AD4080_GPIO_CONFIG_A_GPO_0_EN BIT(0) + +/* AD4080_REG_GPIO_CONFIG_B Bit Definition */ +#define AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK GENMASK(7, 4) +#define AD4080_GPIO_CONFIG_B_GPIO_0_SEL_MSK GENMASK(3, 0) + +/* AD4080_REG_FIFO_CONFIG Bit Definition */ +#define AD4080_FIFO_CONFIG_FIFO_MODE_MSK GENMASK(1, 0) + +/* AD4080_REG_FILTER_CONFIG Bit Definition */ +#define AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK GENMASK(6, 3) +#define AD4080_FILTER_CONFIG_FILTER_SEL_MSK GENMASK(1, 0) + +/* Miscellaneous Definitions */ +#define AD4080_SPI_READ BIT(7) +#define AD4080_CHIP_ID GENMASK(2, 0) + +#define AD4080_MAX_SAMP_FREQ 40000000 +#define AD4080_MIN_SAMP_FREQ 1250000 + +enum ad4080_filter_type { + FILTER_NONE, + SINC_1, + SINC_5, + SINC_5_COMP +}; + +static const unsigned int ad4080_scale_table[][2] =3D { + { 6000, 0 }, +}; + +static const char *const ad4080_filter_type_iio_enum[] =3D { + [FILTER_NONE] =3D "none", + [SINC_1] =3D "sinc1", + [SINC_5] =3D "sinc5", + [SINC_5_COMP] =3D "sinc5+pf1", +}; + +static const int ad4080_dec_rate_iio_enum[] =3D { + 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, +}; + +static const char * const ad4080_power_supplies[] =3D { + "vdd33", "vdd11", "vddldo", "iovdd", "vrefin", +}; + +struct ad4080_chip_info { + const char *name; + unsigned int product_id; + int num_scales; + const unsigned int (*scale_table)[2]; + const struct iio_chan_spec *channels; + unsigned int num_channels; +}; + +struct ad4080_state { + struct regmap *regmap; + struct clk *clk; + struct iio_backend *back; + const struct ad4080_chip_info *info; + /* + * Synchronize access to members the of driver state, and ensure + * atomicity of consecutive regmap operations. + */ + struct mutex lock; + unsigned int num_lanes; + unsigned int dec_rate; + unsigned long clk_rate; + enum ad4080_filter_type filter_type; + bool lvds_cnv_en; +}; + +static const struct regmap_config ad4080_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .read_flag_mask =3D BIT(7), + .max_register =3D 0x29, +}; + +static int ad4080_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2) +{ + unsigned int tmp; + + tmp =3D (st->info->scale_table[0][0] * 1000000ULL) >> + st->info->channels[0].scan_type.realbits; + *val =3D tmp / 1000000; + *val2 =3D tmp % 1000000; + + return IIO_VAL_INT_PLUS_NANO; +} + +static unsigned int ad4080_get_dec_rate(struct iio_dev *dev, + const struct iio_chan_spec *chan) +{ + struct ad4080_state *st =3D iio_priv(dev); + int ret; + unsigned int data; + + ret =3D regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); + if (ret) + return ret; + + return 1 << (FIELD_GET(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, data) + 1); +} + +static int ad4080_set_dec_rate(struct iio_dev *dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct ad4080_state *st =3D iio_priv(dev); + int ret; + + if ((st->filter_type >=3D SINC_5 && mode >=3D 512) || mode < 2) + return -EINVAL; + + ret =3D regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, + AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, + FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, + (ilog2(mode) - 1))); + if (ret) + return ret; + + return 0; +} + +static int ad4080_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long m) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + unsigned int dec_rate; + + switch (m) { + case IIO_CHAN_INFO_SCALE: + return ad4080_get_scale(st, val, val2); + case IIO_CHAN_INFO_SAMP_FREQ: + dec_rate =3D ad4080_get_dec_rate(indio_dev, chan); + if (st->filter_type =3D=3D SINC_5_COMP) + dec_rate *=3D 2; + if (st->filter_type) + *val =3D DIV_ROUND_CLOSEST(st->clk_rate, dec_rate); + else + *val =3D st->clk_rate; + return IIO_VAL_INT; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *val =3D ad4080_get_dec_rate(indio_dev, chan); + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int ad4080_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + return ad4080_set_dec_rate(indio_dev, chan, val); + default: + return -EINVAL; + } +} + +static int ad4080_lvds_sync_write(struct ad4080_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + int ret; + + ret =3D regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); + if (ret) + return ret; + + ret =3D iio_backend_interface_data_align(st->back, 100); + if (ret =3D=3D -ETIMEDOUT) + dev_err(dev, "LVDS Sync Timeout.\n"); + if (ret) + return ret; + + dev_dbg(dev, "Success: Pattern correct and Locked!\n"); + return regmap_clear_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); +} + +static ssize_t ad4080_get_filter_type(struct iio_dev *dev, + const struct iio_chan_spec *chan) +{ + struct ad4080_state *st =3D iio_priv(dev); + unsigned int data; + int ret; + + ret =3D regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); + if (ret) + return ret; + + return FIELD_GET(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, data); +} + +static int ad4080_set_filter_type(struct iio_dev *dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct ad4080_state *st =3D iio_priv(dev); + unsigned int dec_rate; + int ret; + + dec_rate =3D ad4080_get_dec_rate(dev, chan); + + if (mode >=3D SINC_5 && dec_rate >=3D 512) + return -EINVAL; + + guard(mutex)(&st->lock); + ret =3D iio_backend_filter_type_set(st->back, mode); + if (ret) + return ret; + + ret =3D regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, + AD4080_FILTER_CONFIG_FILTER_SEL_MSK, + FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, + mode)); + if (ret) + return ret; + + st->filter_type =3D mode; + + return 0; +} + +static int ad4080_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals =3D ad4080_dec_rate_iio_enum; + *length =3D ARRAY_SIZE(ad4080_dec_rate_iio_enum); + *type =3D IIO_VAL_INT; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static const struct iio_info ad4080_iio_info =3D { + .debugfs_reg_access =3D ad4080_reg_access, + .read_raw =3D ad4080_read_raw, + .write_raw =3D ad4080_write_raw, + .read_avail =3D ad4080_read_avail, +}; + +static const struct iio_enum ad4080_filter_type_enum =3D { + .items =3D ad4080_filter_type_iio_enum, + .num_items =3D ARRAY_SIZE(ad4080_filter_type_iio_enum), + .set =3D ad4080_set_filter_type, + .get =3D ad4080_get_filter_type, +}; + +static struct iio_chan_spec_ext_info ad4080_ext_info[] =3D { + IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad4080_filter_type_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, + &ad4080_filter_type_enum), + { } +}; + +static const struct iio_chan_spec ad4080_channel =3D { + .type =3D IIO_VOLTAGE, + .indexed =3D 1, + .channel =3D 0, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_all_available =3D + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .ext_info =3D ad4080_ext_info, + .scan_index =3D 0, + .scan_type =3D { + .sign =3D 's', + .realbits =3D 20, + .storagebits =3D 32, + }, +}; + +static const struct ad4080_chip_info ad4080_chip_info =3D { + .name =3D "AD4080", + .product_id =3D AD4080_CHIP_ID, + .scale_table =3D ad4080_scale_table, + .num_scales =3D ARRAY_SIZE(ad4080_scale_table), + .num_channels =3D 1, + .channels =3D &ad4080_channel, +}; + +static int ad4080_setup(struct iio_dev *indio_dev) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + struct device *dev =3D regmap_get_device(st->regmap); + unsigned int id; + int ret; + + ret =3D regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, + AD4080_INTERFACE_CONFIG_A_SW_RESET); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, + AD4080_INTERFACE_CONFIG_A_SDO_ENABLE); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD4080_REG_CHIP_TYPE, &id); + if (ret) + return ret; + + if (id !=3D AD4080_CHIP_ID) + dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); + + ret =3D regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A, + AD4080_GPIO_CONFIG_A_GPO_1_EN); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4080_REG_GPIO_CONFIG_B, + FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK, 3)); + if (ret) + return ret; + + ret =3D iio_backend_num_lanes_set(st->back, st->num_lanes); + if (ret) + return ret; + + if (!st->lvds_cnv_en) + return 0; + + ret =3D regmap_update_bits(st->regmap, + AD4080_REG_ADC_DATA_INTF_CONFIG_B, + AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, + FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, 7)); + if (ret) + return ret; + + if (st->num_lanes !=3D 1) { + ret =3D regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES); + if (ret) + return ret; + } + + ret =3D regmap_set_bits(st->regmap, + AD4080_REG_ADC_DATA_INTF_CONFIG_B, + AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN); + if (ret) + return ret; + + return ad4080_lvds_sync_write(st); +} + +static void ad4080_properties_parse(struct ad4080_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + + st->lvds_cnv_en =3D device_property_read_bool(dev, "adi,lvds-cnv-enable"); + + st->num_lanes =3D 1; + device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes); +} + +static int ad4080_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct device *dev =3D &spi->dev; + struct ad4080_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + + ret =3D devm_regulator_bulk_get_enable(dev, + ARRAY_SIZE(ad4080_power_supplies), + ad4080_power_supplies); + if (ret) + return dev_err_probe(dev, ret, + "failed to get and enable supplies\n"); + + st->regmap =3D devm_regmap_init_spi(spi, &ad4080_regmap_config); + if (IS_ERR(st->regmap)) + return PTR_ERR(st->regmap); + + st->info =3D spi_get_device_match_data(spi); + if (!st->info) + return -ENODEV; + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + indio_dev->name =3D st->info->name; + indio_dev->channels =3D st->info->channels; + indio_dev->num_channels =3D st->info->num_channels; + indio_dev->info =3D &ad4080_iio_info; + + ad4080_properties_parse(st); + + st->clk =3D devm_clk_get_enabled(&spi->dev, "cnv"); + if (IS_ERR(st->clk)) + return PTR_ERR(st->clk); + + st->clk_rate =3D clk_get_rate(st->clk); + + st->back =3D devm_iio_backend_get(dev, NULL); + if (IS_ERR(st->back)) + return PTR_ERR(st->back); + + ret =3D devm_iio_backend_request_buffer(dev, st->back, indio_dev); + if (ret) + return ret; + + ret =3D devm_iio_backend_enable(dev, st->back); + if (ret) + return ret; + + ret =3D ad4080_setup(indio_dev); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct spi_device_id ad4080_id[] =3D { + { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad4080_id); + +static const struct of_device_id ad4080_of_match[] =3D { + { .compatible =3D "adi,ad4080", &ad4080_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, ad4080_of_match); + +static struct spi_driver ad4080_driver =3D { + .driver =3D { + .name =3D "ad4080", + .of_match_table =3D ad4080_of_match, + }, + .probe =3D ad4080_probe, + .id_table =3D ad4080_id, +}; +module_spi_driver(ad4080_driver); + +MODULE_AUTHOR("Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v4 10/10] Documetation: ABI: add sinc1 and sinc5+pf1 filter Date: Fri, 2 May 2025 11:59:05 +0300 Message-ID: <20250502085905.24926-11-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250502085905.24926-1-antoniu.miclaus@analog.com> References: <20250502085905.24926-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: H9BvGm4BH8ZpqtPKsUtA_lG3LuGRFl9k X-Authority-Analysis: v=2.4 cv=TpTmhCXh c=1 sm=1 tr=0 ts=6814897e cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=Jj58fO0nKZ7HuPVzIAUA:9 a=+jEqtf1s3R9VXZ0wqowq2kgwd+I=:19 X-Proofpoint-ORIG-GUID: H9BvGm4BH8ZpqtPKsUtA_lG3LuGRFl9k X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDA2OSBTYWx0ZWRfX4pnh5kI+U0+r 86i3i4hO5eXzIbZmrd75SqDUuaWJRw6geSIdjrul8tOG9qsPJ9wMupU6PgpDJtjux8Htl6VoIDm JAgj9i5WyNR/XOKWUEfntMCDLcNwyRBQn+QZR2OYjgTW1YijIkqMCn2Smwj78L/H2tjd01Q8sL3 Vq6cxSjfnnNfj+A7mCg7UCw1ZOnCOYtVR9rcskiSEAvwQT4SA6C542iWEvn4pt1bON6w4mtNN8d PyoeVy6v/CNqKZMxzajDWKoXo9rggsDtTHL43YINgBWqlX/BJ3GsCoo2PZQfDdKFP/46BYT0Glg XyWDbomg10dAjvwhL+twhyXrruI4PuLIDbqQ0o13yWzoCmCWri2G99SzlZn5wnyrK9zmSI49ER4 jIjsMBuTS7dokzZaNRILxPKtlPyPGk+U2ckGuY8mfOUZzRrO5VC2fIMxaq+pcx21eXSPByCF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 impostorscore=0 suspectscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 phishscore=0 mlxlogscore=945 spamscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020069 Content-Type: text/plain; charset="utf-8" Add sinc1 and sinc5+pf1 filter types used for ad4080 device. Add these two options into the filter_type available attribute. Signed-off-by: Antoniu Miclaus --- Documentation/ABI/testing/sysfs-bus-iio | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index b8838cb92d38..2dfb74b5a990 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -2275,6 +2275,8 @@ Description: Reading returns a list with the possible filter modes. Options for the attribute: =20 + * "sinc1" - The digital sinc1 filter. Fast 1st + conversion time. Poor noise performance. * "sinc3" - The digital sinc3 filter. Moderate 1st conversion time. Good noise performance. * "sinc4" - Sinc 4. Excellent noise performance. Long @@ -2290,6 +2292,7 @@ Description: * "sinc3+pf2" - Sinc3 + device specific Post Filter 2. * "sinc3+pf3" - Sinc3 + device specific Post Filter 3. * "sinc3+pf4" - Sinc3 + device specific Post Filter 4. + * "sinc5+pf1" - Sinc5 + device specific Post Filter 1. =20 What: /sys/bus/iio/devices/iio:deviceX/filter_type What: /sys/bus/iio/devices/iio:deviceX/in_voltageY-voltageZ_filter_type --=20 2.49.0