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Thu, 1 May 2025 21:37:46 -0700 From: Robert Lin To: , , , , CC: , , , Robert Lin Subject: [PATCH v7 1/3] clocksource/drivers/timer-tegra186: add WDIOC_GETTIMELEFT support Date: Fri, 2 May 2025 12:37:25 +0800 Message-ID: <20250502043727.396896-2-robelin@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250502043727.396896-1-robelin@nvidia.com> References: <20250502043727.396896-1-robelin@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044AA:EE_|BY5PR12MB4324:EE_ X-MS-Office365-Filtering-Correlation-Id: ace08967-4c28-400d-86f8-08dd89331e52 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2025 04:37:59.9546 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ace08967-4c28-400d-86f8-08dd89331e52 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044AA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4324 Content-Type: text/plain; charset="utf-8" From: Pohsun Su This change adds support for WDIOC_GETTIMELEFT so userspace programs can get the number of seconds before system reset by the watchdog timer via ioctl. Signed-off-by: Pohsun Su Signed-off-by: Robert Lin --- drivers/clocksource/timer-tegra186.c | 64 +++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/tim= er-tegra186.c index ea742889ee06..8d5698770cbd 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2019-2025 NVIDIA Corporation. All rights reserved. */ =20 +#include #include #include #include @@ -30,6 +31,7 @@ =20 #define TMRSR 0x004 #define TMRSR_INTR_CLR BIT(30) +#define TMRSR_PCV GENMASK(28, 0) =20 #define TMRCSSR 0x008 #define TMRCSSR_SRC_USEC (0 << 0) @@ -46,6 +48,9 @@ #define WDTCR_TIMER_SOURCE_MASK 0xf #define WDTCR_TIMER_SOURCE(x) ((x) & 0xf) =20 +#define WDTSR 0x004 +#define WDTSR_CURRENT_EXPIRATION_COUNT GENMASK(14, 12) + #define WDTCMDR 0x008 #define WDTCMDR_DISABLE_COUNTER BIT(1) #define WDTCMDR_START_COUNTER BIT(0) @@ -235,12 +240,69 @@ static int tegra186_wdt_set_timeout(struct watchdog_d= evice *wdd, return 0; } =20 +static unsigned int tegra186_wdt_get_timeleft(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt =3D to_tegra186_wdt(wdd); + u32 expiration, val; + u64 timeleft; + + if (!watchdog_active(&wdt->base)) { + /* return zero if the watchdog timer is not activated. */ + return 0; + } + + /* + * Reset occurs on the fifth expiration of the + * watchdog timer and so when the watchdog timer is configured, + * the actual value programmed into the counter is 1/5 of the + * timeout value. Once the counter reaches 0, expiration count + * will be increased by 1 and the down counter restarts. + * Hence to get the time left before system reset we must + * combine 2 parts: + * 1. value of the current down counter + * 2. (number of counter expirations remaining) * (timeout/5) + */ + + /* Get the current number of counter expirations. Should be a + * value between 0 and 4 + */ + val =3D readl_relaxed(wdt->regs + WDTSR); + expiration =3D FIELD_GET(WDTSR_CURRENT_EXPIRATION_COUNT, val); + if (WARN_ON(expiration > 4)) + return 0; + + /* Get the current counter value in microsecond. */ + val =3D readl_relaxed(wdt->tmr->regs + TMRSR); + timeleft =3D FIELD_GET(TMRSR_PCV, val); + + /* + * Calculate the time remaining by adding the time for the + * counter value to the time of the counter expirations that + * remain. + */ + timeleft +=3D (((u64)wdt->base.timeout * USEC_PER_SEC) / 5) * (4 - expira= tion); + + /* + * Convert the current counter value to seconds, + * rounding up to the nearest second. Cast u64 to + * u32 under the assumption that no overflow happens + * when coverting to seconds. + */ + timeleft =3D (timeleft + USEC_PER_SEC / 2) / USEC_PER_SEC; + + if (WARN_ON(timeleft > U32_MAX)) + return U32_MAX; + + return lower_32_bits(timeleft); +} + static const struct watchdog_ops tegra186_wdt_ops =3D { .owner =3D THIS_MODULE, .start =3D tegra186_wdt_start, .stop =3D tegra186_wdt_stop, .ping =3D tegra186_wdt_ping, .set_timeout =3D tegra186_wdt_set_timeout, + .get_timeleft =3D tegra186_wdt_get_timeleft, }; =20 static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *teg= ra, --=20 2.34.1