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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v3 1/9] opp: add new helper API dev_pm_opp_set_level() Date: Fri, 2 May 2025 08:40:10 +0530 Message-ID: <20250502031018.1292-2-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502031018.1292-1-quic_ptalari@quicinc.com> References: <20250502031018.1292-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: S187y4mWfQrfqtE9FPRzZKeizgHACilE X-Authority-Analysis: v=2.4 cv=KtlN2XWN c=1 sm=1 tr=0 ts=681437bd cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=RqhrKAo0oSNuShJv3MAA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: S187y4mWfQrfqtE9FPRzZKeizgHACilE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAyMSBTYWx0ZWRfX+DL/0TtGi6Vt jbI47N5UVA4rneUF2CNBf9x+V6n5pd+ULtwIInXxiAwF7RVkUhOznH0TtD3c5L1BJ1DQTqReQNj +PMW03HGcNc/QAVP1vt0xGWpJWCM3hsTv5fCyLXDzBLLUMCjmi1NCg5IMMsnHhSDy5AqWfLauA9 84UqrrisdAy+R0vAnm9k1gyvPimnMLialf8qfAxljZXhEqgX6dsc+qRLrUUK6u1TILaPJZlqIbt Fe7bbjropnjCo3CKm/qPni1GhMYV8ZwPnxcOeiQqGH4ebxlVqJh1iePUiudwD2yu0R9c6u81nbc CVR293iVnMrzbGv440c1KunaKpYWd3vRGL+LH1ifNUJ2O2xLDaEcQD8fcA2AchdSHd+9UV9EVMV 0AhiRGCz6C67/5yUu7gtKi53yNtXvmqnbLOjokDp9gXIRrv3o3fVrPdwtbTq3VKPOUQows5E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020021 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To configure a device to a specific performance level, consumer drivers currently need to determine the OPP based on the exact level and then set it, resulting in code duplication across drivers. The new helper API, dev_pm_opp_set_level(), addresses this issue by providing a streamlined method for consumer drivers to find and set the OPP based on the desired performance level, thereby eliminating redundancy. Signed-off-by: Praveen Talari v2 -> v3 - moved function defination to pm_opp.h from core.c with inline - updated return value with IS_ERR(opp) v1 -> v2 - reorder sequence of tags in commit text --- include/linux/pm_opp.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index e7b5c602c92f..31ed8a7b554e 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -197,6 +197,28 @@ int dev_pm_opp_get_sharing_cpus(struct device *cpu_dev= , struct cpumask *cpumask) void dev_pm_opp_remove_table(struct device *dev); void dev_pm_opp_cpumask_remove_table(const struct cpumask *cpumask); int dev_pm_opp_sync_regulators(struct device *dev); + +/* + * dev_pm_opp_set_level() - Configure device for a level + * @dev: device for which we do this operation + * @level: level to set to + * + * Return: 0 on success, a non-zero value if there is an error otherwise. + */ +static inline int dev_pm_opp_set_level(struct device *dev, unsigned int le= vel) +{ + struct dev_pm_opp *opp =3D dev_pm_opp_find_level_exact(dev, level); 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , , Nikunj Kela Subject: [PATCH v3 2/9] dt-bindings: serial: describe SA8255p Date: Fri, 2 May 2025 08:40:11 +0530 Message-ID: <20250502031018.1292-3-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502031018.1292-1-quic_ptalari@quicinc.com> References: <20250502031018.1292-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JbBO0qbbf8wNYaBJ3pAhdEkRjoJxUQOc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAyMSBTYWx0ZWRfXyckAtZ0CF2yM 8yp+KyeFrmIkaWo/vudbejIgwfgqlgrC519fzkN0rS6IaQ0Aqzs+KRKBIpabbUFRW86sctMSMU3 2DvB7LVmLS3H4zBrCMtmvFQ6pkpl0IC8nCYEGrjkx+m2sk7Oi1lcvTrNQcbJpWWdd6aAWFWrkow 6e4R7psTsrWsDlA6/dkdK/ppCykhgnBhSdTBEgj70Zioyf1+E5eQ1BD5T1VoY89N8AZHsFTy+Rz /CzIos5WG5Z8WJ1LlDSJm6tCEwqbAuTgjjePH0uk7RZNizC/0zteMRw8lVGI+DsixKN7lcb/OkQ pi3PBxsO7CBNNjE+EYuAsvwP+J+ctuv7a5JR75zfWW6Bv7llvJnjZysYmWESYVCLPmU6JPlVsYF TbMKzqIHBuzv/RJYe+eN8+hqwJLvS6DSZPPPxjPCQOX7g/muWm68WZ0VqASiKxp3bydqxwkd X-Authority-Analysis: v=2.4 cv=b5qy4sGx c=1 sm=1 tr=0 ts=681437c5 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=rjx3OjMNV77wTL7fGyAA:9 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: JbBO0qbbf8wNYaBJ3pAhdEkRjoJxUQOc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 mlxscore=0 impostorscore=0 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020021 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nikunj Kela SA8255p platform abstracts resources such as clocks, interconnect and GPIO pins configuration in Firmware. SCMI power and perf protocols are used to send request for resource configurations. Add DT bindings for the QUP GENI UART controller on sa8255p platform. Signed-off-by: Nikunj Kela Co-developed-by: Praveen Talari Signed-off-by: Praveen Talari v2 -> v3 - dropped description for interrupt-names - rebased reg property order in required option v1 -> v2 - reorder sequence of tags in commit text - moved reg property after compatible field - added interrupt-names property --- .../serial/qcom,sa8255p-geni-uart.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/qcom,sa8255p-g= eni-uart.yaml diff --git a/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uar= t.yaml b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.ya= ml new file mode 100644 index 000000000000..85b1d7c05079 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,sa8255p-geni-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Geni based QUP UART interface + +maintainers: + - Praveen Talari + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + items: + - description: UART core irq + - description: Wakeup irq (RX GPIO) + + interrupt-names: + items: + - const: uart + - const: wakeup + + power-domains: + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: power + - const: perf + +required: + - compatible + - reg + - interrupts + - power-domains + - power-domain-names + +unevaluatedProperties: false + +examples: + - | + #include + + serial@990000 { + compatible =3D "qcom,sa8255p-geni-uart"; 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , , Nikunj Kela Subject: [PATCH v3 3/9] dt-bindings: qcom: geni-se: describe SA8255p Date: Fri, 2 May 2025 08:40:12 +0530 Message-ID: <20250502031018.1292-4-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502031018.1292-1-quic_ptalari@quicinc.com> References: <20250502031018.1292-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: NVhd4-dbQnFj7pXGAqjOIaNO-NXqHZ2i X-Proofpoint-ORIG-GUID: NVhd4-dbQnFj7pXGAqjOIaNO-NXqHZ2i X-Authority-Analysis: v=2.4 cv=UZZRSLSN c=1 sm=1 tr=0 ts=681437ce cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=v7CWcBsnNxNFVLN3aFYA:9 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAyMSBTYWx0ZWRfXxi0CxqslQwrp 53azCw6nLJ4AH1PIlo5oC2Jopb5HvcV+TMNazNXfnvAqPvXbWTr3MidWJcweowW+FSM/aCAKDOo 4gLQwsQIikYDNv59ffsbNY7HM2I0W/LBPw02d8jePPc1y46TLTBHUJASGFeyDNLdKZ03N+K9yL/ OERKRqcKWvg3aiAHbyQ9IHDZvQzIlPHPRRHWtVVH1hKHSVnGIMuOqLpACJQjWgNCKvwFCirigje cvXbJHU10YY3+nNloI17gHfoeKJVDwhn+hi1Z+Dr30ovGt+gh3PXM2AXzYSU5G842/BrFm3ys2L 1Bs6d60ce9Uol5tw2oTkh6ju7BpdeYU/iGFw+ru5MMwi/0jH3nyaTalLn5WPWW4IZFsNrrMNvPo 26uJ0L/+FzurOGxaSkRr1M1OLpWFQdqY2hKh6yoYBXlZWVk0uMYsdb6L+c6lzJLnfurHjj/Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020021 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nikunj Kela SA8255p platform abstracts resources such as clocks, interconnect configuration in Firmware. Add DT bindings for the QUP Wrapper on sa8255p platform. Signed-off-by: Nikunj Kela Co-developed-by: Praveen Talari Signed-off-by: Praveen Talari v2 -> v3 - reordered required option v1 -> v2 - reorder sequence of tags in commit text - resolved waring errors while encountered in dt binding and dtb check. --- .../soc/qcom/qcom,sa8255p-geni-se-qup.yaml | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p= -geni-se-qup.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-s= e-qup.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-s= e-qup.yaml new file mode 100644 index 000000000000..b66c7c45a6ae --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.y= aml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI Serial Engine QUP Wrapper Controller + +maintainers: + - Praveen Talari + +description: + Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapp= er + is a programmable module for supporting a wide range of serial interfaces + like UART, SPI, I2C, I3C, etc. A single QUP module can provide up to 8 S= erial + Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP + Wrapper controller is modeled as a node with zero or more child nodes ea= ch + representing a serial engine. + +properties: + compatible: + const: qcom,sa8255p-geni-se-qup + + reg: + description: QUP wrapper common register address and length. + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + iommus: + maxItems: 1 + + dma-coherent: true + +patternProperties: + "spi@[0-9a-f]+$": + type: object + description: GENI serial engine based SPI controller. SPI in master mo= de + supports up to 50MHz, up to four chip selects, programmab= le + data path from 4 bits to 32 bits and numerous protocol + variants. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-spi + + "i2c@[0-9a-f]+$": + type: object + description: GENI serial engine based I2C controller. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-i2c + + "serial@[0-9a-f]+$": + type: object + description: GENI Serial Engine based UART Controller. + additionalProperties: true + + properties: + compatible: + enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + +additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + geniqup@9c0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + reg =3D <0 0x9c0000 0 0x6000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + serial@990000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0 0x990000 0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi0_pd 0>, <&scmi0_dvfs 0>; + power-domain-names =3D "power", "perf"; + }; + }; + }; +... --=20 2.17.1 From nobody Mon Feb 9 10:11:43 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7564319E992; Fri, 2 May 2025 03:11:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746155485; cv=none; b=tz1E2giGd0kG0EoqosVbYnn7fLy9pyQKX5kY1gleE95HvQPTMSQYfSG3dcKqoGBh4ngAtv89L9TuMI7oPbwn9d8oNeiz4d139ar8TFjG2P+jYo/RJUNsI1ZxuZkGSvfpKNhX1r0aufUkEUL9H3SGTkRR+GYgkWUiuH4aK8BAf3s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746155485; c=relaxed/simple; bh=GP5Dc3P/OcDRwYIk6e6VkYoWGaN6ntMAwC0QkKOcdJw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aHH9bUiC4EAxpcvKLbrfnD87s6FWLVuGv44qFMWn4KuAqOMLVbQxXvY+OFNL1t/jfKZujDQwMT3xbdKvANwwM36CRDW0bGTfbPUPU2llbqRvpSHSIv8yBo2r9AzIlqbDuaCjmnHyeY9wTb1ArnkGz/cWp4W4d67BaAb6q8jIBfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=B2dSfHys; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="B2dSfHys" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5421N27Y009452; Fri, 2 May 2025 03:11:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=qcppdkim1; bh=vVw3dvZ/YhMx9uo/bo7T5hkv UJVZMtDQpdlx0inPnnU=; b=B2dSfHyshEnHuX2rn4UZHGOuIeHdDQwA0HMMXHih iNheNNI/gKmXccy7oYv5tDvM7fK2/GO7Qawpvs4qcj6yTnBuCpElnQUYpUmycE0k 6MLvUPnJv1Sbsx82q3LQ9WA1GqNjoGcV9cpF8VsQybCYH65LGgMOrhvgpI1voXVq MvpUHMlOWnaVlOWDTHwK0kEbX9baCV/naqeVgH98mHAmbmLYDngrrbEpE7Kyp6AM HCwrDeuBoHuH+AzLZuZBlfG7ETHNunDVq2w6Y4ExXsDYpOM9ynZ3UEDpBBWbUMea qtXNTupoDBAwcCMIMcCFOcprqENvIpo+6egTTZosQ9+eGQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46b6ubq4m9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 May 2025 03:11:18 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5423BHtm013804 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 2 May 2025 03:11:17 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 1 May 2025 20:11:10 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v3 4/9] soc: qcom: geni-se: Enable QUPs on SA8255p Qualcomm platforms Date: Fri, 2 May 2025 08:40:13 +0530 Message-ID: <20250502031018.1292-5-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502031018.1292-1-quic_ptalari@quicinc.com> References: <20250502031018.1292-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: cPVnZo1xoH9mulNSp6jRrUJi0STSMckE X-Authority-Analysis: v=2.4 cv=bsxMBFai c=1 sm=1 tr=0 ts=681437d6 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=-8ewQQW4l5uToJikuzQA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAyMSBTYWx0ZWRfXwfcOrCI32a35 8lQjhKXrBZtdQXM5g/koZ8Snsa2a5eKaLEBmTE0o5wBKXsB+OKTRJwKRP2ZLxyX3BoJ44u7bAgn f4DPomKaKoInmM1739Xoqg2AgEFVXdyIkPcOLExVrosgu9NItcfLEZ0PBv8Uo9pKjnY8IO+NzqG pSi5NftNChVoodChVPr8xXoAqxjePZODbSvHNKxPd6lLsfKgIBqogjBfi36lIFVc2uXusO7H7bh VKrHQx7Y2ikz03biwi7y180hxMi8Z0eE8jdNM2aUWebKaMCRYiiutgKmSMaSH9og+zPhuKXfuIi ybSHldBeyvoRt68KN//4X0P2xEgCcOblomGfQHbb0mKfWqy5//gmFzEqwc04I3hMDxU79rPh4sE xN7kW4igo9TX5Kb30Nju2aWxZmdQwaDvRfG3JaDxCg/JLvKdj46aPKl5BttLsFOSIQPtFsQe X-Proofpoint-ORIG-GUID: cPVnZo1xoH9mulNSp6jRrUJi0STSMckE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 bulkscore=0 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020021 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the sa8255p platform, resources such as clocks,interconnects and TLMM (GPIO) configurations are managed by firmware. Introduce a platform data function callback to distinguish whether resource control is performed by firmware or directly by the driver in linux. The refactor ensures clear differentiation of resource management mechanisms, improving maintainability and flexibility in handling platform-specific configurations. Signed-off-by: Praveen Talari v1 -> v2 - changed datatype of i from int to unsigned int as per comment. --- drivers/soc/qcom/qcom-geni-se.c | 77 +++++++++++++++++++++------------ 1 file changed, 49 insertions(+), 28 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index 4cb959106efa..0e3658b09603 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -105,6 +105,8 @@ struct geni_wrapper { struct geni_se_desc { unsigned int num_clks; const char * const *clks; + int (*geni_se_rsc_init)(struct geni_wrapper *wrapper, + const struct geni_se_desc *desc); }; =20 static const char * const icc_path_names[] =3D {"qup-core", "qup-config", @@ -891,10 +893,44 @@ int geni_icc_disable(struct geni_se *se) } EXPORT_SYMBOL_GPL(geni_icc_disable); =20 +static int geni_se_resource_init(struct geni_wrapper *wrapper, + const struct geni_se_desc *desc) +{ + struct device *dev =3D wrapper->dev; + int ret; + unsigned int i; + + wrapper->num_clks =3D min_t(unsigned int, desc->num_clks, MAX_CLKS); + + for (i =3D 0; i < wrapper->num_clks; ++i) + wrapper->clks[i].id =3D desc->clks[i]; + + ret =3D of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells"= ); + if (ret < 0) { + dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); + return ret; + } + + if (ret < wrapper->num_clks) { + dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n", + dev->of_node, wrapper->num_clks); + return -EINVAL; + } + + ret =3D devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks); + if (ret) { + dev_err(dev, "Err getting clks %d\n", ret); + return ret; + } + + return ret; +} + static int geni_se_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct geni_wrapper *wrapper; + const struct geni_se_desc *desc; int ret; =20 wrapper =3D devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); @@ -906,36 +942,12 @@ static int geni_se_probe(struct platform_device *pdev) if (IS_ERR(wrapper->base)) return PTR_ERR(wrapper->base); =20 - if (!has_acpi_companion(&pdev->dev)) { - const struct geni_se_desc *desc; - int i; - - desc =3D device_get_match_data(&pdev->dev); - if (!desc) - return -EINVAL; - - wrapper->num_clks =3D min_t(unsigned int, desc->num_clks, MAX_CLKS); - - for (i =3D 0; i < wrapper->num_clks; ++i) - wrapper->clks[i].id =3D desc->clks[i]; - - ret =3D of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells= "); - if (ret < 0) { - dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); - return ret; - } + desc =3D device_get_match_data(&pdev->dev); =20 - if (ret < wrapper->num_clks) { - dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n", - dev->of_node, wrapper->num_clks); + if (!has_acpi_companion(&pdev->dev) && desc->geni_se_rsc_init) { + ret =3D desc->geni_se_rsc_init(wrapper, desc); + if (ret) return -EINVAL; - } - - ret =3D devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks); - if (ret) { - dev_err(dev, "Err getting clks %d\n", ret); - return ret; - } } =20 dev_set_drvdata(dev, wrapper); @@ -951,6 +963,13 @@ static const char * const qup_clks[] =3D { static const struct geni_se_desc qup_desc =3D { .clks =3D qup_clks, .num_clks =3D ARRAY_SIZE(qup_clks), + .geni_se_rsc_init =3D geni_se_resource_init, +}; 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v3 5/9] serial: qcom-geni: move resource initialization to separate function Date: Fri, 2 May 2025 08:40:14 +0530 Message-ID: <20250502031018.1292-6-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502031018.1292-1-quic_ptalari@quicinc.com> References: <20250502031018.1292-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=G5AcE8k5 c=1 sm=1 tr=0 ts=681437de cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=0DDkC8yEFXPSaA7UoRYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAyMSBTYWx0ZWRfX0We2Tel0D1Pd ++XXjXGxvHVYD+Wb+pWuS+ZRkqCqDln2F+AzDDHu4jCwc5cN9m4myqAd5C+LYMCwAar3JXfe1vD hDuA96hGfvnTDb+zglXoYhQ9iyn2o5nkAdHJbxK7cBuIfJ05cBDdDREJj0IP3ikBmgMtLIfVYmT YBZWqN6aodvVZyRjMWijg5tSu6JqjNOGTT5acQ12i4vAoW3oJnber/hxA+mfZ2VzIR+E8r94iJy w1O86Od/kyLFHYg0PtNELmtrDkb11fHdbVZyKeWmRhsNVfG/NeZW6TarTTnlRGdLdqOSkUubo8i 1MauD3seh+ysDMj9OgCoD/2MCoMhkuUYyc+HvcSj551a+Blj7lPzFzyX0hOH2g+8ZLlWDWCnq3A obp/0zea3Ba10DhuOYJd072Ilw9MDN8giqsOgyfM+6xukU5tIv6Los1IUdkIj4+gafgJIuGh X-Proofpoint-GUID: iaCLMEQoJhqmBjewcFnLOdJTPxh8VRFl X-Proofpoint-ORIG-GUID: iaCLMEQoJhqmBjewcFnLOdJTPxh8VRFl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 mlxscore=0 malwarescore=0 suspectscore=0 clxscore=1015 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020021 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enhances code readability and future modifications within the new API. Move the code that handles the actual initialization of resources like clock and ICC paths to a separate function, making the probe function cleaner. Signed-off-by: Praveen Talari v1 -> v2 - updated subject description. - added a new line after function end --- drivers/tty/serial/qcom_geni_serial.c | 66 ++++++++++++++++----------- 1 file changed, 40 insertions(+), 26 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 0293b6210aa6..6ad759146f71 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1588,6 +1588,43 @@ static struct uart_driver qcom_geni_uart_driver =3D { .nr =3D GENI_UART_PORTS, }; =20 +static int geni_serial_resource_init(struct qcom_geni_serial_port *port) +{ + int ret; + + port->se.clk =3D devm_clk_get(port->se.dev, "se"); + if (IS_ERR(port->se.clk)) { + ret =3D PTR_ERR(port->se.clk); + dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret); + return ret; + } + + ret =3D geni_icc_get(&port->se, NULL); + if (ret) + return ret; + + port->se.icc_paths[GENI_TO_CORE].avg_bw =3D GENI_DEFAULT_BW; + port->se.icc_paths[CPU_TO_GENI].avg_bw =3D GENI_DEFAULT_BW; + + /* Set BW for register access */ + ret =3D geni_icc_set_bw(&port->se); + if (ret) + return ret; + + ret =3D devm_pm_opp_set_clkname(port->se.dev, "se"); + if (ret) + return ret; + + /* OPP table is optional */ + ret =3D devm_pm_opp_of_add_table(port->se.dev); + if (ret && ret !=3D -ENODEV) { + dev_err(port->se.dev, "invalid OPP table in device tree\n"); + return ret; + } + + return 0; +} + static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { @@ -1690,12 +1727,10 @@ static int qcom_geni_serial_probe(struct platform_d= evice *pdev) port->dev_data =3D data; port->se.dev =3D &pdev->dev; port->se.wrapper =3D dev_get_drvdata(pdev->dev.parent); - port->se.clk =3D devm_clk_get(&pdev->dev, "se"); - if (IS_ERR(port->se.clk)) { - ret =3D PTR_ERR(port->se.clk); - dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); + + ret =3D geni_serial_resource_init(port); + if (ret) return ret; - } =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) @@ -1713,17 +1748,6 @@ static int qcom_geni_serial_probe(struct platform_de= vice *pdev) return -ENOMEM; } =20 - ret =3D geni_icc_get(&port->se, NULL); - if (ret) - return ret; - port->se.icc_paths[GENI_TO_CORE].avg_bw =3D GENI_DEFAULT_BW; - port->se.icc_paths[CPU_TO_GENI].avg_bw =3D GENI_DEFAULT_BW; - - /* Set BW for register access */ - ret =3D geni_icc_set_bw(&port->se); - if (ret) - return ret; - port->name =3D devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v3 6/9] serial: qcom-geni: move resource control logic to separate functions Date: Fri, 2 May 2025 08:40:15 +0530 Message-ID: <20250502031018.1292-7-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502031018.1292-1-quic_ptalari@quicinc.com> References: <20250502031018.1292-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: thKxI7YUZl82a0gbshDQSokxjw9maEBE X-Authority-Analysis: v=2.4 cv=KtlN2XWN c=1 sm=1 tr=0 ts=681437e6 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=HYIVWE9JnHk2aDURxZAA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: thKxI7YUZl82a0gbshDQSokxjw9maEBE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAyMSBTYWx0ZWRfX0xqSING3WFbN s+DcXICa5smJl7D+JXCGBGInCBFVH9sPY2uWooifz30O1dg+4y+XOX1rUgtRXId7gpAPnOZ7BFu YUaejTjB6gg1pMtqBEpFbPRNrJv8vOXhM42Hu0jch4cAtFxYmhpaguHkWTrklSHgvIvAjFv2/iY vLBV5R4R1zWYNlxSGg79BBKPWUxKRL/FmaHJp6uEmF+j3pmZ1g1T1znm6R5h4LqUQoqe19Wtw7O G1CCnrWtGPiE2S6oYlz2pWtrLHLUv75qWeF3TN1H3MpPsZLJAcYNQiOFxvAU3zye3UN2pI7TJO1 ri1zZWIzxvia40VhGjhTXL7cQsEtzyoRUs2RPcNL2bizBr1xvbIvDPTaCjxalBDriTq8YbxMV8J AR1Aar7F5pJkh/KXB/C4KKPIwyiL2VfveodDB16KY30lh+wOIbDeRAZtaOZRyFyq+gJquezE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020021 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Supports use in PM system/runtime frameworks, helping to distinguish new resource control mechanisms and facilitate future modifications within the new API. The code that handles the actual enable or disable of resources like clock and ICC paths to a separate function (geni_serial_resources_on() and geni_serial_resources_off()) which enhances code readability. Signed-off-by: Praveen Talari v1 -> v2 - returned 0 instead of ret variable --- drivers/tty/serial/qcom_geni_serial.c | 54 +++++++++++++++++++++------ 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 6ad759146f71..2cd2085473f3 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1588,6 +1588,42 @@ static struct uart_driver qcom_geni_uart_driver =3D { .nr =3D GENI_UART_PORTS, }; =20 +static int geni_serial_resources_off(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); + int ret; + + dev_pm_opp_set_rate(uport->dev, 0); + ret =3D geni_se_resources_off(&port->se); + if (ret) + return ret; + + geni_icc_disable(&port->se); + + return 0; +} + +static int geni_serial_resources_on(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); + int ret; + + ret =3D geni_icc_enable(&port->se); + if (ret) + return ret; + + ret =3D geni_se_resources_on(&port->se); + if (ret) { + geni_icc_disable(&port->se); + return ret; + } + + if (port->clk_rate) + dev_pm_opp_set_rate(uport->dev, port->clk_rate); + + return 0; +} + static int geni_serial_resource_init(struct qcom_geni_serial_port *port) { int ret; @@ -1628,23 +1664,17 @@ static int geni_serial_resource_init(struct qcom_ge= ni_serial_port *port) static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { - struct qcom_geni_serial_port *port =3D to_dev_port(uport); =20 /* If we've never been called, treat it as off */ if (old_state =3D=3D UART_PM_STATE_UNDEFINED) old_state =3D UART_PM_STATE_OFF; =20 - if (new_state =3D=3D UART_PM_STATE_ON && old_state =3D=3D UART_PM_STATE_O= FF) { - geni_icc_enable(&port->se); - if (port->clk_rate) - dev_pm_opp_set_rate(uport->dev, port->clk_rate); - geni_se_resources_on(&port->se); - } else if (new_state =3D=3D UART_PM_STATE_OFF && - old_state =3D=3D UART_PM_STATE_ON) { - geni_se_resources_off(&port->se); - dev_pm_opp_set_rate(uport->dev, 0); - geni_icc_disable(&port->se); - } + if (new_state =3D=3D UART_PM_STATE_ON && old_state =3D=3D UART_PM_STATE_O= FF) + geni_serial_resources_on(uport); + else if (new_state =3D=3D UART_PM_STATE_OFF && + old_state =3D=3D UART_PM_STATE_ON) + geni_serial_resources_off(uport); + } =20 static const struct uart_ops qcom_geni_console_pops =3D { --=20 2.17.1 From nobody Mon Feb 9 10:11:43 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8481C19D081; Fri, 2 May 2025 03:11:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746155509; cv=none; b=nyQEJfgbIdJR9Pi4O9tvPsu3YW5ihnOM7k05rQu1sJQdqF6kSL+oFj5zlC7fqq7k00Us4W1iki2dB/tvA1nlhqsRjgqJzoy+QSYUxiFHc5Yza6lggMgNeEtht1ppZZ+bikzH8Vn/DqznKnU+LDEd9QrrATiwm8tvkCk4gxuxn68= ARC-Message-Signature: i=1; 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v3 7/9] serial: qcom-geni: move clock-rate logic to separate function Date: Fri, 2 May 2025 08:40:16 +0530 Message-ID: <20250502031018.1292-8-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502031018.1292-1-quic_ptalari@quicinc.com> References: <20250502031018.1292-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAyMSBTYWx0ZWRfX1PWtMNfW8Hui 8BJOp9K8BpcHB7kMT4XpYYPk28mMKxd3iPED1F1ZFGsl2VMVj7pmp7S1cumJIhJF9PHkBnQYx6f jGo58+QOk/jyOfmPQW+qPFcOUzMOJlNY0nmwPaAUb75xCAjAbLY3k/NhtAKg+4P9uxpmmof26yV dtKfV5A3q59hmbro+AkIB9aeigQiCdWg/ROyyYhQ7nd84TQwWcEkDWMyfknrjXj2LipWC+trD2/ D+PULLLSEN68gih6YBlRyh3zsc5Gj3Zd4a/hyIeL7r2CFHzmMm1t2c4HR+tdT6dbaYsndSy4NXn bPAYoiyFv8IxDKJmIH5IoGCCk3FmoeSphpRlYabI9kpZw4oBEheTxeIs14YT2r+OrHsyKezt0bR Xp4O+/o/5Kxh6VAW8GIvkDL7TqulQXWEXCLgEPAbhcftY5K6lIu2fHS8bdeM7nD2X4gyinFQ X-Proofpoint-GUID: _KMxyBX1vE8KX_Q4haZ94T0rkn7ua5Wp X-Authority-Analysis: v=2.4 cv=W404VQWk c=1 sm=1 tr=0 ts=681437ed cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=X08zvMDfRsL5Z2rP0xYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: _KMxyBX1vE8KX_Q4haZ94T0rkn7ua5Wp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 spamscore=0 clxscore=1015 phishscore=0 impostorscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020021 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Facilitates future modifications within the new function, leading to better readability and maintainability of the code. Move the code that handles the actual logic of clock-rate calculations to a separate function geni_serial_set_rate() which enhances code readability. Signed-off-by: Praveen Talari v1 -> v2 - resolved build warnings for datatype format specifiers - removed double spaces in log --- drivers/tty/serial/qcom_geni_serial.c | 62 +++++++++++++++++---------- 1 file changed, 39 insertions(+), 23 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 2cd2085473f3..60afee3884a6 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1283,27 +1283,14 @@ static unsigned long get_clk_div_rate(struct clk *c= lk, unsigned int baud, return ser_clk; } =20 -static void qcom_geni_serial_set_termios(struct uart_port *uport, - struct ktermios *termios, - const struct ktermios *old) +static int geni_serial_set_rate(struct uart_port *uport, unsigned long bau= d) { - unsigned int baud; - u32 bits_per_char; - u32 tx_trans_cfg; - u32 tx_parity_cfg; - u32 rx_trans_cfg; - u32 rx_parity_cfg; - u32 stop_bit_len; - unsigned int clk_div; - u32 ser_clk_cfg; struct qcom_geni_serial_port *port =3D to_dev_port(uport); unsigned long clk_rate; - u32 ver, sampling_rate; unsigned int avg_bw_core; - unsigned long timeout; - - /* baud rate */ - baud =3D uart_get_baud_rate(uport, termios, old, 300, 4000000); + unsigned int clk_div; + u32 ver, sampling_rate; + u32 ser_clk_cfg; =20 sampling_rate =3D UART_OVERSAMPLING; /* Sampling rate is halved for IP versions >=3D 2.5 */ @@ -1315,13 +1302,13 @@ static void qcom_geni_serial_set_termios(struct uar= t_port *uport, sampling_rate, &clk_div); if (!clk_rate) { dev_err(port->se.dev, - "Couldn't find suitable clock rate for %u\n", + "Couldn't find suitable clock rate for %lu\n", baud * sampling_rate); - return; + return -EINVAL; } =20 - dev_dbg(port->se.dev, "desired_rate =3D %u, clk_rate =3D %lu, clk_div =3D= %u\n", - baud * sampling_rate, clk_rate, clk_div); + dev_dbg(port->se.dev, "desired_rate =3D %lu, clk_rate =3D %lu, clk_div = =3D %u\n", + baud * sampling_rate, clk_rate, clk_div); =20 uport->uartclk =3D clk_rate; port->clk_rate =3D clk_rate; @@ -1339,6 +1326,37 @@ static void qcom_geni_serial_set_termios(struct uart= _port *uport, port->se.icc_paths[CPU_TO_GENI].avg_bw =3D Bps_to_icc(baud); geni_icc_set_bw(&port->se); =20 + writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); + writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); + return 0; +} + +static void qcom_geni_serial_set_termios(struct uart_port *uport, + struct ktermios *termios, + const struct ktermios *old) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); + unsigned int baud; + unsigned long timeout; + u32 bits_per_char; + u32 tx_trans_cfg; + u32 tx_parity_cfg; + u32 rx_trans_cfg; + u32 rx_parity_cfg; + u32 stop_bit_len; + int ret =3D 0; + + /* baud rate */ + baud =3D uart_get_baud_rate(uport, termios, old, 300, 4000000); + + ret =3D geni_serial_set_rate(uport, baud); + if (ret) { + dev_err(port->se.dev, + "%s: Failed to set baud:%u ret:%d\n", + __func__, baud, ret); + return; + } + /* parity */ tx_trans_cfg =3D readl(uport->membase + SE_UART_TX_TRANS_CFG); tx_parity_cfg =3D readl(uport->membase + SE_UART_TX_PARITY_CFG); @@ -1406,8 +1424,6 @@ static void qcom_geni_serial_set_termios(struct uart_= port *uport, writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); - writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); - writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); } =20 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE --=20 2.17.1 From nobody Mon Feb 9 10:11:43 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0BFF19D081; Fri, 2 May 2025 03:11:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746155516; cv=none; b=P9aGopzCYqjgaJCEBDcjuTX3ptUxhQ40FoAy+MgBCuqPhhloY+NlHVLwz4x/nH7X/dKlapgqKJ2uQQstsOfNQglnnkINc3KfDa22Ff1rJm9r4haSwviviMIXlxCK3a3DMHaf/JSOsPaekUtwkHvRfMZo7t03kHPnXshKG5SseBo= ARC-Message-Signature: i=1; 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v3 8/9] serial: qcom-geni: Enable PM runtime for serial driver Date: Fri, 2 May 2025 08:40:17 +0530 Message-ID: <20250502031018.1292-9-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502031018.1292-1-quic_ptalari@quicinc.com> References: <20250502031018.1292-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: x6GQF1oLw-f44PIVycctP_CZCsWZUzPu X-Proofpoint-ORIG-GUID: x6GQF1oLw-f44PIVycctP_CZCsWZUzPu X-Authority-Analysis: v=2.4 cv=UZZRSLSN c=1 sm=1 tr=0 ts=681437f6 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=6AnO7isMBx9hvYDJyqkA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAyMSBTYWx0ZWRfX+0WlFGzEQUeJ kVCV9DInwda1wuwlr3RJQCkuw0D6WE86NubFspnoQ6aC28Mgj35pu3n6Gi/R2K9F7vu8tqq01B1 ru1ZuWB6vxO7YOpmRSwMPB8+96lUkfWK70mj24ytly3iBlpK26f53oCXxCrsR1glLYZJFm3YZ8J TuTcds/zuA+xxuX3Lnnxt+pcouyM5egz24n1erLwmBbo6AIbR5FveBeBiu4YDIikWUdzhjiN7+3 l3e37Io5deb+PIHDBHfPX3lNJf5bQveIJc15WjrOSubfmbj5HSyM3bbNBwTzSYLn7lunSwWRsfo OpetWNYPI/CSgc2Sbeg27RMjnb8DAqJs0xxFcVMguqZnrGw8XzZQsDk+Fvjq+PlmwPOMwlfAYYA 8uq6ShHQTHHWXRZ3836d5A3QPnS9F0KBEfHezkMjUzYGqS8QkbXSIdmBBg1aomHbjZltuFwU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020021 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Power Management (PM) runtime support to Qualcomm GENI serial driver. Introduce necessary callbacks and updates to ensure seamless transitions between power states, enhancing overall power efficiency. Signed-off-by: Praveen Talari --- drivers/tty/serial/qcom_geni_serial.c | 33 +++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 60afee3884a6..9d698c354510 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1686,10 +1686,10 @@ static void qcom_geni_serial_pm(struct uart_port *u= port, old_state =3D UART_PM_STATE_OFF; =20 if (new_state =3D=3D UART_PM_STATE_ON && old_state =3D=3D UART_PM_STATE_O= FF) - geni_serial_resources_on(uport); + pm_runtime_resume_and_get(uport->dev); else if (new_state =3D=3D UART_PM_STATE_OFF && old_state =3D=3D UART_PM_STATE_ON) - geni_serial_resources_off(uport); + pm_runtime_put_sync(uport->dev); =20 } =20 @@ -1827,9 +1827,11 @@ static int qcom_geni_serial_probe(struct platform_de= vice *pdev) return ret; } =20 + pm_runtime_enable(port->se.dev); + ret =3D uart_add_one_port(drv, uport); if (ret) - return ret; + goto error; =20 if (port->wakeup_irq > 0) { device_init_wakeup(&pdev->dev, true); @@ -1839,11 +1841,15 @@ static int qcom_geni_serial_probe(struct platform_d= evice *pdev) device_init_wakeup(&pdev->dev, false); ida_free(&port_ida, uport->line); uart_remove_one_port(drv, uport); - return ret; + goto error; } } =20 return 0; + +error: + pm_runtime_disable(port->se.dev); + return ret; } =20 static void qcom_geni_serial_remove(struct platform_device *pdev) @@ -1855,9 +1861,26 @@ static void qcom_geni_serial_remove(struct platform_= device *pdev) dev_pm_clear_wake_irq(&pdev->dev); device_init_wakeup(&pdev->dev, false); ida_free(&port_ida, uport->line); + pm_runtime_disable(port->se.dev); uart_remove_one_port(drv, &port->uport); } =20 +static int qcom_geni_serial_runtime_suspend(struct device *dev) +{ + struct qcom_geni_serial_port *port =3D dev_get_drvdata(dev); + struct uart_port *uport =3D &port->uport; + + return geni_serial_resources_off(uport); +}; + +static int qcom_geni_serial_runtime_resume(struct device *dev) +{ + struct qcom_geni_serial_port *port =3D dev_get_drvdata(dev); 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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v3 9/9] serial: qcom-geni: Enable Serial on SA8255p Qualcomm platforms Date: Fri, 2 May 2025 08:40:18 +0530 Message-ID: <20250502031018.1292-10-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502031018.1292-1-quic_ptalari@quicinc.com> References: <20250502031018.1292-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gZprPK_xlq42Gd23OZUc8uXwt8yIKPr8 X-Proofpoint-ORIG-GUID: gZprPK_xlq42Gd23OZUc8uXwt8yIKPr8 X-Authority-Analysis: v=2.4 cv=UZZRSLSN c=1 sm=1 tr=0 ts=681437fe cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=YJyStIVdxSjxqG8W5N4A:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAyMSBTYWx0ZWRfX4h3ceconJQiz 03qNmqblsC1m2qu4yCjf6B80zXDCV21NMarKPMVIUn1s+u59ChVRP027N6Gl9EeIcoeM8NmrNhG XFUHpBMPSkN7MuC5e+mr7Nu6Puex4/6OSR1QKD/LAF7+BGTSVvGFTupESYJ8aEhc2ANB2LkqZ3l zKP5ejFlAXnQjFcLFoGH/fF9goDsFf99BhIpFwTmZfRbHq5XGV0Sty5WznKKoA5eWuPTte9NRJK V6NwmdnWzNtuljey23+6Yd1z7GGvJqXxHrkQqBrDyByEUTGxa0Bg4WYY4xcNXThx3BlzTOBSETp BiH3trMEvlqArOlMvSGN8kGp29AWfBCXX42uqrCsga7be8w5JuVf9j8Sb9f3U9pNAFz0eunJzTK XGuFBzKVcEOtS4m98zh9O9A9UMObNIoECDuvdwoQ+6NnOnDoKUJKMx5sLmukPotEje7i1+Gi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020021 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power states(on/off). The SCMI performance protocol manages UART baud rates, with each baud rate represented by a performance level. The driver uses the dev_pm_opp_set_level() API to request the desired baud rate by specifying the performance level. Signed-off-by: Praveen Talari --- drivers/tty/serial/qcom_geni_serial.c | 150 +++++++++++++++++++++++--- 1 file changed, 135 insertions(+), 15 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 9d698c354510..51036d5c8ea1 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -99,10 +100,16 @@ #define DMA_RX_BUF_SIZE 2048 =20 static DEFINE_IDA(port_ida); +#define DOMAIN_IDX_POWER 0 +#define DOMAIN_IDX_PERF 1 =20 struct qcom_geni_device_data { bool console; enum geni_se_xfer_mode mode; + struct dev_pm_domain_attach_data pd_data; + int (*geni_serial_pwr_rsc_init)(struct uart_port *uport); + int (*geni_serial_set_rate)(struct uart_port *uport, unsigned long clk_fr= eq); + int (*geni_serial_switch_power_state)(struct uart_port *uport, bool state= ); }; =20 struct qcom_geni_private_data { @@ -140,6 +147,7 @@ struct qcom_geni_serial_port { =20 struct qcom_geni_private_data private_data; const struct qcom_geni_device_data *dev_data; + struct dev_pm_domain_list *pd_list; }; =20 static const struct uart_ops qcom_geni_console_pops; @@ -1331,6 +1339,42 @@ static int geni_serial_set_rate(struct uart_port *up= ort, unsigned long baud) return 0; } =20 +static int geni_serial_set_level(struct uart_port *uport, unsigned long ba= ud) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); + struct device *perf_dev =3D port->pd_list->pd_devs[DOMAIN_IDX_PERF]; + + /* + * The performance protocol sets UART communication + * speeds by selecting different performance levels + * through the OPP framework. + * + * Supported perf levels for baudrates in firmware are below + * +---------------------+--------------------+ + * | Perf level value | Baudrate values | + * +---------------------+--------------------+ + * | 300 | 300 | + * | 1200 | 1200 | + * | 2400 | 2400 | + * | 4800 | 4800 | + * | 9600 | 9600 | + * | 19200 | 19200 | + * | 38400 | 38400 | + * | 57600 | 57600 | + * | 115200 | 115200 | + * | 230400 | 230400 | + * | 460800 | 460800 | + * | 921600 | 921600 | + * | 2000000 | 2000000 | + * | 3000000 | 3000000 | + * | 3200000 | 3200000 | + * | 4000000 | 4000000 | + * +---------------------+--------------------+ + */ + + return dev_pm_opp_set_level(perf_dev, baud); +} + static void qcom_geni_serial_set_termios(struct uart_port *uport, struct ktermios *termios, const struct ktermios *old) @@ -1349,7 +1393,7 @@ static void qcom_geni_serial_set_termios(struct uart_= port *uport, /* baud rate */ baud =3D uart_get_baud_rate(uport, termios, old, 300, 4000000); =20 - ret =3D geni_serial_set_rate(uport, baud); + ret =3D port->dev_data->geni_serial_set_rate(uport, baud); if (ret) { dev_err(port->se.dev, "%s: Failed to set baud:%u ret:%d\n", @@ -1640,8 +1684,27 @@ static int geni_serial_resources_on(struct uart_port= *uport) return 0; } =20 -static int geni_serial_resource_init(struct qcom_geni_serial_port *port) +static int geni_serial_resource_state(struct uart_port *uport, bool power_= on) { + return power_on ? geni_serial_resources_on(uport) : geni_serial_resources= _off(uport); +} + +static int geni_serial_pwr_init(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); + int ret; + + ret =3D dev_pm_domain_attach_list(port->se.dev, + &port->dev_data->pd_data, &port->pd_list); + if (ret <=3D 0) + return -EINVAL; + + return 0; +} + +static int geni_serial_resource_init(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port =3D to_dev_port(uport); int ret; =20 port->se.clk =3D devm_clk_get(port->se.dev, "se"); @@ -1680,7 +1743,6 @@ static int geni_serial_resource_init(struct qcom_geni= _serial_port *port) static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { - /* If we've never been called, treat it as off */ if (old_state =3D=3D UART_PM_STATE_UNDEFINED) old_state =3D UART_PM_STATE_OFF; @@ -1774,13 +1836,16 @@ static int qcom_geni_serial_probe(struct platform_d= evice *pdev) port->se.dev =3D &pdev->dev; port->se.wrapper =3D dev_get_drvdata(pdev->dev.parent); =20 - ret =3D geni_serial_resource_init(port); + ret =3D port->dev_data->geni_serial_pwr_rsc_init(uport); if (ret) return ret; =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; + if (!res) { + ret =3D -EINVAL; + goto error; + } + uport->mapbase =3D res->start; =20 port->tx_fifo_depth =3D DEF_FIFO_DEPTH_WORDS; @@ -1790,19 +1855,26 @@ static int qcom_geni_serial_probe(struct platform_d= evice *pdev) if (!data->console) { port->rx_buf =3D devm_kzalloc(uport->dev, DMA_RX_BUF_SIZE, GFP_KERNEL); - if (!port->rx_buf) - return -ENOMEM; + if (!port->rx_buf) { + ret =3D -ENOMEM; + goto error; + } } =20 port->name =3D devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); - if (!port->name) - return -ENOMEM; + if (!port->name) { + ret =3D -ENOMEM; + goto error; + } =20 irq =3D platform_get_irq(pdev, 0); - if (irq < 0) - return irq; + if (irq < 0) { + ret =3D irq; + goto error; + } + uport->irq =3D irq; uport->has_sysrq =3D IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); =20 @@ -1824,7 +1896,7 @@ static int qcom_geni_serial_probe(struct platform_dev= ice *pdev) IRQF_TRIGGER_HIGH, port->name, uport); if (ret) { dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); - return ret; + goto error; } =20 pm_runtime_enable(port->se.dev); @@ -1849,6 +1921,7 @@ static int qcom_geni_serial_probe(struct platform_dev= ice *pdev) =20 error: pm_runtime_disable(port->se.dev); + dev_pm_domain_detach_list(port->pd_list); return ret; } =20 @@ -1863,22 +1936,31 @@ static void qcom_geni_serial_remove(struct platform= _device *pdev) ida_free(&port_ida, uport->line); pm_runtime_disable(port->se.dev); uart_remove_one_port(drv, &port->uport); + dev_pm_domain_detach_list(port->pd_list); } =20 static int qcom_geni_serial_runtime_suspend(struct device *dev) { struct qcom_geni_serial_port *port =3D dev_get_drvdata(dev); struct uart_port *uport =3D &port->uport; + int ret =3D 0; =20 - return geni_serial_resources_off(uport); + if (port->dev_data->geni_serial_switch_power_state) + ret =3D port->dev_data->geni_serial_switch_power_state(uport, false); + + return ret; }; =20 static int qcom_geni_serial_runtime_resume(struct device *dev) { struct qcom_geni_serial_port *port =3D dev_get_drvdata(dev); struct uart_port *uport =3D &port->uport; + int ret =3D 0; + + if (port->dev_data->geni_serial_switch_power_state) + ret =3D port->dev_data->geni_serial_switch_power_state(uport, true); =20 - return geni_serial_resources_on(uport); + return ret; }; =20 static int qcom_geni_serial_suspend(struct device *dev) @@ -1916,11 +1998,41 @@ static int qcom_geni_serial_resume(struct device *d= ev) static const struct qcom_geni_device_data qcom_geni_console_data =3D { .console =3D true, .mode =3D GENI_SE_FIFO, + .geni_serial_pwr_rsc_init =3D geni_serial_resource_init, + .geni_serial_set_rate =3D geni_serial_set_rate, + .geni_serial_switch_power_state =3D geni_serial_resource_state, }; =20 static const struct qcom_geni_device_data qcom_geni_uart_data =3D { .console =3D false, .mode =3D GENI_SE_DMA, + .geni_serial_pwr_rsc_init =3D geni_serial_resource_init, + .geni_serial_set_rate =3D geni_serial_set_rate, + .geni_serial_switch_power_state =3D geni_serial_resource_state, +}; + +static const struct qcom_geni_device_data sa8255p_qcom_geni_console_data = =3D { + .console =3D true, + .mode =3D GENI_SE_FIFO, + .pd_data =3D { + .pd_flags =3D PD_FLAG_DEV_LINK_ON, + .pd_names =3D (const char*[]) { "power", "perf" }, + .num_pd_names =3D 2, + }, + .geni_serial_pwr_rsc_init =3D geni_serial_pwr_init, + .geni_serial_set_rate =3D geni_serial_set_level, +}; + +static const struct qcom_geni_device_data sa8255p_qcom_geni_uart_data =3D { + .console =3D false, + .mode =3D GENI_SE_DMA, + .pd_data =3D { + .pd_flags =3D PD_FLAG_DEV_LINK_ON, + .pd_names =3D (const char*[]) { "power", "perf" }, + .num_pd_names =3D 2, + }, + .geni_serial_pwr_rsc_init =3D geni_serial_pwr_init, + .geni_serial_set_rate =3D geni_serial_set_level, }; =20 static const struct dev_pm_ops qcom_geni_serial_pm_ops =3D { @@ -1934,10 +2046,18 @@ static const struct of_device_id qcom_geni_serial_m= atch_table[] =3D { .compatible =3D "qcom,geni-debug-uart", .data =3D &qcom_geni_console_data, }, + { + .compatible =3D "qcom,sa8255p-geni-debug-uart", + .data =3D &sa8255p_qcom_geni_console_data, + }, { .compatible =3D "qcom,geni-uart", .data =3D &qcom_geni_uart_data, }, + { + .compatible =3D "qcom,sa8255p-geni-uart", + .data =3D &sa8255p_qcom_geni_uart_data, + }, {} }; MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); --=20 2.17.1