From nobody Fri Dec 19 18:46:38 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11BE6242917; Fri, 2 May 2025 11:04:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746183856; cv=pass; b=Nn8/s6T5ELyjqUKj+0aJboBJdC+uo5JF/mUYEJwJf5XqrQ7liHzw7lURar0X49Ul7Q0sHS1wdnpIeONZcXfOuaaR7derjwFfFqg60jVlnLHDz403/SeRdbkqA6s3sKRtNwR43Z0kNCwhosQlXd84VXPs+yLuMiaur1T6TXmydE0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746183856; c=relaxed/simple; bh=ioMRugEWublB3+wH+i+bFKX5LLNZRZGfDIlj+9/jrZ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UAIJIsO/XBsvnszJ0dzUUuYiqhpNRWbw2YZypWLY1ijn+h9DyEJs7uhCslGwHF7Ke56PaXyI12ANYYpEuYLm+mBmMz3+3PLMRCk/K6eJQybq/cC9SrTNRAkO9mdS0cvvRWqF/V+xz0Rxr+pcggsdzkm/8SRY4BRfpJIOgUY10Z8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=b2Ijr5M8; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="b2Ijr5M8" ARC-Seal: i=1; a=rsa-sha256; t=1746183810; cv=none; d=zohomail.com; s=zohoarc; b=Wuk9VY6+HZcfXuRN67EKlUwM3sJq2okMWDRnwBuDoNSJM1hs4LWAjTwcfPjecsuZl0bNEVm9yvRkMLXdC0HRC6ASybcUQOLCaGIr0UZfzXdfvK3RJ/GZdq0eFlkwVqce8gKE75uDZT1HcgH8jFy/WN6x6/gK3nJhGuoggR7fy48= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746183810; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=vLcyEazL4MwkJMa6AXHbeFliu5XVPS/TvBzOMo6zWY4=; b=Lqkqd2o80YHYSQv8kXOWLuPfX7fonkMpFKE4U+t4dhHen4jYbXLvh3isP7We+vG+qMK3fThd8j156Q521Y6TuiNHm8coJ2CQvfJifVZTIe/knWebZhRNtxhTUd8vImBnO2aHH3jrLL3z7Tk/u3nazV7XMsLgK9PS4dNtlQjGulk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1746183810; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=vLcyEazL4MwkJMa6AXHbeFliu5XVPS/TvBzOMo6zWY4=; b=b2Ijr5M8fYEB1+Ufw1d+lgXzLkzQFssdAb2gNvPiYyYw2mPV2gL5mL0GJS1XCBfk 4tYaniJSDIF0R4J1Kst3rnA7OwiPMDpwDc3fTo2FcTPeztLwDgFrFRlxY2W3dyxwwlN RPZ45TOy1lK18uLonoRxMqc2QWvTzOTqUL+YC37A= Received: by mx.zohomail.com with SMTPS id 1746183809886671.6040478081637; Fri, 2 May 2025 04:03:29 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 02 May 2025 13:03:07 +0200 Subject: [PATCH v3 01/10] dt-bindings: clock: rk3576: add IOC gated clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250502-rk3576-sai-v3-1-376cef19dd7c@collabora.com> References: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> In-Reply-To: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Catalin Marinas , Will Deacon , Sugar Zhang Cc: Luca Ceresoli , Sebastian Reichel , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, Nicolas Frattaroli , Krzysztof Kozlowski X-Mailer: b4 0.14.2 Certain clocks on the RK3576 are additionally essentially "gated" behind some bit toggles in the IOC GRF range. Downstream ungates these by adding a separate clock driver that maps over the GRF range and leaks their implementation of this into the DT. Instead, define some new clock IDs for these, so that consumers of these types of clocks can properly articulate which clock they're using, so that we can then add them to the clock driver for SoCs that need them. Acked-by: Krzysztof Kozlowski Signed-off-by: Nicolas Frattaroli --- include/dt-bindings/clock/rockchip,rk3576-cru.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-b= indings/clock/rockchip,rk3576-cru.h index f576e61bec7041455e10ac18c92f3b33ec0760e3..ded5ce42e62a7f4bc8058fd71b5= e9e1d4580f49c 100644 --- a/include/dt-bindings/clock/rockchip,rk3576-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h @@ -594,4 +594,14 @@ #define SCMI_ARMCLK_B 11 #define SCMI_CLK_GPU 456 =20 +/* IOC-controlled output clocks */ +#define CLK_SAI0_MCLKOUT_TO_IO 571 +#define CLK_SAI1_MCLKOUT_TO_IO 572 +#define CLK_SAI2_MCLKOUT_TO_IO 573 +#define CLK_SAI3_MCLKOUT_TO_IO 574 +#define CLK_SAI4_MCLKOUT_TO_IO 575 +#define CLK_SAI4_MCLKOUT_TO_IO 575 +#define CLK_FSPI0_TO_IO 576 +#define CLK_FSPI1_TO_IO 577 + #endif --=20 2.49.0 From nobody Fri Dec 19 18:46:38 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C50E22E3F0; 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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1746183816; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Tzt9Yvz9LGixXxd7Uq6axcCRPjeonMXipGT1HQAtvdI=; b=OcDI4n38v01Gq9+0EHLUc0v3vsnF0HQeNO0JJCb0GQH7IT3wzxKfISUOqTso/FAg ivFtIFz4b1ccdD7Skg3NVtKYHliNdzl8ZA5RDSOpioM3u1HDq3DcxDnKIbSMYczWbRg Ia3igSFI8spZd6b2WRGDCH/YE1k/VIfHLCa3mt6E= Received: by mx.zohomail.com with SMTPS id 1746183815330431.7592419117924; Fri, 2 May 2025 04:03:35 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 02 May 2025 13:03:08 +0200 Subject: [PATCH v3 02/10] clk: rockchip: introduce auxiliary GRFs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250502-rk3576-sai-v3-2-376cef19dd7c@collabora.com> References: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> In-Reply-To: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Catalin Marinas , Will Deacon , Sugar Zhang Cc: Luca Ceresoli , Sebastian Reichel , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The MUXGRF clock branch type depends on having access to some sort of GRF as a regmap to be registered. So far, we could easily get away with only ever having one GRF stowed away in the context. However, newer Rockchip SoCs, such as the RK3576, have several GRFs which are relevant for clock purposes. It already depends on the pmu0 GRF for MUXGRF reasons, but could get away with not refactoring this because it didn't need the sysgrf at all, so could overwrite the pointer in the clock provider to the pmu0 grf regmap handle. In preparation for needing to finally access more than one GRF per SoC, let's untangle this. Introduce an auxiliary GRF hashmap, and a GRF type enum. The hasmap is keyed by the enum, and clock branches now have a struct member to store the value of that enum, which defaults to the system GRF. The SoC-specific _clk_init function can then insert pointers to GRF regmaps into the hashmap based on the grf type. During clock branch registration, we then pick the right GRF for each branch from the hashmap if something other than the sys GRF is requested. The reason for doing it with this grf type indirection in the clock branches is so that we don't need to define the MUXGRF branches in a separate step, just to have a direct pointer to a regmap available already. Signed-off-by: Nicolas Frattaroli --- drivers/clk/rockchip/clk-rk3288.c | 2 +- drivers/clk/rockchip/clk-rk3328.c | 6 +++--- drivers/clk/rockchip/clk-rk3568.c | 2 +- drivers/clk/rockchip/clk-rk3576.c | 32 ++++++++++++++++++++++---------- drivers/clk/rockchip/clk-rv1126.c | 2 +- drivers/clk/rockchip/clk.c | 17 ++++++++++++++++- drivers/clk/rockchip/clk.h | 29 ++++++++++++++++++++++++++++- 7 files changed, 72 insertions(+), 18 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-r= k3288.c index 90d329216064a5a31cefab723c86088fcb620ea2..0a1e017df7c661e4eb73b236b7a= 9dadde4ac0ff7 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -418,7 +418,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[]= __initdata =3D { RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 11, GFLAGS), MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT, - RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS), + RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS, grf_type_sys), GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0, RK3288_CLKGATE_CON(9), 0, GFLAGS), =20 diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-r= k3328.c index cf60fcf2fa5cde4ef97a05852f071763a4ccee40..cd5f65b6cdf55074c753f1dee96= 972c2a589c260 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -677,9 +677,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[]= __initdata =3D { RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3328_CLKGATE_CON(3), 5, GFLAGS), MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPAR= ENT, - RK3328_GRF_MAC_CON1, 10, 1, MFLAGS), + RK3328_GRF_MAC_CON1, 10, 1, MFLAGS, grf_type_sys), MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_= NO_REPARENT, - RK3328_GRF_SOC_CON4, 14, 1, MFLAGS), + RK3328_GRF_SOC_CON4, 14, 1, MFLAGS, grf_type_sys), =20 COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0, RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS, @@ -692,7 +692,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[]= __initdata =3D { RK3328_CLKSEL_CON(26), 8, 2, DFLAGS, RK3328_CLKGATE_CON(9), 2, GFLAGS), MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_RE= PARENT, - RK3328_GRF_MAC_CON2, 10, 1, MFLAGS), + RK3328_GRF_MAC_CON2, 10, 1, MFLAGS, grf_type_sys), =20 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), =20 diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-r= k3568.c index ed2fb08bd39de81de2127b70ddb184cf66afa3bb..d48ab9d6c064632498a1f7eaff2= 2952e8e62b642 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -591,7 +591,7 @@ static struct rockchip_clk_branch rk3568_clk_branches[]= __initdata =3D { RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(4), 0, GFLAGS), MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(9), 15, 1, MFLAGS), + RK3568_CLKSEL_CON(9), 15, 1, MFLAGS, grf_type_sys), =20 COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(10), 0, 2, DFLAGS, diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-r= k3576.c index be703f250197af2097fa591837de03accb8c51da..7a23683e18ff0d813e7b7fdc339= b9539fa27bc66 100644 --- a/drivers/clk/rockchip/clk-rk3576.c +++ b/drivers/clk/rockchip/clk-rk3576.c @@ -1678,13 +1678,13 @@ static struct rockchip_clk_branch rk3576_clk_branch= es[] __initdata =3D { =20 /* phy ref */ MUXGRF(CLK_PHY_REF_SRC, "clk_phy_ref_src", clk_phy_ref_src_p, 0, - RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS), + RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS, grf_type_pmu0), MUXGRF(CLK_USBPHY_REF_SRC, "clk_usbphy_ref_src", clk_usbphy_ref_src_p, 0, - RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS), + RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS, grf_type_pmu0), MUXGRF(CLK_CPLL_REF_SRC, "clk_cpll_ref_src", clk_cpll_ref_src_p, 0, - RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS), + RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS, grf_type_pmu0), MUXGRF(CLK_AUPLL_REF_SRC, "clk_aupll_ref_src", clk_aupll_ref_src_p, 0, - RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS), + RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS, grf_type_pmu0), =20 /* secure ns */ COMPOSITE_NODIV(ACLK_SECURE_NS, "aclk_secure_ns", mux_350m_175m_116m_24m_= p, CLK_IS_CRITICAL, @@ -1727,13 +1727,14 @@ static void __init rk3576_clk_init(struct device_no= de *np) struct rockchip_clk_provider *ctx; unsigned long clk_nr_clks; void __iomem *reg_base; - struct regmap *grf; + struct rockchip_aux_grf *pmu0_grf_e; + struct regmap *pmu0_grf; =20 clk_nr_clks =3D rockchip_clk_find_max_clk_id(rk3576_clk_branches, ARRAY_SIZE(rk3576_clk_branches)) + 1; =20 - grf =3D syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf"); - if (IS_ERR(grf)) { + pmu0_grf =3D syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf= "); + if (IS_ERR(pmu0_grf)) { pr_err("%s: could not get PMU0 GRF syscon\n", __func__); return; } @@ -1747,11 +1748,16 @@ static void __init rk3576_clk_init(struct device_no= de *np) ctx =3D rockchip_clk_init(np, reg_base, clk_nr_clks); if (IS_ERR(ctx)) { pr_err("%s: rockchip clk init failed\n", __func__); - iounmap(reg_base); - return; + goto err_unmap; } =20 - ctx->grf =3D grf; + pmu0_grf_e =3D kzalloc(sizeof(*pmu0_grf_e), GFP_KERNEL); + if (!pmu0_grf_e) + goto err_unmap; + + pmu0_grf_e->grf =3D pmu0_grf; + pmu0_grf_e->type =3D grf_type_pmu0; + hash_add(ctx->aux_grf_table, &pmu0_grf_e->node, grf_type_pmu0); =20 rockchip_clk_register_plls(ctx, rk3576_pll_clks, ARRAY_SIZE(rk3576_pll_clks), @@ -1774,6 +1780,12 @@ static void __init rk3576_clk_init(struct device_nod= e *np) rockchip_register_restart_notifier(ctx, RK3576_GLB_SRST_FST, NULL); =20 rockchip_clk_of_add_provider(np, ctx); + + return; + +err_unmap: + iounmap(reg_base); + return; } =20 CLK_OF_DECLARE(rk3576_cru, "rockchip,rk3576-cru", rk3576_clk_init); diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-r= v1126.c index fc19c5522490592b449580ea3c286f6d1f5b32cc..15e7bfe84506c30edb25909aae4= 2aa25697649c6 100644 --- a/drivers/clk/rockchip/clk-rv1126.c +++ b/drivers/clk/rockchip/clk-rv1126.c @@ -857,7 +857,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[]= __initdata =3D { RV1126_GMAC_CON, 5, 1, MFLAGS), MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PAR= ENT | CLK_SET_RATE_NO_REPARENT, - RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS), + RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS, grf_type_sys), =20 GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0, RV1126_CLKGATE_CON(20), 7, GFLAGS), diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index cbf93ea119a9e25c037607ded1f6f358918e8656..0f029106d8aaa24ced78b2ef297= 26aa561ef6f0d 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -382,6 +382,8 @@ static struct rockchip_clk_provider *rockchip_clk_init_= base( ctx->cru_node =3D np; spin_lock_init(&ctx->lock); =20 + hash_init(ctx->aux_grf_table); + ctx->grf =3D syscon_regmap_lookup_by_phandle(ctx->cru_node, "rockchip,grf"); =20 @@ -496,6 +498,8 @@ void rockchip_clk_register_branches(struct rockchip_clk= _provider *ctx, struct rockchip_clk_branch *list, unsigned int nr_clk) { + struct regmap *grf =3D ctx->grf; + struct rockchip_aux_grf *agrf; struct clk *clk; unsigned int idx; unsigned long flags; @@ -504,6 +508,17 @@ void rockchip_clk_register_branches(struct rockchip_cl= k_provider *ctx, flags =3D list->flags; clk =3D NULL; =20 + /* for GRF-dependent branches, choose the right grf first */ + if (list->branch_type =3D=3D branch_muxgrf && + list->grf_type !=3D grf_type_sys) { + hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) { + if (agrf->type =3D=3D list->grf_type) { + grf =3D agrf->grf; + break; + } + } + } + /* catch simple muxes */ switch (list->branch_type) { case branch_mux: @@ -526,7 +541,7 @@ void rockchip_clk_register_branches(struct rockchip_clk= _provider *ctx, case branch_muxgrf: clk =3D rockchip_clk_register_muxgrf(list->name, list->parent_names, list->num_parents, - flags, ctx->grf, list->muxdiv_offset, + flags, grf, list->muxdiv_offset, list->mux_shift, list->mux_width, list->mux_flags); break; diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index df2b2d706450f38dfe2b3c7762763c5e832b9892..c136ac54e6213490a995fff5537= 30fa63694dd8f 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -19,6 +19,7 @@ =20 #include #include +#include =20 struct clk; =20 @@ -440,12 +441,35 @@ enum rockchip_pll_type { .k =3D _k, \ } =20 +enum rockchip_grf_type { + grf_type_sys =3D 0, + grf_type_pmu0, + grf_type_pmu1, + grf_type_ioc, +}; + +/* ceil(sqrt(enums in rockchip_grf_type - 1)) */ +#define GRF_HASH_ORDER 2 + +/** + * struct rockchip_aux_grf - entry for the aux_grf_table hashtable + * @grf: pointer to the grf this entry references + * @type: what type of GRF this is + * @node: hlist node + */ +struct rockchip_aux_grf { + struct regmap *grf; + enum rockchip_grf_type type; + struct hlist_node node; +}; + /** * struct rockchip_clk_provider - information about clock provider * @reg_base: virtual address for the register base. * @clk_data: holds clock related data like clk* and number of clocks. * @cru_node: device-node of the clock-provider * @grf: regmap of the general-register-files syscon + * @aux_grf_table: hashtable of auxiliary GRF regmaps, indexed by grf_type * @lock: maintains exclusion between callbacks for a given clock-provider. */ struct rockchip_clk_provider { @@ -453,6 +477,7 @@ struct rockchip_clk_provider { struct clk_onecell_data clk_data; struct device_node *cru_node; struct regmap *grf; + DECLARE_HASHTABLE(aux_grf_table, GRF_HASH_ORDER); spinlock_t lock; }; =20 @@ -660,6 +685,7 @@ struct rockchip_clk_branch { u8 gate_shift; u8 gate_flags; unsigned int linked_clk_id; + enum rockchip_grf_type grf_type; struct rockchip_clk_branch *child; }; =20 @@ -900,7 +926,7 @@ struct rockchip_clk_branch { .mux_table =3D mt, \ } =20 -#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \ +#define MUXGRF(_id, cname, pnames, f, o, s, w, mf, gt) \ { \ .id =3D _id, \ .branch_type =3D branch_muxgrf, \ @@ -913,6 +939,7 @@ struct rockchip_clk_branch { .mux_width =3D w, \ .mux_flags =3D mf, \ .gate_offset =3D -1, \ + .grf_type =3D gt, \ } =20 #define DIV(_id, cname, pname, f, o, s, w, df) \ --=20 2.49.0 From nobody Fri Dec 19 18:46:38 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17A29241671; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250502-rk3576-sai-v3-3-376cef19dd7c@collabora.com> References: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> In-Reply-To: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Catalin Marinas , Will Deacon , Sugar Zhang Cc: Luca Ceresoli , Sebastian Reichel , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Some rockchip SoCs, namely the RK3576, have bits in a General Register File (GRF) that act just like clock gates. The downstream vendor kernel simply maps over the already mapped GRF range with a generic clock gate driver. This solution isn't suitable for upstream, as a memory range will be in use by multiple drivers at the same time, and it leaks implementation details into the device tree. Instead, implement this with a new clock branch type in the Rockchip clock driver: GRF gates. Somewhat akin to MUXGRF, this clock branch depends on the type of GRF, but functions like a gate instead. Signed-off-by: Nicolas Frattaroli --- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk.c | 9 +++- drivers/clk/rockchip/clk.h | 20 ++++++++ drivers/clk/rockchip/gate-grf.c | 105 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 134 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index e8ece20aebfdeffbdc5bfffd2c6f35f2cfcf74f6..f0e0b2c6e876a84610fb3ecf33c= c1935b10058d9 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -14,6 +14,7 @@ clk-rockchip-y +=3D clk-mmc-phase.o clk-rockchip-y +=3D clk-muxgrf.o clk-rockchip-y +=3D clk-ddr.o clk-rockchip-y +=3D gate-link.o +clk-rockchip-y +=3D gate-grf.o clk-rockchip-$(CONFIG_RESET_CONTROLLER) +=3D softrst.o =20 obj-$(CONFIG_CLK_PX30) +=3D clk-px30.o diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 0f029106d8aaa24ced78b2ef29726aa561ef6f0d..34d96aa7cd51b8bde380b4a81ce= 07ffdf24b8593 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -509,7 +509,7 @@ void rockchip_clk_register_branches(struct rockchip_clk= _provider *ctx, clk =3D NULL; =20 /* for GRF-dependent branches, choose the right grf first */ - if (list->branch_type =3D=3D branch_muxgrf && + if ((list->branch_type =3D=3D branch_muxgrf || list->branch_type =3D=3D = branch_grf_gate) && list->grf_type !=3D grf_type_sys) { hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) { if (agrf->type =3D=3D list->grf_type) { @@ -588,6 +588,13 @@ void rockchip_clk_register_branches(struct rockchip_cl= k_provider *ctx, ctx->reg_base + list->gate_offset, list->gate_shift, list->gate_flags, &ctx->lock); break; + case branch_grf_gate: + flags |=3D CLK_SET_RATE_PARENT; + clk =3D rockchip_clk_register_gate_grf(list->name, + list->parent_names[0], flags, grf, + list->gate_offset, list->gate_shift, + list->gate_flags); + break; case branch_composite: clk =3D rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index c136ac54e6213490a995fff553730fa63694dd8f..ebaed429a30dc2c41c866f973f8= cf78b32136311 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -647,6 +647,11 @@ struct clk *rockchip_clk_register_muxgrf(const char *n= ame, int flags, struct regmap *grf, int reg, int shift, int width, int mux_flags); =20 +struct clk *rockchip_clk_register_gate_grf(const char *name, + const char *parent_name, unsigned long flags, + struct regmap *regmap, unsigned int reg, + unsigned int shift, u8 gate_flags); + #define PNAME(x) static const char *const x[] __initconst =20 enum rockchip_clk_branch_type { @@ -656,6 +661,7 @@ enum rockchip_clk_branch_type { branch_divider, branch_fraction_divider, branch_gate, + branch_grf_gate, branch_linked_gate, branch_mmc, branch_inverter, @@ -985,6 +991,20 @@ struct rockchip_clk_branch { .gate_flags =3D gf, \ } =20 +#define GATE_GRF(_id, cname, pname, f, o, b, gf, gt) \ + { \ + .id =3D _id, \ + .branch_type =3D branch_grf_gate, \ + .name =3D cname, \ + .parent_names =3D (const char *[]){ pname }, \ + .num_parents =3D 1, \ + .flags =3D f, \ + .gate_offset =3D o, \ + .gate_shift =3D b, \ + .gate_flags =3D gf, \ + .grf_type =3D gt, \ + } + #define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ { \ .id =3D _id, \ diff --git a/drivers/clk/rockchip/gate-grf.c b/drivers/clk/rockchip/gate-gr= f.c new file mode 100644 index 0000000000000000000000000000000000000000..8122f471f39134a7298be8daf07= 18cfa4f8852a7 --- /dev/null +++ b/drivers/clk/rockchip/gate-grf.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Nicolas Frattaroli + * + * Certain clocks on Rockchip are "gated" behind an additional register bit + * write in a GRF register, such as the SAI MCLKs on RK3576. This code + * implements a clock driver for these types of gates, based on regmaps. + */ + +#include +#include +#include +#include +#include "clk.h" + +struct rockchip_gate_grf { + struct clk_hw hw; + struct regmap *regmap; + unsigned int reg; + unsigned int shift; + u8 flags; +}; + +#define to_gate_grf(_hw) container_of(_hw, struct rockchip_gate_grf, hw) + +static int rockchip_gate_grf_enable(struct clk_hw *hw) +{ + struct rockchip_gate_grf *gate =3D to_gate_grf(hw); + u32 val =3D !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? BIT(gate->shift) := 0; + u32 hiword =3D ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->s= hift + 16); + int ret; + + ret =3D regmap_update_bits(gate->regmap, gate->reg, + hiword | BIT(gate->shift), hiword | val); + + return ret; +} + +static void rockchip_gate_grf_disable(struct clk_hw *hw) +{ + struct rockchip_gate_grf *gate =3D to_gate_grf(hw); + u32 val =3D !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : BIT(gate->shif= t); + u32 hiword =3D ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->s= hift + 16); + + regmap_update_bits(gate->regmap, gate->reg, + hiword | BIT(gate->shift), hiword | val); +} + +static int rockchip_gate_grf_is_enabled(struct clk_hw *hw) +{ + struct rockchip_gate_grf *gate =3D to_gate_grf(hw); + bool invert =3D !!(gate->flags & CLK_GATE_SET_TO_DISABLE); + int ret; + + ret =3D regmap_test_bits(gate->regmap, gate->reg, BIT(gate->shift)); + if (ret < 0) + ret =3D 0; + + return invert ? 1 - ret : ret; + +} + +static const struct clk_ops rockchip_gate_grf_ops =3D { + .enable =3D rockchip_gate_grf_enable, + .disable =3D rockchip_gate_grf_disable, + .is_enabled =3D rockchip_gate_grf_is_enabled, +}; + +struct clk *rockchip_clk_register_gate_grf(const char *name, + const char *parent_name, unsigned long flags, + struct regmap *regmap, unsigned int reg, unsigned int shift, + u8 gate_flags) +{ + struct rockchip_gate_grf *gate; + struct clk_init_data init; + struct clk *clk; + + if (IS_ERR(regmap)) { + pr_err("%s: regmap not available\n", __func__); + return ERR_PTR(-EOPNOTSUPP); + } + + gate =3D kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.flags =3D flags; + init.num_parents =3D parent_name ? 1 : 0; + init.parent_names =3D parent_name ? &parent_name : NULL; + init.ops =3D &rockchip_gate_grf_ops; + + gate->hw.init =3D &init; + gate->regmap =3D regmap; + gate->reg =3D reg; + gate->shift =3D shift; + gate->flags =3D gate_flags; + + clk =3D clk_register(NULL, &gate->hw); + if (IS_ERR(clk)) + kfree(gate); + + return clk; +} --=20 2.49.0 From nobody Fri Dec 19 18:46:38 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66A05245031; Fri, 2 May 2025 11:04:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746183859; cv=pass; b=E1SP0xAiYhjLvgd1eCBiVl4Ame4+T3tE1h9ZZSLlZR7g3fNqlfLwxQBO88ht3v/GRAEaNj2HP1aQneXNzgr8tybwx45SdPJW+obvH40aAqFDmBHyEGsTeSH612ze1vPjeTao2nkMX96CkivgIjBuqqDjIlcbICFx+6+PkVy2KfQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746183859; c=relaxed/simple; bh=dU+hgfPEwS2itaCGKHx6wQyXlgQV1jnm+iPfHOQI1j4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=A0SCtlGcM/JyfbWdCOqvBCZlkyH1Xec/Tn3BYRWOnBjQEkpDc3797XFz7DLRXHWEqKvI30rYvTnxc9b0mR66oatx1sGUL04+Khvx3Z8Li6vABltgJ0zYu4dcIr6t2rurAhbZ2rQgHu9R+dX7KnYcWAJxiUMFXZ/JLCze10voWGg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=LD1VbD8k; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="LD1VbD8k" ARC-Seal: i=1; a=rsa-sha256; t=1746183828; cv=none; d=zohomail.com; s=zohoarc; b=WvGsSoVHqrN+HJACVFuyfdSLUWZHdPchiZ59Ien3craywrtKkw29yy3CyH5jnidq60anKDCLK6rJ9Ipp7bE6o2UQqu+ZIXjIJazuKR4I7QGlKixZJ0lox/0zVkh78SsRVMAE3/NZcVMCd1Z1sWPXjdf2ptYWLjL0jQ/fHjqvA00= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746183828; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Hop8oTkubTw5xWvmcx4MmwlzsXO1N7ei5yW53mT4mNk=; b=VNBP9+xFRAhZ6KTZfM/Ng8Up5vaC+4t/aF3VJi/PjgE1jIMvr9nfwaGCkOXjaKnBaRyW2J6JfJctuGOSzM47Jij3FScWhoGSm7pzqepMD68QJtRyTK70S1f5Mjr5eSeVQP1ojHu6+QzvFCaGzYpp8LibeahLCyPd6hPMibWkUGg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1746183828; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Hop8oTkubTw5xWvmcx4MmwlzsXO1N7ei5yW53mT4mNk=; b=LD1VbD8kAfNPhTDJEIogyb6RpUgwd9ZCluzMYjMEvubaGWLPLgd5bvGeCkI5AzyT x8N98lJMghapzJ5kwkKVSqy1hQNkZlwfDL5gRQMZDpHtbPGrmjupanpk5r8piiwZjw9 /Hb/Mb+MvL6ec2RSggefeJmW2OI2OjPi9DKLnluw= Received: by mx.zohomail.com with SMTPS id 174618382638267.61073827582447; Fri, 2 May 2025 04:03:46 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 02 May 2025 13:03:10 +0200 Subject: [PATCH v3 04/10] clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250502-rk3576-sai-v3-4-376cef19dd7c@collabora.com> References: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> In-Reply-To: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Catalin Marinas , Will Deacon , Sugar Zhang Cc: Luca Ceresoli , Sebastian Reichel , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The Rockchip RK3576 gates the SAI MCLKOUT clocks behind some IOC GRF writes. Add these clock branches, and add the IOC GRF to the auxiliary GRF hashtable. Signed-off-by: Nicolas Frattaroli --- drivers/clk/rockchip/clk-rk3576.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-r= k3576.c index 7a23683e18ff0d813e7b7fdc339b9539fa27bc66..1e269490ac7f6b56ed4e53a711c= 7d4d922b6e149 100644 --- a/drivers/clk/rockchip/clk-rk3576.c +++ b/drivers/clk/rockchip/clk-rk3576.c @@ -15,6 +15,7 @@ =20 #define RK3576_GRF_SOC_STATUS0 0x600 #define RK3576_PMU0_GRF_OSC_CON6 0x18 +#define RK3576_VCCIO_IOC_MISC_CON0 0x6400 =20 enum rk3576_plls { bpll, lpll, vpll, aupll, cpll, gpll, ppll, @@ -1481,6 +1482,14 @@ static struct rockchip_clk_branch rk3576_clk_branche= s[] __initdata =3D { RK3576_CLKGATE_CON(10), 0, GFLAGS), GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0_8ch", 0, RK3576_CLKGATE_CON(10), 1, GFLAGS), + GATE_GRF(CLK_SAI0_MCLKOUT_TO_IO, "mclk_sai0_to_io", "clk_sai0_mclkout", + 0, RK3576_VCCIO_IOC_MISC_CON0, 0, GFLAGS, grf_type_ioc), + GATE_GRF(CLK_SAI1_MCLKOUT_TO_IO, "mclk_sai1_to_io", "clk_sai1_mclkout", + 0, RK3576_VCCIO_IOC_MISC_CON0, 1, GFLAGS, grf_type_ioc), + GATE_GRF(CLK_SAI2_MCLKOUT_TO_IO, "mclk_sai2_to_io", "clk_sai2_mclkout", + 0, RK3576_VCCIO_IOC_MISC_CON0, 2, GFLAGS, grf_type_ioc), + GATE_GRF(CLK_SAI3_MCLKOUT_TO_IO, "mclk_sai3_to_io", "clk_sai3_mclkout", + 0, RK3576_VCCIO_IOC_MISC_CON0, 3, GFLAGS, grf_type_ioc), =20 /* sdgmac */ COMPOSITE_NODIV(HCLK_SDGMAC_ROOT, "hclk_sdgmac_root", mux_200m_100m_50m_2= 4m_p, 0, @@ -1727,7 +1736,9 @@ static void __init rk3576_clk_init(struct device_node= *np) struct rockchip_clk_provider *ctx; unsigned long clk_nr_clks; void __iomem *reg_base; + struct rockchip_aux_grf *ioc_grf_e; struct rockchip_aux_grf *pmu0_grf_e; + struct regmap *ioc_grf; struct regmap *pmu0_grf; =20 clk_nr_clks =3D rockchip_clk_find_max_clk_id(rk3576_clk_branches, @@ -1739,6 +1750,12 @@ static void __init rk3576_clk_init(struct device_nod= e *np) return; } =20 + ioc_grf =3D syscon_regmap_lookup_by_compatible("rockchip,rk3576-ioc-grf"); + if (IS_ERR(ioc_grf)) { + pr_err("%s: could not get IOC GRF syscon\n", __func__); + return; + } + reg_base =3D of_iomap(np, 0); if (!reg_base) { pr_err("%s: could not map cru region\n", __func__); @@ -1759,6 +1776,14 @@ static void __init rk3576_clk_init(struct device_nod= e *np) pmu0_grf_e->type =3D grf_type_pmu0; hash_add(ctx->aux_grf_table, &pmu0_grf_e->node, grf_type_pmu0); =20 + ioc_grf_e =3D kzalloc(sizeof(*ioc_grf_e), GFP_KERNEL); + if (!ioc_grf_e) + goto err_free_pmu0; + + ioc_grf_e->grf =3D ioc_grf; + ioc_grf_e->type =3D grf_type_ioc; + hash_add(ctx->aux_grf_table, &ioc_grf_e->node, grf_type_ioc); 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=KsJ0uu0+k5q97j0fojNsiTYMw+kcsIPUow5pYeDRNeA=; b=E4Y2QTv1+WRePRFi8E1hKzIUehShpcAAhtEGPNPAm+Ja6v+brMxfgOBGuIT/kdaI qD6vC11jwDIRgIuS9liO5AM7dqrMVRIbsuoPdPM6c30FP72K1+W3lKjpBqRyPdNpnZJ HisSr4IT1/fc//dSqJRXxTMgP85SIDkyZnZg3E5E= Received: by mx.zohomail.com with SMTPS id 1746183831926614.9332549402269; Fri, 2 May 2025 04:03:51 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 02 May 2025 13:03:11 +0200 Subject: [PATCH v3 05/10] arm64: dts: rockchip: Add RK3576 SAI nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250502-rk3576-sai-v3-5-376cef19dd7c@collabora.com> References: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> In-Reply-To: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Catalin Marinas , Will Deacon , Sugar Zhang Cc: Luca Ceresoli , Sebastian Reichel , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The RK3576 SoC has 10 SAI controllers in total. Five of them are in the video output power domains, and are used for digital audio output along with the video signal of those, e.g. HDMI audio. The other five, SAI0 through SAI4, are exposed externally. SAI0 and SAI1 are capable of 8-channel audio, whereas SAI2, SAI3 and SAI4 are limited to two channels. These five are in the audio power domain. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 200 +++++++++++++++++++++++++++= ++++ 1 file changed, 200 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index ddc92ccc530d6757660971f0a609b5127784bb04..7bb906c3cb4e80691abf39d0e57= 888f79370bc75 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1010,6 +1010,41 @@ vop_mmu: iommu@27d07e00 { status =3D "disabled"; }; =20 + sai5: sai@27d40000 { + compatible =3D "rockchip,rk3576-sai"; + reg =3D <0x0 0x27d40000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>; + clock-names =3D "mclk", "hclk"; + dmas =3D <&dmac2 3>; + dma-names =3D "rx"; + power-domains =3D <&power RK3576_PD_VO0>; + resets =3D <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>; + reset-names =3D "m", "h"; + rockchip,sai-rx-route =3D <0 1 2 3>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SAI5"; + status =3D "disabled"; + }; + + sai6: sai@27d50000 { + compatible =3D "rockchip,rk3576-sai"; + reg =3D <0x0 0x27d50000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>; + clock-names =3D "mclk", "hclk"; + dmas =3D <&dmac2 4>, <&dmac2 5>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3576_PD_VO0>; + resets =3D <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>; + reset-names =3D "m", "h"; + rockchip,sai-rx-route =3D <0 1 2 3>; + rockchip,sai-tx-route =3D <0 1 2 3>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SAI6"; + status =3D "disabled"; + }; + hdmi: hdmi@27da0000 { compatible =3D "rockchip,rk3576-dw-hdmi-qp"; reg =3D <0x0 0x27da0000 0x0 0x20000>; @@ -1050,6 +1085,57 @@ hdmi_out: port@1 { }; }; =20 + sai7: sai@27ed0000 { + compatible =3D "rockchip,rk3576-sai"; + reg =3D <0x0 0x27ed0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>; + clock-names =3D "mclk", "hclk"; + dmas =3D <&dmac2 19>; + dma-names =3D "tx"; + power-domains =3D <&power RK3576_PD_VO1>; + resets =3D <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>; + reset-names =3D "m", "h"; + rockchip,sai-tx-route =3D <0 1 2 3>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SAI7"; + status =3D "disabled"; + }; + + sai8: sai@27ee0000 { + compatible =3D "rockchip,rk3576-sai"; + reg =3D <0x0 0x27ee0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>; + clock-names =3D "mclk", "hclk"; + dmas =3D <&dmac1 7>; + dma-names =3D "tx"; + power-domains =3D <&power RK3576_PD_VO1>; + resets =3D <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>; + reset-names =3D "m", "h"; + rockchip,sai-tx-route =3D <0 1 2 3>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SAI8"; + status =3D "disabled"; + }; + + sai9: sai@27ef0000 { + compatible =3D "rockchip,rk3576-sai"; + reg =3D <0x0 0x27ef0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>; + clock-names =3D "mclk", "hclk"; + dmas =3D <&dmac0 26>; + dma-names =3D "tx"; + power-domains =3D <&power RK3576_PD_VO1>; + resets =3D <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>; + reset-names =3D "m", "h"; + rockchip,sai-tx-route =3D <0 1 2 3>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SAI9"; + status =3D "disabled"; + }; + qos_hdcp1: qos@27f02000 { compatible =3D "rockchip,rk3576-qos", "syscon"; reg =3D <0x0 0x27f02000 0x0 0x20>; @@ -1596,6 +1682,120 @@ log_leakage: log-leakage@22 { }; }; =20 + sai0: sai@2a600000 { + compatible =3D "rockchip,rk3576-sai"; + reg =3D <0x0 0x2a600000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>; + clock-names =3D "mclk", "hclk"; + dmas =3D <&dmac0 0>, <&dmac0 1>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3576_PD_AUDIO>; + resets =3D <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; + reset-names =3D "m", "h"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sai0m0_lrck + &sai0m0_sclk + &sai0m0_sdi0 + &sai0m0_sdi1 + &sai0m0_sdi2 + &sai0m0_sdi3 + &sai0m0_sdo0 + &sai0m0_sdo1 + &sai0m0_sdo2 + &sai0m0_sdo3>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SAI0"; + status =3D "disabled"; + }; + + sai1: sai@2a610000 { + compatible =3D "rockchip,rk3576-sai"; + reg =3D <0x0 0x2a610000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; + clock-names =3D "mclk", "hclk"; + dmas =3D <&dmac0 2>, <&dmac0 3>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3576_PD_AUDIO>; + resets =3D <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; + reset-names =3D "m", "h"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0 + &sai1m0_sdo1 + &sai1m0_sdo2 + &sai1m0_sdo3>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SAI1"; + status =3D "disabled"; + }; + + sai2: sai@2a620000 { + compatible =3D "rockchip,rk3576-sai"; + reg =3D <0x0 0x2a620000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>; + clock-names =3D "mclk", "hclk"; + dmas =3D <&dmac1 0>, <&dmac1 1>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3576_PD_AUDIO>; + resets =3D <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; + reset-names =3D "m", "h"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sai2m0_lrck + &sai2m0_sclk + &sai2m0_sdi + &sai2m0_sdo>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SAI2"; + status =3D "disabled"; + }; + + sai3: sai@2a630000 { + compatible =3D "rockchip,rk3576-sai"; + reg =3D <0x0 0x2a630000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>; + clock-names =3D "mclk", "hclk"; + dmas =3D <&dmac1 2>, <&dmac1 3>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3576_PD_AUDIO>; + resets =3D <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>; + reset-names =3D "m", "h"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sai3m0_lrck + &sai3m0_sclk + &sai3m0_sdi + &sai3m0_sdo>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SAI3"; + status =3D "disabled"; + }; + + sai4: sai@2a640000 { + compatible =3D "rockchip,rk3576-sai"; + reg =3D <0x0 0x2a640000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>; + clock-names =3D "mclk", "hclk"; + dmas =3D <&dmac2 0>, <&dmac2 1>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3576_PD_AUDIO>; + resets =3D <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>; + reset-names =3D "m", "h"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sai4m0_lrck + &sai4m0_sclk + &sai4m0_sdi + &sai4m0_sdo>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SAI4"; + status =3D "disabled"; + }; + gic: interrupt-controller@2a701000 { compatible =3D "arm,gic-400"; reg =3D <0x0 0x2a701000 0 0x10000>, --=20 2.49.0 From nobody Fri Dec 19 18:46:38 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D757D253F19; Fri, 2 May 2025 11:04:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250502-rk3576-sai-v3-6-376cef19dd7c@collabora.com> References: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> In-Reply-To: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Catalin Marinas , Will Deacon , Sugar Zhang Cc: Luca Ceresoli , Sebastian Reichel , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The RK3576 SoC now has upstream support for HDMI. Add an HDMI audio node, which uses SAI6 as its audio controller according to downstream. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 7bb906c3cb4e80691abf39d0e57888f79370bc75..cb53561f55f3dfb913f40eaab7b= 0c8e090d23c31 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -413,6 +413,22 @@ scmi_clk: protocol@14 { }; }; =20 + hdmi_sound: hdmi-sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "HDMI"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,mclk-fs =3D <256>; + status =3D "disabled"; + + simple-audio-card,codec { + sound-dai =3D <&hdmi>; + }; + + simple-audio-card,cpu { + sound-dai =3D <&sai6>; + }; + }; + pmu_a53: pmu-a53 { compatible =3D "arm,cortex-a53-pmu"; interrupts =3D , @@ -1069,6 +1085,7 @@ hdmi: hdmi@27da0000 { reset-names =3D "ref", "hdp"; rockchip,grf =3D <&ioc_grf>; rockchip,vo-grf =3D <&vo0_grf>; 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Fri, 2 May 2025 04:04:02 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 02 May 2025 13:03:13 +0200 Subject: [PATCH v3 07/10] arm64: dts: rockchip: Add analog audio on RK3576 Sige5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250502-rk3576-sai-v3-7-376cef19dd7c@collabora.com> References: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> In-Reply-To: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Catalin Marinas , Will Deacon , Sugar Zhang Cc: Luca Ceresoli , Sebastian Reichel , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The ArmSoM Sige5 board features an Everest ES8388 codec to provide analog stereo audio output, as well as analog audio input. The codec hangs off the i2c2 bus and responds to address 0x10. It is connected to the SAI1 audio controller of the RK3576, with one SDO (output) lane and one SDI (input) lane. The codec has two sets of outputs. One set, LOUT1/ROUT1, is connected through a set of 22uF non-polarised coupling capacitors to a 3-position connector that appears to be a clone of the JST BM03B-SURS-TF header, and is capable of mating with a JST 03SUR-32S (or JST 03SUR-36L if you prefer lemon-lime) or compatible clone connector. The right headphone output is the one closest to the Type-C DC input connector, the left headphone output is the one in the middle, and the third position, the one closest to the USB3 Type-A host connector, is puzzingly labelled as "HP_GND" in the schematic but is in fact connected to the codecs RIN1 input through a 1uF non-plarised coupling capacitor. LOUT2 and ROUT2 are routed to 1mm test pads T36 and T37 respectively. These are located on the bottom of the board, and do not go through any coupling capacitor. For use as line out, the ES8388 datasheet recommends adding 1uF coupling capacitor if one wishes to use it as a line-level output. There is also a pair of inputs for a stereo microphone, going from two 1mm testpads T34 and T35, which are decoupled with a 100pF capacitor and pulled to 3.3v and ground respectively. These inputs then go through 1uF capacitors each and end up in the LINPUT2 and RINPUT2 pins of the ES8388 codec. The codec's power inputs are routed to receive 3.3V for both its analog and digital inputs, though from different supplies. Signed-off-by: Nicolas Frattaroli --- .../boot/dts/rockchip/rk3576-armsom-sige5.dts | 56 ++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/ar= m64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 570252c4c0bfe56a3c269e47d81fca7676e61787..2c991ad974a95fe1995a8d15eab= a3e7b07d4dfb6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -56,6 +56,34 @@ red_led: red-led { }; }; =20 + es8388_sound: es8388-sound { + compatible =3D "simple-audio-card"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,name =3D "On-board Analog ES8388"; + simple-audio-card,widgets =3D "Microphone", "Headphone Mic", + "Microphone", "Mic Pads", + "Headphone", "Headphone", + "Line Out", "Line Out"; + simple-audio-card,routing =3D "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Line Out", "LOUT2", + "Line Out", "ROUT2", + "RINPUT1", "Headphone Mic", + "LINPUT2", "Mic Pads", + "RINPUT2", "Mic Pads"; + simple-audio-card,pin-switches =3D "Headphone", "Line Out"; + + simple-audio-card,cpu { + sound-dai =3D <&sai1>; + }; + + simple-audio-card,codec { + sound-dai =3D <&es8388>; + system-clock-frequency =3D <12288000>; + }; + }; + vcc_12v0_dcin: regulator-vcc-12v0-dcin { compatible =3D "regulator-fixed"; regulator-name =3D "vcc_12v0_dcin"; @@ -624,6 +652,25 @@ hym8563: rtc@51 { }; }; =20 +&i2c3 { + status =3D "okay"; + + es8388: audio-codec@10 { + compatible =3D "everest,es8388", "everest,es8328"; + reg =3D <0x10>; + clocks =3D <&cru CLK_SAI1_MCLKOUT_TO_IO>; + AVDD-supply =3D <&vcca_3v3_s0>; + DVDD-supply =3D <&vcc_3v3_s0>; + HPVDD-supply =3D <&vcca_3v3_s0>; + PVDD-supply =3D <&vcc_3v3_s0>; + assigned-clocks =3D <&cru CLK_SAI1_MCLKOUT_TO_IO>; + assigned-clock-rates =3D <12288000>; + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sai1m0_mclk>; + }; +}; + &mdio0 { rgmii_phy0: phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; @@ -680,6 +727,15 @@ pcie_reset: pcie-reset { }; }; =20 +&sai1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0>; + status =3D "okay"; +}; + &sdhci { bus-width =3D <8>; full-pwr-cycle-in-suspend; --=20 2.49.0 From nobody Fri Dec 19 18:46:38 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABEA324469A; Fri, 2 May 2025 11:04:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746183881; cv=pass; b=MqdV2lNQMoyheDzQmesLxRVSuL3yDweZeLXk0TtotSksvJlvMtzv76wbSiktvpk4uIvk2tAOINZFKlGE649FAmmuGmWcAKZWXt7UVm0jHGAqgDAUyqbce9wfT+rQG/6H8xbldBPkppAvN+hwjawOQfYNtIuQC6+E8Vfdwaau5Yo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746183881; 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Do this, and also enable the corresponding SAI6 audio controller node. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/ar= m64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 2c991ad974a95fe1995a8d15eaba3e7b07d4dfb6..b09e789c75c47fec7cf7e9810ab= 0dcca32d9404a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -275,6 +275,10 @@ hdmi_out_con: endpoint { }; }; =20 +&hdmi_sound { + status =3D "okay"; +}; + &hdptxphy { status =3D "okay"; }; @@ -736,6 +740,10 @@ &sai1m0_sdi0 status =3D "okay"; }; =20 +&sai6 { + status =3D "okay"; +}; + &sdhci { bus-width =3D <8>; full-pwr-cycle-in-suspend; --=20 2.49.0 From nobody Fri Dec 19 18:46:38 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAB9C25524A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250502-rk3576-sai-v3-9-376cef19dd7c@collabora.com> References: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> In-Reply-To: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Catalin Marinas , Will Deacon , Sugar Zhang Cc: Luca Ceresoli , Sebastian Reichel , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The RK3576 uses Rockchip SAI for audio output. Enable it in the defconfig. Signed-off-by: Nicolas Frattaroli --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 1b8e4abf5fbd8556c6e0c329cdff86512991b2e5..22cf6fb2774aef18c54c2435e4b= 3ff1b94c1a6b1 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1009,6 +1009,7 @@ CONFIG_SND_SOC_SC7280=3Dm CONFIG_SND_SOC_X1E80100=3Dm CONFIG_SND_SOC_ROCKCHIP=3Dm CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=3Dm +CONFIG_SND_SOC_ROCKCHIP_SAI=3Dm CONFIG_SND_SOC_ROCKCHIP_SPDIF=3Dm CONFIG_SND_SOC_ROCKCHIP_RT5645=3Dm CONFIG_SND_SOC_RK3399_GRU_SOUND=3Dm --=20 2.49.0 From nobody Fri Dec 19 18:46:38 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27E55246778; Fri, 2 May 2025 11:04:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250502-rk3576-sai-v3-10-376cef19dd7c@collabora.com> References: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> In-Reply-To: <20250502-rk3576-sai-v3-0-376cef19dd7c@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Catalin Marinas , Will Deacon , Sugar Zhang Cc: Luca Ceresoli , Sebastian Reichel , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The ArmSoM Sige5 board, which is supported in mainline, uses the ES8328 audio driver for audio output on its ES8388 codec controlled through I2C. Enable them as a module. Signed-off-by: Nicolas Frattaroli --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 22cf6fb2774aef18c54c2435e4b3ff1b94c1a6b1..c5a3d35e6196029560da4f39a52= 98c532756a670 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1048,6 +1048,8 @@ CONFIG_SND_SOC_DA7213=3Dm CONFIG_SND_SOC_ES7134=3Dm CONFIG_SND_SOC_ES7241=3Dm CONFIG_SND_SOC_ES8316=3Dm +CONFIG_SND_SOC_ES8328=3Dm +CONFIG_SND_SOC_ES8328_I2C=3Dm CONFIG_SND_SOC_GTM601=3Dm CONFIG_SND_SOC_MSM8916_WCD_ANALOG=3Dm CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=3Dm --=20 2.49.0