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Also, make sure that all buffers are released during streamoff. Cc: stable@vger.kernel.org Fixes: 73702f45db81 ("media: iris: allocate, initialize and queue internal = buffers") Reviewed-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_buffer.c | 20 +++++++++++++++- drivers/media/platform/qcom/iris/iris_buffer.h | 3 ++- drivers/media/platform/qcom/iris/iris_vdec.c | 4 ++-- drivers/media/platform/qcom/iris/iris_vidc.c | 33 ++++++++++++++++++++++= ++-- 4 files changed, 54 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index e5c5a564fcb8..981fedb000ed 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -376,7 +376,7 @@ int iris_destroy_internal_buffer(struct iris_inst *inst= , struct iris_buffer *buf return 0; } =20 -int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane) +static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane= , bool force) { const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; struct iris_buffer *buf, *next; @@ -396,6 +396,14 @@ int iris_destroy_internal_buffers(struct iris_inst *in= st, u32 plane) for (i =3D 0; i < len; i++) { buffers =3D &inst->buffers[internal_buf_type[i]]; list_for_each_entry_safe(buf, next, &buffers->list, list) { + /* + * during stream on, skip destroying internal(DPB) buffer + * if firmware did not return it. + * during close, destroy all buffers irrespectively. + */ + if (!force && buf->attr & BUF_ATTR_QUEUED) + continue; + ret =3D iris_destroy_internal_buffer(inst, buf); if (ret) return ret; @@ -405,6 +413,16 @@ int iris_destroy_internal_buffers(struct iris_inst *in= st, u32 plane) return 0; } =20 +int iris_destroy_all_internal_buffers(struct iris_inst *inst, u32 plane) +{ + return iris_destroy_internal_buffers(inst, plane, true); +} + +int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 pla= ne) +{ + return iris_destroy_internal_buffers(inst, plane, false); +} + static int iris_release_internal_buffers(struct iris_inst *inst, enum iris_buffer_type buffer_type) { diff --git a/drivers/media/platform/qcom/iris/iris_buffer.h b/drivers/media= /platform/qcom/iris/iris_buffer.h index c36b6347b077..00825ad2dc3a 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_buffer.h @@ -106,7 +106,8 @@ void iris_get_internal_buffers(struct iris_inst *inst, = u32 plane); int iris_create_internal_buffers(struct iris_inst *inst, u32 plane); int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane); int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffe= r *buffer); -int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane); +int iris_destroy_all_internal_buffers(struct iris_inst *inst, u32 plane); +int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 pla= ne); int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst); int iris_alloc_and_queue_input_int_bufs(struct iris_inst *inst); int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf); diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index 4143acedfc57..9c049b9671cc 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -408,7 +408,7 @@ int iris_vdec_streamon_input(struct iris_inst *inst) =20 iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); =20 - ret =3D iris_destroy_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MP= LANE); + ret =3D iris_destroy_dequeued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_= OUTPUT_MPLANE); if (ret) return ret; =20 @@ -496,7 +496,7 @@ int iris_vdec_streamon_output(struct iris_inst *inst) =20 iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); =20 - ret =3D iris_destroy_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_M= PLANE); + ret =3D iris_destroy_dequeued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_= CAPTURE_MPLANE); if (ret) return ret; =20 diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index ca0f4e310f77..a8144595cc78 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -221,6 +221,33 @@ static void iris_session_close(struct iris_inst *inst) iris_wait_for_session_response(inst, false); } =20 +static void iris_check_num_queued_internal_buffers(struct iris_inst *inst,= u32 plane) +{ + const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + struct iris_buffer *buf, *next; + struct iris_buffers *buffers; + const u32 *internal_buf_type; + u32 internal_buffer_count, i; + u32 count =3D 0; + + if (V4L2_TYPE_IS_OUTPUT(plane)) { + internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + } else { + internal_buf_type =3D platform_data->dec_op_int_buf_tbl; + internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + } + + for (i =3D 0; i < internal_buffer_count; i++) { + buffers =3D &inst->buffers[internal_buf_type[i]]; + list_for_each_entry_safe(buf, next, &buffers->list, list) + count++; + if (count) + dev_err(inst->core->dev, "%d buffer of type %d not released", + count, internal_buf_type[i]); + } +} + int iris_close(struct file *filp) { struct iris_inst *inst =3D iris_get_inst(filp, NULL); @@ -233,8 +260,10 @@ int iris_close(struct file *filp) iris_session_close(inst); iris_inst_change_state(inst, IRIS_INST_DEINIT); iris_v4l2_fh_deinit(inst); - iris_destroy_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 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Thu, 01 May 2025 19:14:07 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 541JE63G021971 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 1 May 2025 19:14:06 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 1 May 2025 12:14:00 -0700 From: Dikshita Agarwal Date: Fri, 2 May 2025 00:43:32 +0530 Subject: [PATCH v3 02/23] media: iris: Update CAPTURE format info based on OUTPUT format Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250502-qcom-iris-hevc-vp9-v3-2-552158a10a7d@quicinc.com> References: <20250502-qcom-iris-hevc-vp9-v3-0-552158a10a7d@quicinc.com> In-Reply-To: <20250502-qcom-iris-hevc-vp9-v3-0-552158a10a7d@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Mauro Carvalho Chehab , Stefan Schmidt , Hans Verkuil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Bryan O'Donoghue , Dmitry Baryshkov , Neil Armstrong , Nicolas Dufresne , , , , , Dikshita Agarwal , <20250417-topic-sm8x50-iris-v10-v7-0-f020cb1d0e98@linaro.org>, <20250424-qcs8300_iris-v5-0-f118f505c300@quicinc.com>, X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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This is required to set the updated capture resolution to firmware when S_FMT is called only for OUTPUT. Cc: stable@vger.kernel.org Fixes: b530b95de22c ("media: iris: implement s_fmt, g_fmt and try_fmt ioctl= s") Reviewed-by: Bryan O'Donoghue Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_vdec.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index 9c049b9671cc..d342f733feb9 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -171,6 +171,11 @@ int iris_vdec_s_fmt(struct iris_inst *inst, struct v4l= 2_format *f) output_fmt->fmt.pix_mp.ycbcr_enc =3D f->fmt.pix_mp.ycbcr_enc; output_fmt->fmt.pix_mp.quantization =3D f->fmt.pix_mp.quantization; =20 + /* Update capture format based on new ip w/h */ + output_fmt->fmt.pix_mp.width =3D ALIGN(f->fmt.pix_mp.width, 128); + output_fmt->fmt.pix_mp.height =3D ALIGN(f->fmt.pix_mp.height, 32); + inst->buffers[BUF_OUTPUT].size =3D iris_get_buffer_size(inst, BUF_OUTPUT= ); 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Thu, 1 May 2025 19:14:13 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 1 May 2025 12:14:07 -0700 From: Dikshita Agarwal Date: Fri, 2 May 2025 00:43:33 +0530 Subject: [PATCH v3 03/23] media: iris: Avoid updating frame size to firmware during reconfig Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250502-qcom-iris-hevc-vp9-v3-3-552158a10a7d@quicinc.com> References: <20250502-qcom-iris-hevc-vp9-v3-0-552158a10a7d@quicinc.com> In-Reply-To: <20250502-qcom-iris-hevc-vp9-v3-0-552158a10a7d@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Mauro Carvalho Chehab , Stefan Schmidt , Hans Verkuil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Bryan O'Donoghue , Dmitry Baryshkov , Neil Armstrong , Nicolas Dufresne , , , , , Dikshita Agarwal , <20250417-topic-sm8x50-iris-v10-v7-0-f020cb1d0e98@linaro.org>, <20250424-qcs8300_iris-v5-0-f118f505c300@quicinc.com>, X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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If the driver sends the same resolution back to the firmware the resolution will be aligned to 16 bytes not 8. The alignment mismatch would then subsequently cause the firmware to send another redundant sequence change event. Fix this by not setting the resolution property during reconfig. Cc: stable@vger.kernel.org Fixes: 3a19d7b9e08b ("media: iris: implement set properties to firmware dur= ing streamon") Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c | 15 ++++++++----= --- drivers/media/platform/qcom/iris/iris_state.c | 2 +- drivers/media/platform/qcom/iris/iris_state.h | 1 + 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 64f887d9a17d..2a86c27443ea 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -546,14 +546,15 @@ static int iris_hfi_gen1_set_resolution(struct iris_i= nst *inst) struct hfi_framesize fs; int ret; =20 - fs.buffer_type =3D HFI_BUFFER_INPUT; - fs.width =3D inst->fmt_src->fmt.pix_mp.width; - fs.height =3D inst->fmt_src->fmt.pix_mp.height; - - ret =3D hfi_gen1_set_property(inst, ptype, &fs, sizeof(fs)); - if (ret) - return ret; + if (!iris_drc_pending(inst)) { + fs.buffer_type =3D HFI_BUFFER_INPUT; + fs.width =3D inst->fmt_src->fmt.pix_mp.width; + fs.height =3D inst->fmt_src->fmt.pix_mp.height; =20 + ret =3D hfi_gen1_set_property(inst, ptype, &fs, sizeof(fs)); + if (ret) + return ret; + } fs.buffer_type =3D HFI_BUFFER_OUTPUT2; fs.width =3D inst->fmt_dst->fmt.pix_mp.width; fs.height =3D inst->fmt_dst->fmt.pix_mp.height; diff --git a/drivers/media/platform/qcom/iris/iris_state.c b/drivers/media/= platform/qcom/iris/iris_state.c index 5976e926c83d..104e1687ad39 100644 --- a/drivers/media/platform/qcom/iris/iris_state.c +++ b/drivers/media/platform/qcom/iris/iris_state.c @@ -245,7 +245,7 @@ int iris_inst_sub_state_change_pause(struct iris_inst *= inst, u32 plane) return iris_inst_change_sub_state(inst, 0, set_sub_state); } =20 -static inline bool iris_drc_pending(struct iris_inst *inst) +bool iris_drc_pending(struct iris_inst *inst) { return inst->sub_state & IRIS_INST_SUB_DRC && inst->sub_state & IRIS_INST_SUB_DRC_LAST; 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However, firmware can send some responses on other port as well. Remove the strict port validation to correctly handle session property responses from the firmware. Cc: stable@vger.kernel.org Fixes: 3a19d7b9e08b ("media: iris: implement set properties to firmware dur= ing streamon") Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index b75a01641d5d..d1a2a497a7b2 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -636,9 +636,6 @@ static int iris_hfi_gen2_handle_session_property(struct= iris_inst *inst, { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); =20 - if (pkt->port !=3D HFI_PORT_BITSTREAM) - return 0; - if (pkt->flags & HFI_FW_FLAGS_INFORMATION) return 0; =20 --=20 2.34.1 From nobody Mon Feb 9 02:38:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D904226D18; 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Thu, 01 May 2025 19:14:26 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 541JEP8o002405 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 1 May 2025 19:14:25 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 1 May 2025 12:14:19 -0700 From: Dikshita Agarwal Date: Fri, 2 May 2025 00:43:35 +0530 Subject: [PATCH v3 05/23] media: iris: Prevent HFI queue writes when core is in deinit state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250502-qcom-iris-hevc-vp9-v3-5-552158a10a7d@quicinc.com> References: <20250502-qcom-iris-hevc-vp9-v3-0-552158a10a7d@quicinc.com> In-Reply-To: <20250502-qcom-iris-hevc-vp9-v3-0-552158a10a7d@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Mauro Carvalho Chehab , Stefan Schmidt , Hans Verkuil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Bryan O'Donoghue , Dmitry Baryshkov , Neil Armstrong , Nicolas Dufresne , , , , , Dikshita Agarwal , <20250417-topic-sm8x50-iris-v10-v7-0-f020cb1d0e98@linaro.org>, <20250424-qcs8300_iris-v5-0-f118f505c300@quicinc.com>, X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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However, the core can also transition to the deinit state due to a system error triggered by the response thread. In such cases, writing to the HFI queues should not be allowed. Fix this by adding a check for the core deinit state, ensuring that writes are rejected when core is not in a valid state. Cc: stable@vger.kernel.org Fixes: fb583a214337 ("media: iris: introduce host firmware interface with n= ecessary hooks") Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_hfi_queue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_queue.c b/drivers/me= dia/platform/qcom/iris/iris_hfi_queue.c index fac7df0c4d1a..221dcd09e1e1 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_queue.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_queue.c @@ -113,7 +113,7 @@ int iris_hfi_queue_cmd_write_locked(struct iris_core *c= ore, void *pkt, u32 pkt_s { struct iris_iface_q_info *q_info =3D &core->command_queue; =20 - if (core->state =3D=3D IRIS_CORE_ERROR) + if (core->state =3D=3D IRIS_CORE_ERROR || core->state =3D=3D IRIS_CORE_DE= INIT) return -EINVAL; =20 if (!iris_hfi_queue_write(q_info, pkt, pkt_size)) { --=20 2.34.1 From nobody Mon Feb 9 02:38:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56979226D18; 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Thu, 01 May 2025 19:14:32 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 541JEVgt029510 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 1 May 2025 19:14:31 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 1 May 2025 12:14:25 -0700 From: Dikshita Agarwal Date: Fri, 2 May 2025 00:43:36 +0530 Subject: [PATCH v3 06/23] media: iris: Remove deprecated property setting to firmware Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250502-qcom-iris-hevc-vp9-v3-6-552158a10a7d@quicinc.com> References: <20250502-qcom-iris-hevc-vp9-v3-0-552158a10a7d@quicinc.com> In-Reply-To: <20250502-qcom-iris-hevc-vp9-v3-0-552158a10a7d@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Mauro Carvalho Chehab , Stefan Schmidt , Hans Verkuil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Bryan O'Donoghue , Dmitry Baryshkov , Neil Armstrong , Nicolas Dufresne , , , , , Dikshita Agarwal , <20250417-topic-sm8x50-iris-v10-v7-0-f020cb1d0e98@linaro.org>, <20250424-qcs8300_iris-v5-0-f118f505c300@quicinc.com>, X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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At the same time, remove the check for non-zero number of v4l2 controls as some SOC might not expose any capability which requires v4l2 control. Cc: stable@vger.kernel.org Fixes: 79865252acb6 ("media: iris: enable video driver probe of SM8250 SoC") Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_ctrls.c | 6 ------ drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c | 8 -------- drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h | 1 - drivers/media/platform/qcom/iris/iris_platform_common.h | 2 +- drivers/media/platform/qcom/iris/iris_platform_sm8250.c | 9 --------- 5 files changed, 1 insertion(+), 25 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index b690578256d5..915de101fcba 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -17,8 +17,6 @@ static inline bool iris_valid_cap_id(enum platform_inst_f= w_cap_type cap_id) static enum platform_inst_fw_cap_type iris_get_cap_id(u32 id) { switch (id) { - case V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER: - return DEBLOCK; case V4L2_CID_MPEG_VIDEO_H264_PROFILE: return PROFILE; case V4L2_CID_MPEG_VIDEO_H264_LEVEL: @@ -34,8 +32,6 @@ static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_typ= e cap_id) return 0; =20 switch (cap_id) { - case DEBLOCK: - return V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER; case PROFILE: return V4L2_CID_MPEG_VIDEO_H264_PROFILE; case LEVEL: @@ -84,8 +80,6 @@ int iris_ctrls_init(struct iris_inst *inst) if (iris_get_v4l2_id(cap[idx].cap_id)) num_ctrls++; } - if (!num_ctrls) - return -EINVAL; =20 /* Adding 1 to num_ctrls to include V4L2_CID_MIN_BUFFERS_FOR_CAPTURE */ =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 2a86c27443ea..ce855a20ce4b 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -490,14 +490,6 @@ iris_hfi_gen1_packet_session_set_property(struct hfi_s= ession_set_property_pkt *p packet->shdr.hdr.size +=3D sizeof(u32) + sizeof(*wm); break; } - case HFI_PROPERTY_CONFIG_VDEC_POST_LOOP_DEBLOCKER: { - struct hfi_enable *en =3D prop_data; - u32 *in =3D pdata; - - en->enable =3D *in; - packet->shdr.hdr.size +=3D sizeof(u32) + sizeof(*en); - break; - } default: return -EINVAL; } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index 9f246816a286..e178604855c1 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -65,7 +65,6 @@ =20 #define HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS 0x202001 =20 -#define HFI_PROPERTY_CONFIG_VDEC_POST_LOOP_DEBLOCKER 0x1200001 #define HFI_PROPERTY_PARAM_VDEC_DPB_COUNTS 0x120300e #define HFI_PROPERTY_CONFIG_VDEC_ENTROPY 0x1204004 =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index ac76d9e1ef9c..1dab276431c7 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -89,7 +89,7 @@ enum platform_inst_fw_cap_type { CODED_FRAMES, BIT_DEPTH, RAP_FRAME, - DEBLOCK, + TIER, INST_FW_CAP_MAX, }; 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As a result, the firmware properties were not being set correctly. Fix this by properly assigning the function pointers from the core capability to the instance capability, ensuring that the properties are correctly applied to the firmware. Cc: stable@vger.kernel.org Fixes: 3a19d7b9e08b ("media: iris: implement set properties to firmware dur= ing streamon") Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_ctrls.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 915de101fcba..13f5cf0d0e8a 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -157,6 +157,7 @@ void iris_session_init_caps(struct iris_core *core) core->inst_fw_caps[cap_id].value =3D caps[i].value; core->inst_fw_caps[cap_id].flags =3D caps[i].flags; core->inst_fw_caps[cap_id].hfi_id =3D caps[i].hfi_id; + core->inst_fw_caps[cap_id].set =3D caps[i].set; } } =20 --=20 2.34.1 From nobody Mon Feb 9 02:38:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7CC722A4DA; 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To fix this, add a check to validate that the argument passed is not null before accessing its members. Cc: stable@vger.kernel.org Fixes: fb583a214337 ("media: iris: introduce host firmware interface with n= ecessary hooks") Reported-by: Dan Carpenter Closes: https://lore.kernel.org/linux-media/634cc9b8-f099-4b54-8556-d879fb2= b5169@stanley.mountain/ Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index d1a2a497a7b2..4488540d1d41 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -265,7 +265,8 @@ static int iris_hfi_gen2_handle_system_error(struct iri= s_core *core, { struct iris_inst *instance; =20 - dev_err(core->dev, "received system error of type %#x\n", pkt->type); + if (pkt) + dev_err(core->dev, "received system error of type %#x\n", pkt->type); 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Cc: stable@vger.kernel.org Fixes: 3a19d7b9e08b ("media: iris: implement set properties to firmware dur= ing streamon") Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index a908b41e2868..802fa62c26eb 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -178,7 +178,7 @@ static int iris_hfi_gen2_set_crop_offsets(struct iris_i= nst *inst) sizeof(u64)); } =20 -static int iris_hfi_gen2_set_bit_dpeth(struct iris_inst *inst) +static int iris_hfi_gen2_set_bit_depth(struct iris_inst *inst) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 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Due to timing issue, the flush response corresponding to the first command could arrive after the second flush is issued. This casuses the driver to incorrectly assume that the second flush has completed, leading to the premature signaling of flush_completion. To address this, introduce a counter to track the number of pending flush responses and signal flush completion only when all expected responses are received. Cc: stable@vger.kernel.org Fixes: 11712ce70f8e ("media: iris: implement vb2 streaming ops") Reviewed-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- .../media/platform/qcom/iris/iris_hfi_gen1_command.c | 4 +++- .../media/platform/qcom/iris/iris_hfi_gen1_response.c | 17 +++++++++++--= ---- drivers/media/platform/qcom/iris/iris_instance.h | 2 ++ 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index ce855a20ce4b..bd9d86220e61 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -208,8 +208,10 @@ static int iris_hfi_gen1_session_stop(struct iris_inst= *inst, u32 plane) flush_pkt.flush_type =3D flush_type; =20 ret =3D iris_hfi_queue_cmd_write(core, &flush_pkt, flush_pkt.shdr.hdr.si= ze); - if (!ret) + if (!ret) { + inst->flush_responses_pending++; ret =3D iris_wait_for_session_response(inst, true); + } } =20 return ret; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index b72d503dd740..271e14469223 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -207,7 +207,8 @@ static void iris_hfi_gen1_event_seq_changed(struct iris= _inst *inst, flush_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_FLUSH; flush_pkt.shdr.session_id =3D inst->session_id; flush_pkt.flush_type =3D HFI_FLUSH_OUTPUT; - iris_hfi_queue_cmd_write(inst->core, &flush_pkt, flush_pkt.shdr.hdr.size= ); + if (!iris_hfi_queue_cmd_write(inst->core, &flush_pkt, flush_pkt.shdr.hdr= .size)) + inst->flush_responses_pending++; } =20 iris_vdec_src_change(inst); @@ -408,7 +409,9 @@ static void iris_hfi_gen1_session_ftb_done(struct iris_= inst *inst, void *packet) flush_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_FLUSH; flush_pkt.shdr.session_id =3D inst->session_id; flush_pkt.flush_type =3D HFI_FLUSH_OUTPUT; - iris_hfi_queue_cmd_write(core, &flush_pkt, flush_pkt.shdr.hdr.size); + if (!iris_hfi_queue_cmd_write(core, &flush_pkt, flush_pkt.shdr.hdr.size)) + inst->flush_responses_pending++; + iris_inst_sub_state_change_drain_last(inst); =20 return; @@ -558,7 +561,6 @@ static void iris_hfi_gen1_handle_response(struct iris_c= ore *core, void *response const struct iris_hfi_gen1_response_pkt_info *pkt_info; struct device *dev =3D core->dev; struct hfi_session_pkt *pkt; - struct completion *done; struct iris_inst *inst; bool found =3D false; u32 i; @@ -619,9 +621,12 @@ static void iris_hfi_gen1_handle_response(struct iris_= core *core, void *response if (shdr->error_type !=3D HFI_ERR_NONE) iris_inst_change_state(inst, IRIS_INST_ERROR); =20 - done =3D pkt_info->pkt =3D=3D HFI_MSG_SESSION_FLUSH ? - &inst->flush_completion : &inst->completion; - complete(done); + if (pkt_info->pkt =3D=3D HFI_MSG_SESSION_FLUSH) { + if (!(--inst->flush_responses_pending)) + complete(&inst->flush_completion); + } else { + complete(&inst->completion); + } } mutex_unlock(&inst->lock); =20 diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index caa3c6507006..06a7f1174ad5 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -27,6 +27,7 @@ * @crop: structure of crop info * @completion: structure of signal completions * @flush_completion: structure of signal completions for flush cmd + * @flush_responses_pending: counter to track number of pending flush resp= onses * @fw_caps: array of supported instance firmware capabilities * @buffers: array of different iris buffers * @fw_min_count: minimnum count of buffers needed by fw @@ -57,6 +58,7 @@ struct iris_inst { struct iris_hfi_rect_desc crop; struct completion completion; struct completion flush_completion; + u32 flush_responses_pending; struct platform_inst_fw_cap fw_caps[INST_FW_CAP_MAX]; struct iris_buffers buffers[BUF_TYPE_MAX]; u32 fw_min_count; --=20 2.34.1 From nobody Mon Feb 9 02:38:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EDDD233706; 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This results in a mismatch when the buffers are prepared, causing failure due to outdated size. Introduce a check to prevent size validation during buffer preparation if a resolution reconfiguration is in progress, to handle this. Cc: stable@vger.kernel.org Fixes: 17f2a485ca67 ("media: iris: implement vb2 ops for buf_queue and firm= ware response") Reviewed-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_vb2.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/pl= atform/qcom/iris/iris_vb2.c index cdf11feb590b..b3bde10eb6d2 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -259,13 +259,14 @@ int iris_vb2_buf_prepare(struct vb2_buffer *vb) return -EINVAL; } =20 - if (vb->type =3D=3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE && - vb2_plane_size(vb, 0) < iris_get_buffer_size(inst, BUF_OUTPUT)) - return -EINVAL; - if (vb->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE && - vb2_plane_size(vb, 0) < iris_get_buffer_size(inst, BUF_INPUT)) - return -EINVAL; - + if (!(inst->sub_state & IRIS_INST_SUB_DRC)) { + if (vb->type =3D=3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE && + vb2_plane_size(vb, 0) < iris_get_buffer_size(inst, BUF_OUTPUT)) + return -EINVAL; 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Reviewed-by: Bryan O'Donoghue Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_buffer.c | 11 ++++++++--- drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h | 2 ++ drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c | 6 ++++++ 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 981fedb000ed..018334512bae 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -611,10 +611,13 @@ int iris_vb2_buffer_done(struct iris_inst *inst, stru= ct iris_buffer *buf) =20 vb2 =3D &vbuf->vb2_buf; =20 - if (buf->flags & V4L2_BUF_FLAG_ERROR) + if (buf->flags & V4L2_BUF_FLAG_ERROR) { state =3D VB2_BUF_STATE_ERROR; - else - state =3D VB2_BUF_STATE_DONE; + vb2_set_plane_payload(vb2, 0, 0); + vb2->timestamp =3D 0; + v4l2_m2m_buf_done(vbuf, state); + return 0; + } =20 vbuf->flags |=3D buf->flags; =20 @@ -634,6 +637,8 @@ int iris_vb2_buffer_done(struct iris_inst *inst, struct= iris_buffer *buf) v4l2_m2m_mark_stopped(m2m_ctx); } } + + state =3D VB2_BUF_STATE_DONE; vb2->timestamp =3D buf->timestamp; v4l2_m2m_buf_done(vbuf, state); =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index e178604855c1..adffcead58ea 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -116,6 +116,8 @@ #define HFI_FRAME_NOTCODED 0x7f002000 #define HFI_FRAME_YUV 0x7f004000 #define HFI_UNUSED_PICT 0x10000000 +#define HFI_BUFFERFLAG_DATACORRUPT 0x00000008 +#define HFI_BUFFERFLAG_DROP_FRAME 0x20000000 =20 struct hfi_pkt_hdr { u32 size; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 271e14469223..d36e29c779db 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -484,6 +484,12 @@ static void iris_hfi_gen1_session_ftb_done(struct iris= _inst *inst, void *packet) buf->attr |=3D BUF_ATTR_DEQUEUED; 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Also make sure: - These 0 length buffers are not returned as result of flush. - Its not a buffer with LAST flag enabled which will also have 0 filled length. Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 4488540d1d41..3bb326843a7b 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -378,6 +378,12 @@ static int iris_hfi_gen2_handle_output_buffer(struct i= ris_inst *inst, =20 buf->flags =3D iris_hfi_gen2_get_driver_buffer_flags(inst, hfi_buffer->fl= ags); =20 + if (!buf->data_size && inst->state =3D=3D IRIS_INST_STREAMING && + !(hfi_buffer->flags & HFI_BUF_FW_FLAG_LAST) && + !(inst->sub_state & IRIS_INST_SUB_DRC)) { + buf->flags |=3D V4L2_BUF_FLAG_ERROR; + } + return 0; } =20 --=20 2.34.1 From nobody Mon Feb 9 02:38:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CE8522B5A3; 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Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h | 1 + drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index 806f8bb7f505..666061a612c3 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -113,6 +113,7 @@ enum hfi_picture_type { HFI_PICTURE_I =3D 0x00000008, HFI_PICTURE_CRA =3D 0x00000010, HFI_PICTURE_BLA =3D 0x00000020, + HFI_PICTURE_NOSHOW =3D 0x00000040, }; =20 enum hfi_buffer_type { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 3bb326843a7b..2267e220c9ea 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -91,7 +91,9 @@ static int iris_hfi_gen2_get_driver_buffer_flags(struct i= ris_inst *inst, u32 hfi struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); 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Reviewed-by: Vikash Garodia Signed-off-by: Dikshita Agarwal Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_buffer.c | 1 + drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c | 7 ++++++- drivers/media/platform/qcom/iris/iris_instance.h | 2 ++ drivers/media/platform/qcom/iris/iris_vb2.c | 3 ++- drivers/media/platform/qcom/iris/iris_vdec.c | 2 ++ 5 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 018334512bae..7dbac74b1a8d 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -636,6 +636,7 @@ int iris_vb2_buffer_done(struct iris_inst *inst, struct= iris_buffer *buf) v4l2_event_queue_fh(&inst->fh, &ev); v4l2_m2m_mark_stopped(m2m_ctx); } + inst->last_buffer_dequeued =3D true; } =20 state =3D VB2_BUF_STATE_DONE; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index d36e29c779db..19ced1b3ee74 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -458,7 +458,12 @@ static void iris_hfi_gen1_session_ftb_done(struct iris= _inst *inst, void *packet) timestamp_us =3D timestamp_hi; timestamp_us =3D (timestamp_us << 32) | timestamp_lo; } else { - flags |=3D V4L2_BUF_FLAG_LAST; + if (pkt->stream_id =3D=3D 1 && !inst->last_buffer_dequeued) { + if (iris_drc_pending(inst)) { + flags |=3D V4L2_BUF_FLAG_LAST; + inst->last_buffer_dequeued =3D true; + } + } } buf->timestamp =3D timestamp_us; =20 diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index 06a7f1174ad5..5ec6368b2af7 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -43,6 +43,7 @@ * @sequence_out: a sequence counter for output queue * @tss: timestamp metadata * @metadata_idx: index for metadata buffer + * @last_buffer_dequeued: a flag to indicate that last buffer is sent by d= river */ =20 struct iris_inst { @@ -74,6 +75,7 @@ struct iris_inst { u32 sequence_out; struct iris_ts_metadata tss[VIDEO_MAX_FRAME]; u32 metadata_idx; + bool last_buffer_dequeued; }; =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/pl= atform/qcom/iris/iris_vb2.c index b3bde10eb6d2..8b17c7c39487 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -305,7 +305,7 @@ void iris_vb2_buf_queue(struct vb2_buffer *vb2) goto exit; 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At this point, the capture queue is not streaming, making the flush unnecessary. Additionally, remove the reinit_completion call for the flush completion signal, as it is not needed. This simplifies the code and avoids unnecessary reinitialization. Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 19ced1b3ee74..926acee1f48c 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -200,8 +200,7 @@ static void iris_hfi_gen1_event_seq_changed(struct iris= _inst *inst, =20 iris_hfi_gen1_read_changed_params(inst, pkt); =20 - if (inst->state !=3D IRIS_INST_ERROR) { - reinit_completion(&inst->flush_completion); + if (inst->state !=3D IRIS_INST_ERROR && !(inst->sub_state & IRIS_INST_SUB= _FIRST_IPSC)) { =20 flush_pkt.shdr.hdr.size =3D sizeof(struct hfi_session_flush_pkt); flush_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_FLUSH; --=20 2.34.1 From nobody Mon Feb 9 02:38:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF31B2288C0; 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Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_vdec.c | 36 ------------------------= ---- 1 file changed, 36 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index de4e3fe8ed5a..ce97c555192a 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -244,35 +244,6 @@ void iris_vdec_src_change(struct iris_inst *inst) v4l2_event_queue_fh(&inst->fh, &event); } =20 -static int iris_vdec_get_num_queued_buffers(struct iris_inst *inst, - enum iris_buffer_type type) -{ - struct v4l2_m2m_ctx *m2m_ctx =3D inst->m2m_ctx; - struct v4l2_m2m_buffer *buffer, *n; - struct iris_buffer *buf; - u32 count =3D 0; - - switch (type) { - case BUF_INPUT: - v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buffer, n) { - buf =3D to_iris_buffer(&buffer->vb); - if (!(buf->attr & BUF_ATTR_QUEUED)) - continue; - count++; - } - return count; - case BUF_OUTPUT: - v4l2_m2m_for_each_dst_buf_safe(m2m_ctx, buffer, n) { - buf =3D to_iris_buffer(&buffer->vb); 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#define DEFAULT_MAX_HOST_BUF_COUNT 64 #define DEFAULT_MAX_HOST_BURST_BUF_COUNT 256 #define DEFAULT_FPS 30 +#define NUM_MBS_8K ((8192 * 4352) / 256) =20 enum stage_type { STAGE_1 =3D 1, @@ -172,6 +173,7 @@ struct iris_platform_data { struct ubwc_config_data *ubwc_config; u32 num_vpp_pipe; u32 max_session_count; + /* max number of macroblocks per frame supported */ u32 max_core_mbpf; const u32 *input_config_params; unsigned int input_config_params_size; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 1e69ba15db0f..deb7037e8e86 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -248,7 +248,7 @@ struct iris_platform_data sm8550_data =3D { .ubwc_config =3D &ubwc_config_sm8550, .num_vpp_pipe =3D 4, .max_session_count =3D 16, - .max_core_mbpf =3D ((8192 * 4352) / 256) * 2, + .max_core_mbpf =3D NUM_MBS_8K * 2, .input_config_params =3D sm8550_vdec_input_config_params, .input_config_params_size =3D @@ -308,7 +308,7 @@ struct iris_platform_data sm8650_data =3D { .ubwc_config =3D &ubwc_config_sm8550, .num_vpp_pipe =3D 4, .max_session_count =3D 16, - .max_core_mbpf =3D ((8192 * 4352) / 256) * 2, + .max_core_mbpf =3D NUM_MBS_8K * 2, .input_config_params =3D sm8550_vdec_input_config_params, .input_config_params_size =3D diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 543fa2661539..8183e4e95fa4 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -127,7 +127,7 @@ struct iris_platform_data sm8250_data =3D { .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe =3D 4, .max_session_count =3D 16, - .max_core_mbpf =3D (8192 * 4352) / 256, + .max_core_mbpf =3D NUM_MBS_8K, .input_config_params =3D sm8250_vdec_input_config_param_default, .input_config_params_size =3D --=20 2.34.1 From nobody Mon Feb 9 02:38:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9051422D7B1; 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This change updates the format enumeration (VIDIOC_ENUM_FMT) and allows setting these formats via VIDIOC_S_FMT. Reviewed-by: Bryan O'Donoghue Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- .../platform/qcom/iris/iris_hfi_gen1_command.c | 15 ++++- .../platform/qcom/iris/iris_hfi_gen1_defines.h | 2 + .../platform/qcom/iris/iris_hfi_gen2_command.c | 14 ++++- .../platform/qcom/iris/iris_hfi_gen2_defines.h | 3 + drivers/media/platform/qcom/iris/iris_instance.h | 2 + drivers/media/platform/qcom/iris/iris_vdec.c | 69 ++++++++++++++++++= ++-- drivers/media/platform/qcom/iris/iris_vdec.h | 11 ++++ drivers/media/platform/qcom/iris/iris_vidc.c | 3 - 8 files changed, 108 insertions(+), 11 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index bd9d86220e61..dbb1b1dab097 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -88,16 +88,29 @@ static int iris_hfi_gen1_sys_pc_prep(struct iris_core *= core) static int iris_hfi_gen1_session_open(struct iris_inst *inst) { struct hfi_session_open_pkt packet; + u32 codec =3D 0; int ret; =20 if (inst->state !=3D IRIS_INST_DEINIT) return -EALREADY; =20 + switch (inst->codec) { + case V4L2_PIX_FMT_H264: + codec =3D HFI_VIDEO_CODEC_H264; + break; + case V4L2_PIX_FMT_HEVC: + codec =3D HFI_VIDEO_CODEC_HEVC; + break; + case V4L2_PIX_FMT_VP9: + codec =3D HFI_VIDEO_CODEC_VP9; + break; + } + packet.shdr.hdr.size =3D sizeof(struct hfi_session_open_pkt); packet.shdr.hdr.pkt_type =3D HFI_CMD_SYS_SESSION_INIT; packet.shdr.session_id =3D inst->session_id; packet.session_domain =3D HFI_SESSION_TYPE_DEC; - packet.session_codec =3D HFI_VIDEO_CODEC_H264; + packet.session_codec =3D codec; =20 reinit_completion(&inst->completion); =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index adffcead58ea..d4d119ca98b0 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -13,6 +13,8 @@ #define HFI_SESSION_TYPE_DEC 2 =20 #define HFI_VIDEO_CODEC_H264 0x00000002 +#define HFI_VIDEO_CODEC_HEVC 0x00002000 +#define HFI_VIDEO_CODEC_VP9 0x00004000 =20 #define HFI_ERR_NONE 0x0 =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 802fa62c26eb..f23be2340658 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -416,7 +416,19 @@ static int iris_hfi_gen2_session_set_config_params(str= uct iris_inst *inst, u32 p static int iris_hfi_gen2_session_set_codec(struct iris_inst *inst) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 codec =3D HFI_CODEC_DECODE_AVC; + u32 codec =3D 0; + + switch (inst->codec) { + case V4L2_PIX_FMT_H264: + codec =3D HFI_CODEC_DECODE_AVC; + break; + case V4L2_PIX_FMT_HEVC: + codec =3D HFI_CODEC_DECODE_HEVC; + break; + case V4L2_PIX_FMT_VP9: + codec =3D HFI_CODEC_DECODE_VP9; + break; + } =20 iris_hfi_gen2_packet_session_property(inst, HFI_PROP_CODEC, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index 666061a612c3..283d2f27e4c8 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -104,6 +104,9 @@ enum hfi_color_format { enum hfi_codec_type { HFI_CODEC_DECODE_AVC =3D 1, HFI_CODEC_ENCODE_AVC =3D 2, + HFI_CODEC_DECODE_HEVC =3D 3, + HFI_CODEC_ENCODE_HEVC =3D 4, + HFI_CODEC_DECODE_VP9 =3D 5, }; =20 enum hfi_picture_type { diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index 5ec6368b2af7..0e1f5799b72d 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -43,6 +43,7 @@ * @sequence_out: a sequence counter for output queue * @tss: timestamp metadata * @metadata_idx: index for metadata buffer + * @codec: codec type * @last_buffer_dequeued: a flag to indicate that last buffer is sent by d= river */ =20 @@ -75,6 +76,7 @@ struct iris_inst { u32 sequence_out; struct iris_ts_metadata tss[VIDEO_MAX_FRAME]; u32 metadata_idx; + u32 codec; bool last_buffer_dequeued; }; =20 diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index ce97c555192a..d670b51c5839 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -32,6 +32,7 @@ int iris_vdec_inst_init(struct iris_inst *inst) f->fmt.pix_mp.width =3D DEFAULT_WIDTH; f->fmt.pix_mp.height =3D DEFAULT_HEIGHT; f->fmt.pix_mp.pixelformat =3D V4L2_PIX_FMT_H264; + inst->codec =3D f->fmt.pix_mp.pixelformat; f->fmt.pix_mp.num_planes =3D 1; f->fmt.pix_mp.plane_fmt[0].bytesperline =3D 0; f->fmt.pix_mp.plane_fmt[0].sizeimage =3D iris_get_buffer_size(inst, BUF_I= NPUT); @@ -67,14 +68,67 @@ void iris_vdec_inst_deinit(struct iris_inst *inst) kfree(inst->fmt_src); } =20 +static const struct iris_fmt iris_vdec_formats[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static const struct iris_fmt * +find_format(struct iris_inst *inst, u32 pixfmt, u32 type) +{ + unsigned int size =3D ARRAY_SIZE(iris_vdec_formats); + const struct iris_fmt *fmt =3D iris_vdec_formats; + unsigned int i; + + for (i =3D 0; i < size; i++) { + if (fmt[i].pixfmt =3D=3D pixfmt) + break; + } + + if (i =3D=3D size || fmt[i].type !=3D type) + return NULL; + + return &fmt[i]; +} + +static const struct iris_fmt * +find_format_by_index(struct iris_inst *inst, u32 index, u32 type) +{ + const struct iris_fmt *fmt =3D iris_vdec_formats; + unsigned int size =3D ARRAY_SIZE(iris_vdec_formats); + + if (index >=3D size || fmt[index].type !=3D type) + return NULL; + + return &fmt[index]; +} + int iris_vdec_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f) { + const struct iris_fmt *fmt; + switch (f->type) { case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: - f->pixelformat =3D V4L2_PIX_FMT_H264; + fmt =3D find_format_by_index(inst, f->index, f->type); + if (!fmt) + return -EINVAL; + + f->pixelformat =3D fmt->pixfmt; f->flags =3D V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION; break; case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + if (f->index) + return -EINVAL; f->pixelformat =3D V4L2_PIX_FMT_NV12; break; default: @@ -88,13 +142,15 @@ int iris_vdec_try_fmt(struct iris_inst *inst, struct v= 4l2_format *f) { struct v4l2_pix_format_mplane *pixmp =3D &f->fmt.pix_mp; struct v4l2_m2m_ctx *m2m_ctx =3D inst->m2m_ctx; + const struct iris_fmt *fmt; struct v4l2_format *f_inst; struct vb2_queue *src_q; =20 memset(pixmp->reserved, 0, sizeof(pixmp->reserved)); + fmt =3D find_format(inst, pixmp->pixelformat, f->type); switch (f->type) { case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: - if (f->fmt.pix_mp.pixelformat !=3D V4L2_PIX_FMT_H264) { + if (!fmt) { f_inst =3D inst->fmt_src; f->fmt.pix_mp.width =3D f_inst->fmt.pix_mp.width; f->fmt.pix_mp.height =3D f_inst->fmt.pix_mp.height; @@ -102,7 +158,7 @@ int iris_vdec_try_fmt(struct iris_inst *inst, struct v4= l2_format *f) } break; case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: - if (f->fmt.pix_mp.pixelformat !=3D V4L2_PIX_FMT_NV12) { + if (!fmt) { f_inst =3D inst->fmt_dst; f->fmt.pix_mp.pixelformat =3D f_inst->fmt.pix_mp.pixelformat; f->fmt.pix_mp.width =3D f_inst->fmt.pix_mp.width; @@ -145,13 +201,14 @@ int iris_vdec_s_fmt(struct iris_inst *inst, struct v4= l2_format *f) =20 switch (f->type) { case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: - if (f->fmt.pix_mp.pixelformat !=3D V4L2_PIX_FMT_H264) + if (!(find_format(inst, f->fmt.pix_mp.pixelformat, f->type))) return -EINVAL; =20 fmt =3D inst->fmt_src; fmt->type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; - - codec_align =3D DEFAULT_CODEC_ALIGNMENT; + fmt->fmt.pix_mp.pixelformat =3D f->fmt.pix_mp.pixelformat; + inst->codec =3D fmt->fmt.pix_mp.pixelformat; + codec_align =3D inst->codec =3D=3D V4L2_PIX_FMT_HEVC ? 32 : 16; fmt->fmt.pix_mp.width =3D ALIGN(f->fmt.pix_mp.width, codec_align); fmt->fmt.pix_mp.height =3D ALIGN(f->fmt.pix_mp.height, codec_align); fmt->fmt.pix_mp.num_planes =3D 1; diff --git a/drivers/media/platform/qcom/iris/iris_vdec.h b/drivers/media/p= latform/qcom/iris/iris_vdec.h index b24932dc511a..cd7aab66dc7c 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.h +++ b/drivers/media/platform/qcom/iris/iris_vdec.h @@ -8,6 +8,17 @@ =20 struct iris_inst; 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Reviewed-by: Bryan O'Donoghue Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_ctrls.c | 28 ++++- .../platform/qcom/iris/iris_hfi_gen2_command.c | 28 ++++- .../platform/qcom/iris/iris_hfi_gen2_defines.h | 1 + .../platform/qcom/iris/iris_hfi_gen2_response.c | 34 +++++- .../platform/qcom/iris/iris_platform_common.h | 8 +- .../media/platform/qcom/iris/iris_platform_gen2.c | 80 ++++++++++++- .../platform/qcom/iris/iris_platform_qcs8300.h | 126 +++++++++++++++++= ---- 7 files changed, 266 insertions(+), 39 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 13f5cf0d0e8a..9136b723c0f2 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -18,9 +18,19 @@ static enum platform_inst_fw_cap_type iris_get_cap_id(u3= 2 id) { switch (id) { case V4L2_CID_MPEG_VIDEO_H264_PROFILE: - return PROFILE; + return PROFILE_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: + return PROFILE_HEVC; + case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: + return PROFILE_VP9; case V4L2_CID_MPEG_VIDEO_H264_LEVEL: - return LEVEL; + return LEVEL_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: + return LEVEL_HEVC; + case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: + return LEVEL_VP9; + case V4L2_CID_MPEG_VIDEO_HEVC_TIER: + return TIER; default: return INST_FW_CAP_MAX; } @@ -32,10 +42,20 @@ static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_t= ype cap_id) return 0; =20 switch (cap_id) { - case PROFILE: + case PROFILE_H264: return V4L2_CID_MPEG_VIDEO_H264_PROFILE; - case LEVEL: + case PROFILE_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_PROFILE; + case PROFILE_VP9: + return V4L2_CID_MPEG_VIDEO_VP9_PROFILE; + case LEVEL_H264: return V4L2_CID_MPEG_VIDEO_H264_LEVEL; + case LEVEL_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_LEVEL; + case LEVEL_VP9: + return V4L2_CID_MPEG_VIDEO_VP9_LEVEL; + case TIER: + return V4L2_CID_MPEG_VIDEO_HEVC_TIER; default: return 0; } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index f23be2340658..8c91d336ff7e 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -295,7 +295,19 @@ static int iris_hfi_gen2_set_profile(struct iris_inst = *inst) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); - u32 profile =3D inst->fw_caps[PROFILE].value; + u32 profile =3D 0; + + switch (inst->codec) { + case V4L2_PIX_FMT_HEVC: + profile =3D inst->fw_caps[PROFILE_HEVC].value; + break; + case V4L2_PIX_FMT_VP9: + profile =3D inst->fw_caps[PROFILE_VP9].value; + break; + case V4L2_PIX_FMT_H264: + profile =3D inst->fw_caps[PROFILE_H264].value; + break; + } =20 inst_hfi_gen2->src_subcr_params.profile =3D profile; =20 @@ -312,7 +324,19 @@ static int iris_hfi_gen2_set_level(struct iris_inst *i= nst) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); - u32 level =3D inst->fw_caps[LEVEL].value; + u32 level =3D 0; + + switch (inst->codec) { + case V4L2_PIX_FMT_HEVC: + level =3D inst->fw_caps[LEVEL_HEVC].value; + break; + case V4L2_PIX_FMT_VP9: + level =3D inst->fw_caps[LEVEL_VP9].value; + break; + case V4L2_PIX_FMT_H264: + level =3D inst->fw_caps[LEVEL_H264].value; + break; + } =20 inst_hfi_gen2->src_subcr_params.level =3D level; =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index 283d2f27e4c8..5f13dc11bea5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -46,6 +46,7 @@ #define HFI_PROP_CROP_OFFSETS 0x03000105 #define HFI_PROP_PROFILE 0x03000107 #define HFI_PROP_LEVEL 0x03000108 +#define HFI_PROP_TIER 0x03000109 #define HFI_PROP_STAGE 0x0300010a #define HFI_PROP_PIPE 0x0300010b #define HFI_PROP_LUMA_CHROMA_BIT_DEPTH 0x0300010f diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 2267e220c9ea..1b8787c0f6a7 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -572,8 +572,21 @@ static void iris_hfi_gen2_read_input_subcr_params(stru= ct iris_inst *inst) inst->crop.width =3D pixmp_ip->width - ((subsc_params.crop_offsets[1] >> 16) & 0xFFFF) - inst->crop.left; =20 - inst->fw_caps[PROFILE].value =3D subsc_params.profile; - inst->fw_caps[LEVEL].value =3D subsc_params.level; + switch (inst->codec) { + case V4L2_PIX_FMT_HEVC: + inst->fw_caps[PROFILE_HEVC].value =3D subsc_params.profile; + inst->fw_caps[LEVEL_HEVC].value =3D subsc_params.level; + break; + case V4L2_PIX_FMT_VP9: + inst->fw_caps[PROFILE_VP9].value =3D subsc_params.profile; + inst->fw_caps[LEVEL_VP9].value =3D subsc_params.level; + break; + case V4L2_PIX_FMT_H264: + inst->fw_caps[PROFILE_H264].value =3D subsc_params.profile; + inst->fw_caps[LEVEL_H264].value =3D subsc_params.level; + break; + } + inst->fw_caps[POC].value =3D subsc_params.pic_order_cnt; =20 if (subsc_params.bit_depth !=3D BIT_DEPTH_8 || @@ -797,8 +810,21 @@ static void iris_hfi_gen2_init_src_change_param(struct= iris_inst *inst) full_range, video_format, video_signal_type_present_flag); =20 - subsc_params->profile =3D inst->fw_caps[PROFILE].value; - subsc_params->level =3D inst->fw_caps[LEVEL].value; + switch (inst->codec) { + case V4L2_PIX_FMT_HEVC: + subsc_params->profile =3D inst->fw_caps[PROFILE_HEVC].value; + subsc_params->level =3D inst->fw_caps[LEVEL_HEVC].value; + break; + case V4L2_PIX_FMT_VP9: + subsc_params->profile =3D inst->fw_caps[PROFILE_VP9].value; + subsc_params->level =3D inst->fw_caps[LEVEL_VP9].value; + break; + case V4L2_PIX_FMT_H264: + subsc_params->profile =3D inst->fw_caps[PROFILE_H264].value; + subsc_params->level =3D inst->fw_caps[LEVEL_H264].value; + break; + } + subsc_params->pic_order_cnt =3D inst->fw_caps[POC].value; subsc_params->bit_depth =3D inst->fw_caps[BIT_DEPTH].value; if (inst->fw_caps[CODED_FRAMES].value =3D=3D diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 3e0ae87526a0..71d23214f224 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -81,8 +81,12 @@ struct platform_inst_caps { }; =20 enum platform_inst_fw_cap_type { - PROFILE =3D 1, - LEVEL, + PROFILE_H264 =3D 1, + PROFILE_HEVC, + PROFILE_VP9, + LEVEL_H264, + LEVEL_HEVC, + LEVEL_VP9, INPUT_BUF_HOST_MAX_COUNT, STAGE, PIPE, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index deb7037e8e86..c2cded2876b7 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -17,7 +17,7 @@ =20 static struct platform_inst_fw_cap inst_fw_cap_sm8550[] =3D { { - .cap_id =3D PROFILE, + .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | @@ -31,7 +31,29 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550[] = =3D { .set =3D iris_set_u32_enum, }, { - .cap_id =3D LEVEL, + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D PROFILE_VP9, + .min =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) | + BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2), + .value =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_H264, .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_2, .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | @@ -59,6 +81,60 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550[] = =3D { .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, .set =3D iris_set_u32_enum, }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_VP9, + .min =3D V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_6_0, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0), + .value =3D V4L2_MPEG_VIDEO_VP9_LEVEL_6_0, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D TIER, + .min =3D V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH), + .value =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + .hfi_id =3D HFI_PROP_TIER, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, { .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, .min =3D DEFAULT_MAX_HOST_BUF_COUNT, diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/dri= vers/media/platform/qcom/iris/iris_platform_qcs8300.h index f82355d72fcf..a8d66ed388a3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h @@ -5,48 +5,124 @@ =20 static struct platform_inst_fw_cap inst_fw_cap_qcs8300[] =3D { { - .cap_id =3D PROFILE, + .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH), .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, .hfi_id =3D HFI_PROP_PROFILE, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, .set =3D iris_set_u32_enum, }, { - .cap_id =3D LEVEL, + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D PROFILE_VP9, + .min =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) | + BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2), + .value =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_H264, .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_2, .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2), + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2), .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_1, .hfi_id =3D HFI_PROP_LEVEL, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, .set =3D iris_set_u32_enum, }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_VP9, + .min =3D V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_6_0, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0), + .value =3D V4L2_MPEG_VIDEO_VP9_LEVEL_6_0, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D TIER, + .min =3D V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH), + .value =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + .hfi_id =3D HFI_PROP_TIER, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, { .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, .min =3D DEFAULT_MAX_HOST_BUF_COUNT, --=20 2.34.1 From nobody Mon Feb 9 02:38:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 274CC244681; Thu, 1 May 2025 19:16:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none 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iris: Set mandatory properties for HEVC and VP9 decoders. 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Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_hfi_common.h | 1 + .../platform/qcom/iris/iris_hfi_gen1_command.c | 4 +- .../platform/qcom/iris/iris_hfi_gen2_command.c | 97 +++++++++++++++--- .../platform/qcom/iris/iris_hfi_gen2_response.c | 7 ++ .../platform/qcom/iris/iris_platform_common.h | 16 ++- .../media/platform/qcom/iris/iris_platform_gen2.c | 114 +++++++++++++++++= ---- .../platform/qcom/iris/iris_platform_sm8250.c | 4 +- 7 files changed, 203 insertions(+), 40 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index b2c541367fc6..9e6aadb83783 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -140,6 +140,7 @@ struct hfi_subscription_params { u32 color_info; u32 profile; u32 level; + u32 tier; }; =20 u32 iris_hfi_get_v4l2_color_primaries(u32 hfi_primaries); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index dbb1b1dab097..2e3f5a6b2ff1 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -776,8 +776,8 @@ static int iris_hfi_gen1_session_set_config_params(stru= ct iris_inst *inst, u32 p iris_hfi_gen1_set_bufsize}, }; =20 - config_params =3D core->iris_platform_data->input_config_params; - config_params_size =3D core->iris_platform_data->input_config_params_size; + config_params =3D core->iris_platform_data->input_config_params_default; + config_params_size =3D core->iris_platform_data->input_config_params_defa= ult_size; =20 if (V4L2_TYPE_IS_OUTPUT(plane)) { for (i =3D 0; i < config_params_size; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 8c91d336ff7e..7ca5ae13d62b 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -391,11 +391,28 @@ static int iris_hfi_gen2_set_linear_stride_scanline(s= truct iris_inst *inst) sizeof(u64)); } =20 +static int iris_hfi_gen2_set_tier(struct iris_inst *inst) +{ + struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); + u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + u32 tier =3D inst->fw_caps[TIER].value; + + inst_hfi_gen2->src_subcr_params.tier =3D tier; + + return iris_hfi_gen2_session_set_property(inst, + HFI_PROP_TIER, + HFI_HOST_FLAGS_NONE, + port, + HFI_PAYLOAD_U32_ENUM, + &tier, + sizeof(u32)); +} + static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst,= u32 plane) { struct iris_core *core =3D inst->core; - u32 config_params_size, i, j; - const u32 *config_params; + u32 config_params_size =3D 0, i, j; + const u32 *config_params =3D NULL; int ret; =20 static const struct iris_hfi_prop_type_handle prop_type_handle_arr[] =3D { @@ -410,11 +427,27 @@ static int iris_hfi_gen2_session_set_config_params(st= ruct iris_inst *inst, u32 p {HFI_PROP_LEVEL, iris_hfi_gen2_set_level = }, {HFI_PROP_COLOR_FORMAT, iris_hfi_gen2_set_colorformat = }, {HFI_PROP_LINEAR_STRIDE_SCANLINE, iris_hfi_gen2_set_linear_stride_sc= anline }, + {HFI_PROP_TIER, iris_hfi_gen2_set_tier = }, }; =20 if (V4L2_TYPE_IS_OUTPUT(plane)) { - config_params =3D core->iris_platform_data->input_config_params; - config_params_size =3D core->iris_platform_data->input_config_params_siz= e; + switch (inst->codec) { + case V4L2_PIX_FMT_H264: + config_params =3D core->iris_platform_data->input_config_params_default; + config_params_size =3D + core->iris_platform_data->input_config_params_default_size; + break; + case V4L2_PIX_FMT_HEVC: + config_params =3D core->iris_platform_data->input_config_params_hevc; + config_params_size =3D + core->iris_platform_data->input_config_params_hevc_size; + break; + case V4L2_PIX_FMT_VP9: + config_params =3D core->iris_platform_data->input_config_params_vp9; + config_params_size =3D + core->iris_platform_data->input_config_params_vp9_size; + break; + } } else { config_params =3D core->iris_platform_data->output_config_params; config_params_size =3D core->iris_platform_data->output_config_params_si= ze; @@ -584,8 +617,8 @@ static int iris_hfi_gen2_subscribe_change_param(struct = iris_inst *inst, u32 plan struct hfi_subscription_params subsc_params; u32 prop_type, payload_size, payload_type; struct iris_core *core =3D inst->core; - const u32 *change_param; - u32 change_param_size; + const u32 *change_param =3D NULL; + u32 change_param_size =3D 0; u32 payload[32] =3D {0}; u32 hfi_port =3D 0, i; int ret; @@ -596,8 +629,23 @@ static int iris_hfi_gen2_subscribe_change_param(struct= iris_inst *inst, u32 plan return 0; } =20 - change_param =3D core->iris_platform_data->input_config_params; - change_param_size =3D core->iris_platform_data->input_config_params_size; + switch (inst->codec) { + case V4L2_PIX_FMT_H264: + change_param =3D core->iris_platform_data->input_config_params_default; + change_param_size =3D + core->iris_platform_data->input_config_params_default_size; + break; + case V4L2_PIX_FMT_HEVC: + change_param =3D core->iris_platform_data->input_config_params_hevc; + change_param_size =3D + core->iris_platform_data->input_config_params_hevc_size; + break; + case V4L2_PIX_FMT_VP9: + change_param =3D core->iris_platform_data->input_config_params_vp9; + change_param_size =3D + core->iris_platform_data->input_config_params_vp9_size; + break; + } =20 payload[0] =3D HFI_MODE_PORT_SETTINGS_CHANGE; =20 @@ -644,6 +692,11 @@ static int iris_hfi_gen2_subscribe_change_param(struct= iris_inst *inst, u32 plan payload_size =3D sizeof(u32); payload_type =3D HFI_PAYLOAD_U32; break; + case HFI_PROP_LUMA_CHROMA_BIT_DEPTH: + payload[0] =3D subsc_params.bit_depth; + payload_size =3D sizeof(u32); + payload_type =3D HFI_PAYLOAD_U32; + break; case HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT: payload[0] =3D subsc_params.fw_min_count; payload_size =3D sizeof(u32); @@ -669,6 +722,11 @@ static int iris_hfi_gen2_subscribe_change_param(struct= iris_inst *inst, u32 plan payload_size =3D sizeof(u32); payload_type =3D HFI_PAYLOAD_U32; break; + case HFI_PROP_TIER: + payload[0] =3D subsc_params.tier; + payload_size =3D sizeof(u32); + payload_type =3D HFI_PAYLOAD_U32; + break; default: prop_type =3D 0; ret =3D -EINVAL; @@ -695,8 +753,8 @@ static int iris_hfi_gen2_subscribe_change_param(struct = iris_inst *inst, u32 plan static int iris_hfi_gen2_subscribe_property(struct iris_inst *inst, u32 pl= ane) { struct iris_core *core =3D inst->core; - u32 subscribe_prop_size, i; - const u32 *subcribe_prop; + u32 subscribe_prop_size =3D 0, i; + const u32 *subcribe_prop =3D NULL; u32 payload[32] =3D {0}; =20 payload[0] =3D HFI_MODE_PROPERTY; @@ -705,8 +763,23 @@ static int iris_hfi_gen2_subscribe_property(struct iri= s_inst *inst, u32 plane) subscribe_prop_size =3D core->iris_platform_data->dec_input_prop_size; subcribe_prop =3D core->iris_platform_data->dec_input_prop; } else { - subscribe_prop_size =3D core->iris_platform_data->dec_output_prop_size; - subcribe_prop =3D core->iris_platform_data->dec_output_prop; + switch (inst->codec) { + case V4L2_PIX_FMT_H264: + subcribe_prop =3D core->iris_platform_data->dec_output_prop_avc; + subscribe_prop_size =3D + core->iris_platform_data->dec_output_prop_avc_size; + break; + case V4L2_PIX_FMT_HEVC: + subcribe_prop =3D core->iris_platform_data->dec_output_prop_hevc; + subscribe_prop_size =3D + core->iris_platform_data->dec_output_prop_hevc_size; + break; + case V4L2_PIX_FMT_VP9: + subcribe_prop =3D core->iris_platform_data->dec_output_prop_vp9; + subscribe_prop_size =3D + core->iris_platform_data->dec_output_prop_vp9_size; + break; + } } =20 for (i =3D 0; i < subscribe_prop_size; i++) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 1b8787c0f6a7..221f84d98a48 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -588,6 +588,7 @@ static void iris_hfi_gen2_read_input_subcr_params(struc= t iris_inst *inst) } =20 inst->fw_caps[POC].value =3D subsc_params.pic_order_cnt; + inst->fw_caps[TIER].value =3D subsc_params.tier; =20 if (subsc_params.bit_depth !=3D BIT_DEPTH_8 || !(subsc_params.coded_frames & HFI_BITMASK_FRAME_MBS_ONLY_FLAG)) { @@ -669,6 +670,9 @@ static int iris_hfi_gen2_handle_session_property(struct= iris_inst *inst, inst_hfi_gen2->src_subcr_params.crop_offsets[0] =3D pkt->payload[0]; inst_hfi_gen2->src_subcr_params.crop_offsets[1] =3D pkt->payload[1]; break; + case HFI_PROP_LUMA_CHROMA_BIT_DEPTH: + inst_hfi_gen2->src_subcr_params.bit_depth =3D pkt->payload[0]; + break; case HFI_PROP_CODED_FRAMES: inst_hfi_gen2->src_subcr_params.coded_frames =3D pkt->payload[0]; break; @@ -687,6 +691,9 @@ static int iris_hfi_gen2_handle_session_property(struct= iris_inst *inst, case HFI_PROP_LEVEL: inst_hfi_gen2->src_subcr_params.level =3D pkt->payload[0]; break; + case HFI_PROP_TIER: + inst_hfi_gen2->src_subcr_params.tier =3D pkt->payload[0]; + break; case HFI_PROP_PICTURE_TYPE: inst_hfi_gen2->hfi_frame_info.picture_type =3D pkt->payload[0]; break; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 71d23214f224..adafdce8a856 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -179,14 +179,22 @@ struct iris_platform_data { u32 max_session_count; /* max number of macroblocks per frame supported */ u32 max_core_mbpf; - const u32 *input_config_params; - unsigned int input_config_params_size; + const u32 *input_config_params_default; + unsigned int input_config_params_default_size; + const u32 *input_config_params_hevc; + unsigned int input_config_params_hevc_size; + const u32 *input_config_params_vp9; + unsigned int input_config_params_vp9_size; const u32 *output_config_params; unsigned int output_config_params_size; const u32 *dec_input_prop; unsigned int dec_input_prop_size; - const u32 *dec_output_prop; - unsigned int dec_output_prop_size; + const u32 *dec_output_prop_avc; + unsigned int dec_output_prop_avc_size; + const u32 *dec_output_prop_hevc; + unsigned int dec_output_prop_hevc_size; + const u32 *dec_output_prop_vp9; + unsigned int dec_output_prop_vp9_size; const u32 *dec_ip_int_buf_tbl; unsigned int dec_ip_int_buf_tbl_size; const u32 *dec_op_int_buf_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index c2cded2876b7..d3026b2bcb70 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -257,9 +257,10 @@ static struct tz_cp_config tz_cp_config_sm8550 =3D { .cp_nonpixel_size =3D 0x24800000, }; =20 -static const u32 sm8550_vdec_input_config_params[] =3D { +static const u32 sm8550_vdec_input_config_params_default[] =3D { HFI_PROP_BITSTREAM_RESOLUTION, HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, HFI_PROP_CODED_FRAMES, HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, HFI_PROP_PIC_ORDER_CNT_TYPE, @@ -268,6 +269,26 @@ static const u32 sm8550_vdec_input_config_params[] =3D= { HFI_PROP_SIGNAL_COLOR_INFO, }; =20 +static const u32 sm8550_vdec_input_config_param_hevc[] =3D { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, + HFI_PROP_TIER, + HFI_PROP_SIGNAL_COLOR_INFO, +}; + +static const u32 sm8550_vdec_input_config_param_vp9[] =3D { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, +}; + static const u32 sm8550_vdec_output_config_params[] =3D { HFI_PROP_COLOR_FORMAT, HFI_PROP_LINEAR_STRIDE_SCANLINE, @@ -277,11 +298,19 @@ static const u32 sm8550_vdec_subscribe_input_properti= es[] =3D { HFI_PROP_NO_OUTPUT, }; =20 -static const u32 sm8550_vdec_subscribe_output_properties[] =3D { +static const u32 sm8550_vdec_subscribe_output_properties_avc[] =3D { HFI_PROP_PICTURE_TYPE, HFI_PROP_CABAC_SESSION, }; =20 +static const u32 sm8550_vdec_subscribe_output_properties_hevc[] =3D { + HFI_PROP_PICTURE_TYPE, +}; + +static const u32 sm8550_vdec_subscribe_output_properties_vp9[] =3D { + HFI_PROP_PICTURE_TYPE, +}; + static const u32 sm8550_dec_ip_int_buf_tbl[] =3D { BUF_BIN, BUF_COMV, @@ -325,18 +354,33 @@ struct iris_platform_data sm8550_data =3D { .num_vpp_pipe =3D 4, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, - .input_config_params =3D - sm8550_vdec_input_config_params, - .input_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params), + .input_config_params_default =3D + sm8550_vdec_input_config_params_default, + .input_config_params_default_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .input_config_params_hevc =3D + sm8550_vdec_input_config_param_hevc, + .input_config_params_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .input_config_params_vp9 =3D + sm8550_vdec_input_config_param_vp9, + .input_config_params_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), .output_config_params =3D sm8550_vdec_output_config_params, .output_config_params_size =3D ARRAY_SIZE(sm8550_vdec_output_config_params), .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop =3D sm8550_vdec_subscribe_output_properties, - .dec_output_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_propert= ies), + .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), =20 .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), @@ -385,18 +429,33 @@ struct iris_platform_data sm8650_data =3D { .num_vpp_pipe =3D 4, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, - .input_config_params =3D - sm8550_vdec_input_config_params, - .input_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params), + .input_config_params_default =3D + sm8550_vdec_input_config_params_default, + .input_config_params_default_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .input_config_params_hevc =3D + sm8550_vdec_input_config_param_hevc, + .input_config_params_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .input_config_params_vp9 =3D + sm8550_vdec_input_config_param_vp9, + .input_config_params_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), .output_config_params =3D sm8550_vdec_output_config_params, .output_config_params_size =3D ARRAY_SIZE(sm8550_vdec_output_config_params), .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop =3D sm8550_vdec_subscribe_output_properties, - .dec_output_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_propert= ies), + .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), =20 .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), @@ -441,18 +500,33 @@ struct iris_platform_data qcs8300_data =3D { .num_vpp_pipe =3D 2, .max_session_count =3D 16, .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, - .input_config_params =3D - sm8550_vdec_input_config_params, - .input_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params), + .input_config_params_default =3D + sm8550_vdec_input_config_params_default, + .input_config_params_default_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .input_config_params_hevc =3D + sm8550_vdec_input_config_param_hevc, + .input_config_params_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .input_config_params_vp9 =3D + sm8550_vdec_input_config_param_vp9, + .input_config_params_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), .output_config_params =3D sm8550_vdec_output_config_params, .output_config_params_size =3D ARRAY_SIZE(sm8550_vdec_output_config_params), .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop =3D sm8550_vdec_subscribe_output_properties, - .dec_output_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_propert= ies), + .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), =20 .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 8183e4e95fa4..8d0816a67ae0 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -128,9 +128,9 @@ struct iris_platform_data sm8250_data =3D { .num_vpp_pipe =3D 4, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K, - .input_config_params =3D + .input_config_params_default =3D sm8250_vdec_input_config_param_default, - .input_config_params_size =3D + .input_config_params_default_size =3D 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Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_buffer.c | 3 + drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 397 +++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 46 ++- 3 files changed, 432 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 7dbac74b1a8d..6425e4919e3b 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -205,6 +205,9 @@ static u32 iris_bitstream_buffer_size(struct iris_inst = *inst) if (num_mbs > NUM_MBS_4K) { div_factor =3D 4; base_res_mbs =3D caps->max_mbpf; + } else { + if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + div_factor =3D 1; } =20 /* diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index dce25e410d80..13ee93356bcb 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -31,6 +31,42 @@ static u32 hfi_buffer_bin_h264d(u32 frame_width, u32 fra= me_height, u32 num_vpp_p return size_h264d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); } =20 +static u32 size_h265d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32= num_vpp_pipes) +{ + u32 product =3D frame_width * frame_height; + u32 size_yuv, size_bin_hdr, size_bin_res; + + size_yuv =3D (product <=3D BIN_BUFFER_THRESHOLD) ? + ((BIN_BUFFER_THRESHOLD * 3) >> 1) : ((product * 3) >> 1); + size_bin_hdr =3D size_yuv * H265_CABAC_HDR_RATIO_HD_TOT; + size_bin_res =3D size_yuv * H265_CABAC_RES_RATIO_HD_TOT; + size_bin_hdr =3D ALIGN(size_bin_hdr / num_vpp_pipes, DMA_ALIGNMENT) * num= _vpp_pipes; + size_bin_res =3D ALIGN(size_bin_res / num_vpp_pipes, DMA_ALIGNMENT) * num= _vpp_pipes; + + return size_bin_hdr + size_bin_res; +} + +static u32 hfi_buffer_bin_vp9d(u32 frame_width, u32 frame_height, u32 num_= vpp_pipes) +{ + u32 _size_yuv =3D ALIGN(frame_width, 16) * ALIGN(frame_height, 16) * 3 / = 2; + u32 _size =3D ALIGN(((max_t(u32, _size_yuv, ((BIN_BUFFER_THRESHOLD * 3) >= > 1)) * + VPX_DECODER_FRAME_BIN_HDR_BUDGET / VPX_DECODER_FRAME_BIN_DENOMINATOR * + VPX_DECODER_FRAME_CONCURENCY_LVL) / num_vpp_pipes), DMA_ALIGNMENT) + + ALIGN(((max_t(u32, _size_yuv, ((BIN_BUFFER_THRESHOLD * 3) >> 1)) * + VPX_DECODER_FRAME_BIN_RES_BUDGET / VPX_DECODER_FRAME_BIN_DENOMINATOR * + VPX_DECODER_FRAME_CONCURENCY_LVL) / num_vpp_pipes), DMA_ALIGNMENT); + + return _size * num_vpp_pipes; +} + +static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 frame_height, u32 num= _vpp_pipes) +{ + u32 n_aligned_w =3D ALIGN(frame_width, 16); + u32 n_aligned_h =3D ALIGN(frame_height, 16); + + return size_h265d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); +} + static u32 hfi_buffer_comv_h264d(u32 frame_width, u32 frame_height, u32 _c= omv_bufcount) { u32 frame_height_in_mbs =3D DIV_ROUND_UP(frame_height, 16); @@ -55,6 +91,17 @@ static u32 hfi_buffer_comv_h264d(u32 frame_width, u32 fr= ame_height, u32 _comv_bu return (size_colloc * (_comv_bufcount)) + 512; } =20 +static u32 hfi_buffer_comv_h265d(u32 frame_width, u32 frame_height, u32 _c= omv_bufcount) +{ + u32 frame_height_in_mbs =3D (frame_height + 15) >> 4; + u32 frame_width_in_mbs =3D (frame_width + 15) >> 4; + u32 _size; + + _size =3D ALIGN(((frame_width_in_mbs * frame_height_in_mbs) << 8), 512); + + return (_size * (_comv_bufcount)) + 512; +} + static u32 size_h264d_bse_cmd_buf(u32 frame_height) { u32 height =3D ALIGN(frame_height, 32); @@ -63,6 +110,44 @@ static u32 size_h264d_bse_cmd_buf(u32 frame_height) SIZE_H264D_BSE_CMD_PER_BUF; } =20 +static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32 frame_height) +{ + u32 _size =3D ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZ= E_PELS) * + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) * + NUM_HW_PIC_BUF, DMA_ALIGNMENT); + _size =3D min_t(u32, _size, H265D_MAX_SLICE + 1); + _size =3D 2 * _size * SIZE_H265D_BSE_CMD_PER_BUF; + + return _size; +} + +static u32 hfi_buffer_persist_h265d(u32 rpu_enabled) +{ + return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + + H265_NUM_FRM_INFO * H265_DISPLAY_BUF_SIZE + + H265_NUM_TILE * sizeof(u32) + + NUM_HW_PIC_BUF * SIZE_SEI_USERDATA + + rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), + DMA_ALIGNMENT); +} + +static inline +u32 hfi_iris3_vp9d_comv_size(void) +{ + return (((8192 + 63) >> 6) * ((4320 + 63) >> 6) * 8 * 8 * 2 * 8); +} + +static u32 hfi_buffer_persist_vp9d(void) +{ + return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALI= GNMENT) + + ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) + + ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT) + + ALIGN(VP9_UDC_HEADER_BUF_SIZE, DMA_ALIGNMENT) + + ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, DMA_ALIGNMENT) + + ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE, DMA_ALIGNMENT) + + HDR10_HIST_EXTRADATA_SIZE; +} + static u32 size_h264d_vpp_cmd_buf(u32 frame_height) { u32 size, height =3D ALIGN(frame_height, 32); @@ -83,17 +168,45 @@ static u32 hfi_buffer_persist_h264d(void) =20 static u32 hfi_buffer_non_comv_h264d(u32 frame_width, u32 frame_height, u3= 2 num_vpp_pipes) { - u32 size_bse, size_vpp, size; - - size_bse =3D size_h264d_bse_cmd_buf(frame_height); - size_vpp =3D size_h264d_vpp_cmd_buf(frame_height); - size =3D ALIGN(size_bse, DMA_ALIGNMENT) + + u32 size_bse =3D size_h264d_bse_cmd_buf(frame_height); + u32 size_vpp =3D size_h264d_vpp_cmd_buf(frame_height); + u32 size =3D ALIGN(size_bse, DMA_ALIGNMENT) + ALIGN(size_vpp, DMA_ALIGNMENT) + ALIGN(SIZE_HW_PIC(SIZE_H264D_HW_PIC_T), DMA_ALIGNMENT); =20 return ALIGN(size, DMA_ALIGNMENT); } =20 +static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32 frame_height) +{ + u32 _size =3D ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZ= E_PELS) * + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) * + NUM_HW_PIC_BUF, DMA_ALIGNMENT); + _size =3D min_t(u32, _size, H265D_MAX_SLICE + 1); + _size =3D ALIGN(_size, 4); + _size =3D 2 * _size * SIZE_H265D_VPP_CMD_PER_BUF; + if (_size > VPP_CMD_MAX_SIZE) + _size =3D VPP_CMD_MAX_SIZE; + + return _size; +} + +static u32 hfi_buffer_non_comv_h265d(u32 frame_width, u32 frame_height, u3= 2 num_vpp_pipes) +{ + u32 _size_bse =3D size_h265d_bse_cmd_buf(frame_width, frame_height); + u32 _size_vpp =3D size_h265d_vpp_cmd_buf(frame_width, frame_height); + u32 _size =3D ALIGN(_size_bse, DMA_ALIGNMENT) + + ALIGN(_size_vpp, DMA_ALIGNMENT) + + ALIGN(NUM_HW_PIC_BUF * 20 * 22 * 4, DMA_ALIGNMENT) + + ALIGN(2 * sizeof(u16) * + (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS), DMA_ALIGNM= ENT) + + ALIGN(SIZE_HW_PIC(SIZE_H265D_HW_PIC_T), DMA_ALIGNMENT) + + HDR10_HIST_EXTRADATA_SIZE; + + return ALIGN(_size, DMA_ALIGNMENT); +} + static u32 size_vpss_lb(u32 frame_width, u32 frame_height) { u32 opb_lb_wr_llb_y_buffer_size, opb_lb_wr_llb_uv_buffer_size; @@ -119,6 +232,203 @@ static u32 size_vpss_lb(u32 frame_width, u32 frame_he= ight) opb_lb_wr_llb_y_buffer_size; } =20 +static inline +u32 size_h265d_lb_fe_top_data(u32 frame_width, u32 frame_height) +{ + return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * + (ALIGN(frame_width, 64) + 8) * 2; +} + +static inline +u32 size_h265d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height) +{ + return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * + (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS); +} + +static inline +u32 size_h265d_lb_fe_left_ctrl(u32 frame_width, u32 frame_height) +{ + return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS); +} + +static inline +u32 size_h265d_lb_se_top_ctrl(u32 frame_width, u32 frame_height) +{ + return (LCU_MAX_SIZE_PELS / 8 * (128 / 8)) * ((frame_width + 15) >> 4); +} + +static inline +u32 size_h265d_lb_se_left_ctrl(u32 frame_width, u32 frame_height) +{ + return max_t(u32, ((frame_height + 16 - 1) / 8) * + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, + max_t(u32, ((frame_height + 32 - 1) / 8) * + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, + ((frame_height + 64 - 1) / 8) * + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); +} + +static inline +u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 frame_height) +{ + return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * + (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS); +} + +static inline +u32 size_h265d_lb_vsp_top(u32 frame_width, u32 frame_height) +{ + return ((frame_width + 63) >> 6) * 128; +} + +static inline +u32 size_h265d_lb_vsp_left(u32 frame_width, u32 frame_height) +{ + return ((frame_height + 63) >> 6) * 128; +} + +static inline +u32 size_h265d_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height) +{ + return size_h264d_lb_recon_dma_metadata_wr(frame_height); +} + +static inline +u32 size_h265d_qp(u32 frame_width, u32 frame_height) +{ + return size_h264d_qp(frame_width, frame_height); +} + +static inline +u32 hfi_buffer_line_h265d(u32 frame_width, u32 frame_height, bool is_opb, = u32 num_vpp_pipes) +{ + u32 vpss_lb_size =3D 0, _size; + + _size =3D ALIGN(size_h265d_lb_fe_top_data(frame_width, frame_height), DMA= _ALIGNMENT) + + ALIGN(size_h265d_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMEN= T) + + ALIGN(size_h265d_lb_fe_left_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_h265d_lb_se_left_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_h265d_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMEN= T) + + ALIGN(size_h265d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMEN= T) + + ALIGN(size_h265d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) + + ALIGN(size_h265d_lb_vsp_left(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_h265d_lb_recon_dma_metadata_wr(frame_width, frame_height), + DMA_ALIGNMENT) * 4 + + ALIGN(size_h265d_qp(frame_width, frame_height), DMA_ALIGNMENT); + if (is_opb) + vpss_lb_size =3D size_vpss_lb(frame_width, frame_height); + + return ALIGN((_size + vpss_lb_size), DMA_ALIGNMENT); +} + +static inline +u32 size_vpxd_lb_fe_left_ctrl(u32 frame_width, u32 frame_height) +{ + return max_t(u32, ((frame_height + 15) >> 4) * + MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, + max_t(u32, ((frame_height + 31) >> 5) * + MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, + ((frame_height + 63) >> 6) * + MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); +} + +static inline +u32 size_vpxd_lb_fe_top_ctrl(u32 frame_width, u32 frame_height) +{ + return ((ALIGN(frame_width, 64) + 8) * 10 * 2); +} + +static inline +u32 size_vpxd_lb_se_top_ctrl(u32 frame_width, u32 frame_height) +{ + return ((frame_width + 15) >> 4) * MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE; +} + +static inline +u32 size_vpxd_lb_se_left_ctrl(u32 frame_width, u32 frame_height) +{ + return max_t(u32, ((frame_height + 15) >> 4) * + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, + max_t(u32, ((frame_height + 31) >> 5) * + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, + ((frame_height + 63) >> 6) * + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); +} + +static inline +u32 size_vpxd_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height) +{ + return ALIGN((ALIGN(frame_height, 8) / (4 / 2)) * 64, + BUFFER_ALIGNMENT_32_BYTES); +} + +static inline +u32 size_mp2d_lb_fe_top_data(u32 frame_width, u32 frame_height) +{ + return ((ALIGN(frame_width, 16) + 8) * 10 * 2); +} + +static inline +u32 size_vp9d_lb_fe_top_data(u32 frame_width, u32 frame_height) +{ + return (ALIGN(ALIGN(frame_width, 8), 64) + 8) * 10 * 2; +} + +static inline +u32 size_vp9d_lb_pe_top_data(u32 frame_width, u32 frame_height) +{ + return ((ALIGN(ALIGN(frame_width, 8), 64) >> 6) * 176); +} + +static inline +u32 size_vp9d_lb_vsp_top(u32 frame_width, u32 frame_height) +{ + return (((ALIGN(ALIGN(frame_width, 8), 64) >> 6) * 64 * 8) + 256); +} + +static inline +u32 size_vp9d_qp(u32 frame_width, u32 frame_height) +{ + return size_h264d_qp(frame_width, frame_height); +} + +static inline +u32 hfi_iris3_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_= pipes) +{ + return ALIGN(size_vpxd_lb_fe_left_ctrl(frame_width, frame_height), DMA_AL= IGNMENT) * + num_vpp_pipes + + ALIGN(size_vpxd_lb_se_left_ctrl(frame_width, frame_height), DMA_ALIGNMEN= T) * + num_vpp_pipes + + ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) + + ALIGN(size_vpxd_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT= ) + + 2 * ALIGN(size_vpxd_lb_recon_dma_metadata_wr(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT= ) + + ALIGN(size_vp9d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT= ) + + ALIGN(size_vp9d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT= ) + + ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT); +} + +static inline +u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufco= unt_min, bool is_opb, + u32 num_vpp_pipes) +{ + u32 vpss_lb_size =3D 0; + u32 _lb_size; + + _lb_size =3D hfi_iris3_vp9d_lb_size(frame_width, frame_height, num_vpp_pi= pes); + + if (is_opb) + vpss_lb_size =3D size_vpss_lb(frame_width, frame_height); + + return _lb_size + vpss_lb_size + 4096; +} + static u32 hfi_buffer_line_h264d(u32 frame_width, u32 frame_height, bool is_opb, u32 num_vpp_pipes) { @@ -148,7 +458,14 @@ static u32 iris_vpu_dec_bin_size(struct iris_inst *ins= t) u32 height =3D f->fmt.pix_mp.height; u32 width =3D f->fmt.pix_mp.width; =20 - return hfi_buffer_bin_h264d(width, height, num_vpp_pipes); + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_bin_h264d(width, height, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_bin_h265d(width, height, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_buffer_bin_vp9d(width, height, num_vpp_pipes); + + return 0; } =20 static u32 iris_vpu_dec_comv_size(struct iris_inst *inst) @@ -158,12 +475,24 @@ static u32 iris_vpu_dec_comv_size(struct iris_inst *i= nst) u32 height =3D f->fmt.pix_mp.height; u32 width =3D f->fmt.pix_mp.width; =20 - return hfi_buffer_comv_h264d(width, height, num_comv); + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_comv_h264d(width, height, num_comv); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_comv_h265d(width, height, num_comv); + + return 0; } =20 static u32 iris_vpu_dec_persist_size(struct iris_inst *inst) { - return hfi_buffer_persist_h264d(); + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_persist_h264d(); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_persist_h265d(0); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_buffer_persist_vp9d(); + + return 0; } =20 static u32 iris_vpu_dec_dpb_size(struct iris_inst *inst) @@ -181,7 +510,12 @@ static u32 iris_vpu_dec_non_comv_size(struct iris_inst= *inst) u32 height =3D f->fmt.pix_mp.height; u32 width =3D f->fmt.pix_mp.width; =20 - return hfi_buffer_non_comv_h264d(width, height, num_vpp_pipes); + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_non_comv_h264d(width, height, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_non_comv_h265d(width, height, num_vpp_pipes); + + return 0; } =20 static u32 iris_vpu_dec_line_size(struct iris_inst *inst) @@ -191,11 +525,20 @@ static u32 iris_vpu_dec_line_size(struct iris_inst *i= nst) u32 height =3D f->fmt.pix_mp.height; u32 width =3D f->fmt.pix_mp.width; bool is_opb =3D false; + u32 out_min_count =3D inst->buffers[BUF_OUTPUT].min_count; =20 if (iris_split_mode_enabled(inst)) is_opb =3D true; =20 - return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes); + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_buffer_line_vp9d(width, height, out_min_count, is_opb, + num_vpp_pipes); + + return 0; } =20 static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst) @@ -205,6 +548,24 @@ static u32 iris_vpu_dec_scratch1_size(struct iris_inst= *inst) iris_vpu_dec_line_size(inst); } =20 +static int output_min_count(struct iris_inst *inst) +{ + int output_min_count =3D 4; + + /* fw_min_count > 0 indicates reconfig event has already arrived */ + if (inst->fw_min_count) { + if (iris_split_mode_enabled(inst) && inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return min_t(u32, 4, inst->fw_min_count); + else + return inst->fw_min_count; + } + + if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + output_min_count =3D 9; + + return output_min_count; +} + struct iris_vpu_buf_type_handle { enum iris_buffer_type type; u32 (*handle)(struct iris_inst *inst); @@ -238,6 +599,19 @@ int iris_vpu_buf_size(struct iris_inst *inst, enum iri= s_buffer_type buffer_type) return size; } =20 +static u32 internal_buffer_count(struct iris_inst *inst, + enum iris_buffer_type buffer_type) +{ + if (buffer_type =3D=3D BUF_BIN || buffer_type =3D=3D BUF_LINE || + buffer_type =3D=3D BUF_PERSIST) { + return 1; + } else if (buffer_type =3D=3D BUF_COMV || buffer_type =3D=3D BUF_NON_COMV= ) { + if (inst->codec =3D=3D V4L2_PIX_FMT_H264 || inst->codec =3D=3D V4L2_PIX_= FMT_HEVC) + return 1; + } + return 0; +} + static inline int iris_vpu_dpb_count(struct iris_inst *inst) { if (iris_split_mode_enabled(inst)) { @@ -254,12 +628,13 @@ int iris_vpu_buf_count(struct iris_inst *inst, enum i= ris_buffer_type buffer_type case BUF_INPUT: return MIN_BUFFERS; case BUF_OUTPUT: - return inst->fw_min_count; + return output_min_count(inst); case BUF_BIN: case BUF_COMV: case BUF_NON_COMV: case BUF_LINE: case BUF_PERSIST: + return internal_buffer_count(inst, buffer_type); case BUF_SCRATCH_1: return 1; /* internal buffer count needed by firmware is 1 */ case BUF_DPB: diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.h index 62af6ea6ba1f..2272f0c21683 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -13,6 +13,10 @@ struct iris_inst; #define DMA_ALIGNMENT 256 =20 #define NUM_HW_PIC_BUF 32 +#define LCU_MAX_SIZE_PELS 64 +#define LCU_MIN_SIZE_PELS 16 +#define HDR10_HIST_EXTRADATA_SIZE (4 * 1024) + #define SIZE_HW_PIC(size_per_buf) (NUM_HW_PIC_BUF * (size_per_buf)) =20 #define MAX_TILE_COLUMNS 32 @@ -28,11 +32,47 @@ struct iris_inst; #define SIZE_SLIST_BUF_H264 512 #define H264_DISPLAY_BUF_SIZE 3328 #define H264_NUM_FRM_INFO 66 - -#define SIZE_SEI_USERDATA 4096 - +#define H265_NUM_TILE_COL 32 +#define H265_NUM_TILE_ROW 12 +#define H265_NUM_TILE (H265_NUM_TILE_ROW * H265_NUM_TILE_COL + 1) +#define SIZE_H265D_BSE_CMD_PER_BUF (16 * sizeof(u32)) + +#define NUM_SLIST_BUF_H265 (80 + 20) +#define SIZE_SLIST_BUF_H265 (BIT(10)) +#define H265_DISPLAY_BUF_SIZE (3072) +#define H265_NUM_FRM_INFO (48) + +#define VP9_NUM_FRAME_INFO_BUF 32 +#define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4) +#define VP9_PROB_TABLE_SIZE (3840) +#define VP9_FRAME_INFO_BUF_SIZE (6144) +#define BUFFER_ALIGNMENT_32_BYTES 32 +#define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES) +#define MAX_SUPERFRAME_HEADER_LEN (34) +#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 +#define MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE 64 +#define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64 +#define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8) +#define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8) +#define VP9_UDC_HEADER_BUF_SIZE (3 * 128) + +#define SIZE_SEI_USERDATA 4096 +#define SIZE_DOLBY_RPU_METADATA (41 * 1024) #define H264_CABAC_HDR_RATIO_HD_TOT 1 #define H264_CABAC_RES_RATIO_HD_TOT 3 +#define H265D_MAX_SLICE 1200 +#define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T +#define H265_CABAC_HDR_RATIO_HD_TOT 2 +#define H265_CABAC_RES_RATIO_HD_TOT 2 +#define SIZE_H265D_VPP_CMD_PER_BUF (256) + +#define VPX_DECODER_FRAME_CONCURENCY_LVL (2) +#define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1 +#define VPX_DECODER_FRAME_BIN_RES_BUDGET 3 +#define VPX_DECODER_FRAME_BIN_DENOMINATOR 2 + +#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2) + #define SIZE_H264D_HW_PIC_T (BIT(11)) =20 #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 --=20 2.34.1 From nobody Mon Feb 9 02:38:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 626FE246797; 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Thu, 01 May 2025 19:16:16 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 541JGEOU005620 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 1 May 2025 19:16:14 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 1 May 2025 12:16:09 -0700 From: Dikshita Agarwal Date: Fri, 2 May 2025 00:43:53 +0530 Subject: [PATCH v3 23/23] media: iris: Add codec specific check for VP9 decoder drain handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250502-qcom-iris-hevc-vp9-v3-23-552158a10a7d@quicinc.com> References: <20250502-qcom-iris-hevc-vp9-v3-0-552158a10a7d@quicinc.com> In-Reply-To: <20250502-qcom-iris-hevc-vp9-v3-0-552158a10a7d@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Mauro Carvalho Chehab , Stefan Schmidt , Hans Verkuil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Bryan O'Donoghue , Dmitry Baryshkov , Neil Armstrong , Nicolas Dufresne , , , , , Dikshita Agarwal , <20250417-topic-sm8x50-iris-v10-v7-0-f020cb1d0e98@linaro.org>, <20250424-qcs8300_iris-v5-0-f118f505c300@quicinc.com> X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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The firmware enforces a check for VP9 decoder that the number of buffers queued and dequeued on the output plane should match. When a null buffer is sent, the firmware does not return a response for it, leading to a count mismatch and an assertion failure from the firmware. Acked-by: Vikash Garodia Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c | 2 ++ drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 2e3f5a6b2ff1..5fc30d54af4d 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -401,6 +401,8 @@ static int iris_hfi_gen1_session_drain(struct iris_inst= *inst, u32 plane) ip_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_EMPTY_BUFFER; ip_pkt.shdr.session_id =3D inst->session_id; ip_pkt.flags =3D HFI_BUFFERFLAG_EOS; + if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + ip_pkt.packet_buffer =3D 0xdeadb000; =20 return iris_hfi_queue_cmd_write(inst->core, &ip_pkt, ip_pkt.shdr.hdr.size= ); } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 926acee1f48c..8d1ce8a19a45 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -348,6 +348,10 @@ static void iris_hfi_gen1_session_etb_done(struct iris= _inst *inst, void *packet) struct iris_buffer *buf =3D NULL; bool found =3D false; =20 + /* EOS buffer sent via drain won't be in v4l2 buffer list */ + if (pkt->packet_buffer =3D=3D 0xdeadb000) + return; + v4l2_m2m_for_each_src_buf_safe(m2m_ctx, m2m_buffer, n) { buf =3D to_iris_buffer(&m2m_buffer->vb); if (buf->index =3D=3D pkt->input_tag) { --=20 2.34.1