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Fri, 02 May 2025 04:22:44 -0700 (PDT) Received: from [127.0.0.2] ([2a02:2454:ff21:ef41:3f2f:46a0:5bf3:f8f2]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad1891a2b6esm36062166b.42.2025.05.02.04.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 May 2025 04:22:44 -0700 (PDT) From: Stephan Gerhold Date: Fri, 02 May 2025 13:22:28 +0200 Subject: [PATCH] irqchip/qcom-mpm: Fix crash when trying to handle non-wake GPIOs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250502-irq-qcom-mpm-fix-no-wake-v1-1-8a1eafcd28d4@linaro.org> X-B4-Tracking: v=1; b=H4sIAPOqFGgC/x2MQQqAIBAAvxJ7bsE2guwr0SF0qyXUUqgg/HvSc RhmXkgchRMM1QuRL0kSfIGmrsBss18ZxRYGUtSpThFKPPE0waE7HC7yoA94zzuj7XXLjdbUWgU lPyIX/a/HKecP+M52P2oAAAA= X-Change-ID: 20250502-irq-qcom-mpm-fix-no-wake-d893e19923d0 To: Thomas Gleixner Cc: Shawn Guo , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski , Alexey Klimov X-Mailer: b4 0.14.2 On Qualcomm chipsets not all GPIOs are wakeup capable. Those GPIOs do not have a corresponding MPM pin and should not be handled inside the MPM driver. The IRQ domain hierarchy is always applied, so we need to explicitly disconnect the hierarchy for those. The pinctrl-msm driver marks these with GPIO_NO_WAKE_IRQ. qcom-pdc has a check for this, but irq-qcom-mpm is currently missing the check. This is causing crashes when setting up interrupts for non-wake GPIOs, e.g. root@rb1:~# gpiomon -c gpiochip1 10 irq: IRQ159: trimming hierarchy from :soc@0:interrupt-controller@f200000= -1 Unable to handle kernel paging request at virtual address ffff8000a1dc38= 20 Hardware name: Qualcomm Technologies, Inc. Robotics RB1 (DT) pc : mpm_set_type+0x80/0xcc lr : mpm_set_type+0x5c/0xcc Call trace: mpm_set_type+0x80/0xcc (P) qcom_mpm_set_type+0x64/0x158 irq_chip_set_type_parent+0x20/0x38 msm_gpio_irq_set_type+0x50/0x530 __irq_set_trigger+0x60/0x184 __setup_irq+0x304/0x6bc request_threaded_irq+0xc8/0x19c edge_detector_setup+0x260/0x364 linereq_create+0x420/0x5a8 gpio_ioctl+0x2d4/0x6c0 Fix this by copying the check for GPIO_NO_WAKE_IRQ from qcom-pdc.c, so that MPM is removed entirely from the hierarchy for non-wake GPIOs. Cc: stable@vger.kernel.org Reported-by: Alexey Klimov Tested-by: Alexey Klimov Fixes: a6199bb514d8 ("irqchip: Add Qualcomm MPM controller driver") Signed-off-by: Stephan Gerhold Reviewed-by: Bartosz Golaszewski --- drivers/irqchip/irq-qcom-mpm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index 7942d8eb3d00eae5fa7e5718a05ef889bb8a82f0..f772deb9cba574b9f70649e1646= f16a993eba58a 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -227,6 +227,9 @@ static int qcom_mpm_alloc(struct irq_domain *domain, un= signed int virq, if (ret) return ret; =20 + if (pin =3D=3D GPIO_NO_WAKE_IRQ) + return irq_domain_disconnect_hierarchy(domain, virq); + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, pin, &qcom_mpm_chip, priv); if (ret) --- base-commit: e6a3fc4f10b872d02e25f83227e725c79b25d893 change-id: 20250502-irq-qcom-mpm-fix-no-wake-d893e19923d0 Best regards, --=20 Stephan Gerhold