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Thu, 01 May 2025 03:01:37 -0700 (PDT) From: Sayyad Abid To: linux-iio@vger.kernel.org Cc: sayyad.abid16@gmail.com, jic23@kernel.org, lars@metafoo.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, javier.carrasco.cruz@gmail.com, olivier.moysan@foss.st.com, gstols@baylibre.com, tgamblin@baylibre.com, alisadariana@gmail.com, eblanc@baylibre.com, antoniu.miclaus@analog.com, andriy.shevchenko@linux.intel.com, stefan.popa@analog.com, ramona.gradinariu@analog.com, herve.codina@bootlin.com, tobias.sperling@softing.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 1/5] iio: adc: ti-ads1262.c: add initial driver for TI ADS1262 ADC Date: Thu, 1 May 2025 15:30:39 +0530 Message-Id: <20250501100043.325423-2-sayyad.abid16@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250501100043.325423-1-sayyad.abid16@gmail.com> References: <20250501100043.325423-1-sayyad.abid16@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the core driver file `ti-ads1262.c` for the TI ADS1262 ADC. This initial version implements basic IIO functionality for device probe via SPI and reading raw voltage samples from input channels. Signed-off-by: Sayyad Abid --- drivers/iio/adc/ti-ads1262.c | 438 +++++++++++++++++++++++++++++++++++ 1 file changed, 438 insertions(+) create mode 100644 drivers/iio/adc/ti-ads1262.c diff --git a/drivers/iio/adc/ti-ads1262.c b/drivers/iio/adc/ti-ads1262.c new file mode 100644 index 000000000000..ef34c528ffeb --- /dev/null +++ b/drivers/iio/adc/ti-ads1262.c @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IIO driver for Texas Instruments ADS1662 32-bit ADC + * + * Datasheet: https://www.ti.com/product/ADS1262 + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Commands */ +#define ADS1262_CMD_RESET 0x06 +#define ADS1262_CMD_START1 0x08 +#define ADS1262_CMD_STOP1 0x0A +#define ADS1262_CMD_RDATA1 0x12 +#define ADS1262_CMD_RREG 0x20 +#define ADS1262_CMD_WREG 0x40 + +/* Registers */ +#define ADS1262_REG_ID 0x00 +#define ADS1262_REG_POWER 0x01 +#define ADS1262_REG_INTERFACE 0x02 +#define ADS1262_REG_MODE0 0x03 +#define ADS1262_REG_MODE1 0x04 +#define ADS1262_REG_MODE2 0x05 +#define ADS1262_REG_INPMUX 0x06 + +/* Configurations */ +#define ADS1262_INTREF_ENABLE 0x01 +#define ADS1262_MODE0_ONE_SHOT 0x40 +#define ADS1262_MODE2_PGA_EN 0x00 +#define ADS1262_MODE2_PGA_BYPASS BIT(7) + +/* Masks */ +#define ADS1262_MASK_MODE2_DR GENMASK(4, 0) + +/* ADS1262_SPECS */ +#define ADS1262_MAX_CHANNELS 11 +#define ADS1262_BITS_PER_SAMPLE 32 +#define ADS1262_CLK_RATE_HZ 7372800 +#define ADS1262_CLOCKS_TO_USECS(x) \ + (DIV_ROUND_UP((x) * MICROHZ_PER_HZ, ADS1262_CLK_RATE_HZ)) +#define ADS1262_VOLTAGE_INT_REF_uV 2500000 +#define ADS1262_TEMP_SENSITIVITY_uV_per_C 420 + +#define ADS1262_SETTLE_TIME_USECS 10000 + +/* The Read/Write commands require 4 tCLK to encode and decode, for speeds + * 2x the clock rate, these commands would require extra time between the + * command byte and the data. A simple way to tacke this issue is by + * limiting the SPI bus transfer speed while accessing registers. + */ +#define ADS1262_SPI_BUS_SPEED_SLOW ADS1262_CLK_RATE_HZ + +/* For reading and writing we need a buffer of size 3bytes*/ +#define ADS1262_SPI_CMD_BUFFER_SIZE 3 + +/* Read data buffer size for + * 1 status byte - 4 byte data (32 bit) - 1 byte checksum / CRC + */ +#define ADS1262_SPI_RDATA_BUFFER_SIZE 6 + +#define MILLI 1000 + +/** + * struct ads1262_private - ADS1262 ADC private data structure + * @spi: SPI device structure + * @reset_gpio: GPIO descriptor for reset pin + * @prev_channel: Previously selected channel for MUX configuration + * @cmd_buffer: Buffer for SPI command transfers + * @rx_buffer: Buffer for SPI data reception + */ +struct ads1262_private { + struct spi_device *spi; + struct gpio_desc *reset_gpio; + u8 prev_channel; + u8 cmd_buffer[ADS1262_SPI_CMD_BUFFER_SIZE]; + u8 rx_buffer[ADS1262_SPI_RDATA_BUFFER_SIZE] __aligned(IIO_DMA_MINALIGN); +}; + +#define ADS1262_CHAN(index) \ +{ \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D index, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .scan_index =3D index, \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D ADS1262_BITS_PER_SAMPLE, \ + .storagebits =3D 32, \ + .endianness =3D IIO_CPU \ + }, \ +} + +#define ADS1262_DIFF_CHAN(index, pos_channel, neg_channel) \ +{ \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D pos_channel, \ + .channel2 =3D neg_channel, \ + .differential =3D 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .scan_index =3D index, \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D ADS1262_BITS_PER_SAMPLE, \ + .storagebits =3D 32, \ + .endianness =3D IIO_CPU \ + }, \ +} + +#define ADS1262_TEMP_CHAN(index) \ +{ \ + .type =3D IIO_TEMP, \ + .indexed =3D 1, \ + .channel =3D index, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index =3D index, \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D ADS1262_BITS_PER_SAMPLE, \ + .storagebits =3D 32, \ + .endianness =3D IIO_BE, \ + }, \ +} + +static const struct iio_chan_spec ads1262_channels[] =3D { + /* Single ended channels*/ + ADS1262_CHAN(0), + ADS1262_CHAN(1), + ADS1262_CHAN(2), + ADS1262_CHAN(3), + ADS1262_CHAN(4), + ADS1262_CHAN(5), + ADS1262_CHAN(6), + ADS1262_CHAN(7), + ADS1262_CHAN(8), + ADS1262_CHAN(9), + /* The channel at index 10 is AINCOM, which is the common ground + * of the ADC. It is not a valid channel for the user. + */ + + /* Temperature and Monitor channels */ + ADS1262_TEMP_CHAN(11), /* TEMP SENSOR */ + ADS1262_CHAN(12), /* AVDD MON */ + ADS1262_CHAN(13), /* DVDD MON */ + ADS1262_CHAN(14), /* TDAC TEST */ + /* Differential channels */ + ADS1262_DIFF_CHAN(15, 0, 1), /* AIN0 - AIN1 */ + ADS1262_DIFF_CHAN(16, 2, 3), /* AIN2 - AIN3 */ + ADS1262_DIFF_CHAN(17, 4, 5), /* AIN4 - AIN5 */ + ADS1262_DIFF_CHAN(18, 6, 7), /* AIN6 - AIN7 */ + ADS1262_DIFF_CHAN(19, 8, 9), /* AIN8 - AIN9 */ +}; + +static int ads1262_write_cmd(struct ads1262_private *priv, u8 command) +{ + struct spi_transfer xfer =3D { + .tx_buf =3D priv->cmd_buffer, + .rx_buf =3D priv->rx_buffer, + .len =3D ADS1262_SPI_RDATA_BUFFER_SIZE, + .speed_hz =3D ADS1262_CLK_RATE_HZ, + }; + + priv->cmd_buffer[0] =3D command; + + return spi_sync_transfer(priv->spi, &xfer, 1); +} + +static int ads1262_reg_write(void *context, unsigned int reg, unsigned int= val) +{ + struct ads1262_private *priv =3D context; + + priv->cmd_buffer[0] =3D ADS1262_CMD_WREG | reg; + priv->cmd_buffer[1] =3D 0; + priv->cmd_buffer[2] =3D val; + + return spi_write(priv->spi, &priv->cmd_buffer[0], 3); +} + +static int ads1262_reg_read(void *context, unsigned int reg) +{ + struct ads1262_private *priv =3D context; + struct spi_transfer reg_read_xfer =3D { + .tx_buf =3D priv->cmd_buffer, + .rx_buf =3D priv->cmd_buffer, + .len =3D 3, + .speed_hz =3D ADS1262_CLK_RATE_HZ, + }; + int ret; + + priv->cmd_buffer[0] =3D ADS1262_CMD_RREG | reg; + priv->cmd_buffer[1] =3D 0; + priv->cmd_buffer[2] =3D 0; + + ret =3D spi_sync_transfer(priv->spi, ®_read_xfer, 1); + if (ret) + return ret; + + return 0; +} + +static int ads1262_reset(struct iio_dev *indio_dev) +{ + struct ads1262_private *priv =3D iio_priv(indio_dev); + + if (priv->reset_gpio) { + gpiod_set_value(priv->reset_gpio, 0); + usleep_range(200, 300); + gpiod_set_value(priv->reset_gpio, 1); + } else { + return ads1262_write_cmd(priv, ADS1262_CMD_RESET); + } + return 0; +} + +static int ads1262_init(struct iio_dev *indio_dev) +{ + struct ads1262_private *priv =3D iio_priv(indio_dev); + int ret =3D 0; + + ret =3D ads1262_reset(indio_dev); + if (ret) + return ret; + + /* 10 milliseconds settling time for the ADC to stabilize */ + fsleep(ADS1262_SETTLE_TIME_USECS); + + /* Clearing the RESET bit in the power register to detect ADC reset */ + ret =3D ads1262_reg_write(priv, ADS1262_REG_POWER, ADS1262_INTREF_ENABLE); + if (ret) + return ret; + + /* Setting the ADC to one-shot conversion mode */ + ret =3D ads1262_reg_write(priv, ADS1262_REG_MODE0, ADS1262_MODE0_ONE_SHOT= ); + if (ret) + return ret; + + ret =3D ads1262_reg_read(priv, ADS1262_REG_INPMUX); + if (ret) + return ret; + + priv->prev_channel =3D priv->cmd_buffer[2]; + + return ret; +} + +static int ads1262_get_samp_freq(struct ads1262_private *priv, int *val) +{ + unsigned long samp_freq; + int ret; + + ret =3D ads1262_reg_read(priv, ADS1262_REG_MODE2); + if (ret) + return ret; + + samp_freq =3D priv->cmd_buffer[2]; + + *val =3D (samp_freq & ADS1262_MASK_MODE2_DR); + + return IIO_VAL_INT; +} + +/** + * ads1262_read - Read a single sample from the ADC + * @priv: Pointer to the ADS1262 private data structure + * @chan: Pointer to the IIO channel specification + * @val: Pointer to store the read value + * + * Reads a single sample from the specified ADC channel. For differential + * channels, it sets up the MUX with both channels. For single-ended chann= els, + * it uses the channel number and AINCOM (0x0A). + * + * Return: 0 on success, negative error code on failure + */ +static int ads1262_read(struct ads1262_private *priv, + struct iio_chan_spec const *chan, int *val) +{ + u8 mux_value; + int ret; + + if (chan->differential) { + mux_value =3D (chan->channel << 4) | chan->channel2; + } else { + /* For single-ended channels, use the channel number on one end + * and AINCOM (0x0A) on the other end + */ + mux_value =3D (chan->channel << 4) | 0x0A; + } + + if (mux_value !=3D priv->prev_channel) { + ret =3D ads1262_write_cmd(priv, ADS1262_CMD_STOP1); + if (ret) + return ret; + + ret =3D ads1262_reg_write(priv, ADS1262_REG_INPMUX, mux_value); + if (ret) + return ret; + + priv->prev_channel =3D mux_value; + } + + ret =3D ads1262_write_cmd(priv, ADS1262_CMD_START1); + if (ret) + return ret; + + usleep_range(1000, 2000); + + *val =3D sign_extend64(get_unaligned_be32(priv->rx_buffer + 1), + ADS1262_BITS_PER_SAMPLE - 1); + + return 0; +} + +static int ads1262_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct ads1262_private *spi =3D iio_priv(indio_dev); + s64 temp; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ads1262_read(spi, chan, val); + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_VOLTAGE: + *val =3D ADS1262_VOLTAGE_INT_REF_uV; + *val2 =3D chan->scan_type.realbits; + return IIO_VAL_FRACTIONAL_LOG2; + case IIO_TEMP: + temp =3D (s64)ADS1262_VOLTAGE_INT_REF_uV * MILLI; + temp /=3D ADS1262_TEMP_SENSITIVITY_uV_per_C; + *val =3D temp; + *val2 =3D chan->scan_type.realbits; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_SAMP_FREQ: + return ads1262_get_samp_freq(spi, val); + default: + return -EINVAL; + } +} + +static const struct iio_info ads1262_info =3D { + .read_raw =3D ads1262_read_raw, +}; + +static void ads1262_stop(void *ptr) +{ + struct ads1262_private *adc =3D ptr; + + ads1262_write_cmd(adc, ADS1262_CMD_STOP1); +} + +static int ads1262_probe(struct spi_device *spi) +{ + struct ads1262_private *adc; + struct iio_dev *indio_dev; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc =3D iio_priv(indio_dev); + adc->spi =3D spi; + + spi->mode =3D SPI_MODE_1; + spi->max_speed_hz =3D ADS1262_SPI_BUS_SPEED_SLOW; + spi_set_drvdata(spi, indio_dev); + + indio_dev->dev.parent =3D &spi->dev; + indio_dev->name =3D spi_get_device_id(spi)->name; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D ads1262_channels; + indio_dev->num_channels =3D ARRAY_SIZE(ads1262_channels); + indio_dev->info =3D &ads1262_info; + + ret =3D ads1262_reg_read(adc, ADS1262_REG_ID); + if (ret) + return ret; + + if (adc->rx_buffer[2] !=3D ADS1262_REG_ID) + dev_err_probe(&spi->dev, -EINVAL, "Wrong device ID 0x%x\n", + adc->rx_buffer[2]); + + ret =3D devm_add_action_or_reset(&spi->dev, ads1262_stop, adc); + if (ret) + return ret; + + ret =3D ads1262_init(indio_dev); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static struct spi_device_id ads1262_id_table[] =3D { + { "ads1262" }, + {} +}; +MODULE_DEVICE_TABLE(spi, ads1262_id_table); + +static const struct of_device_id ads1262_of_match[] =3D { + { .compatible =3D "ti,ads1262" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ads1262_of_match); + +static struct spi_driver ads1262_driver =3D { + .driver =3D { + .name =3D "ads1262", + .of_match_table =3D ads1262_of_match, + }, + .probe =3D ads1262_probe, + .id_table =3D ads1262_id_table, +}; +module_spi_driver(ads1262_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Sayyad Abid "); +MODULE_DESCRIPTION("TI ADS1262 ADC"); --=20 2.39.5