From nobody Mon Feb 9 01:17:34 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B14DB27510B; Thu, 1 May 2025 07:30:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746084604; cv=none; b=FSXTm89JxUKKTS7eeXgcDGgvznTfjSy82+6uXX9JmXJROteZiFbdo1ONybj7UaPdmePeUJ9+weFSgf3PejqJtU91mbNFtnt0Fy6igDSTutE50qJDO22MtlwPEtOXvi0GFR1v59ANWuwACWGwc56DapY0RdBr4HLQzoqOiC75wDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746084604; c=relaxed/simple; bh=qmJzK1KsFbjxFaviZGe+X3O14b1NctKbwqRyJwKzkzU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LA57Et3ivZDJzRBWTmiOcgvYviMrQnWyXqC8jpfDUxib1nr3UVi3kArUmpl8ui9SnGkwmIEVD5teoj/Oa1ZkYVDDdKdtqTqS1TSLMHy5VECjvjzHQ/HBnfMosVfz4RDvdghOzlerGeYyRHiWgcFcApUGeC2Cr/kJ8hUSdlmmZ54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=wXc/nkaJ; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="wXc/nkaJ" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5417TviN4160581 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 1 May 2025 02:29:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746084597; bh=Du7fmxFaT2Dho3YcT2SozYDlmnXc97lplTOiOtsjxW4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wXc/nkaJB+jSltMUiiT6YwAkhWrjXnRGMqAQG7WiY2e2BkdpWCVWMi1ixG5TR9qHE SsRuNepqFoH/ChO90c1xVAgbH5iWM6Nxan26f4G5gH/i7GgsQdkxWIFkNBUxuzLkk7 i7njFak3BI+iCP3haFfzWvLwiXtZpPKUIXT3Blpk= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5417TvLA119713 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 May 2025 02:29:57 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 May 2025 02:29:57 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 May 2025 02:29:56 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5417TuHa102658; Thu, 1 May 2025 02:29:56 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , Subject: [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM62D2 SoC Date: Thu, 1 May 2025 12:59:21 +0530 Message-ID: <20250501072923.1262414-2-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250501072923.1262414-1-p-bhagat@ti.com> References: <20250501072923.1262414-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The AM62D2 SoC belongs to the K3 Multicore SoC architecture with DSP core targeted for applications needing high-performance Digital Signal Processing. It is used in applications like automotive audio systems, professional sound equipment, radar and radio for aerospace, sonar in marine devices, and ultrasound in medical imaging. It also supports precise signal analysis in test and measurement tools. Some highlights of AM62D2 SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * DSP with Matrix Multiplication Accelerator(MMA) (up to 2 TOPS) based on single core C7x. * 3x Multichannel Audio Serial Ports (McASP) Up to 4/6/16 Serial Data Pins which can Transmit and Receive Clocks up to 50MHz, with multi-channel I2S and TDM Audio inputs and outputs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports with TSN capable to enable audio networking features such as, Ethernet Audio Video Bridging (eAVB) and Dante. * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, OSPI memory controller, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment. * One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Low power mode support: Partial IO support for CAN/GPIO/UART wakeup. This adds dt bindings for TI's AM62D2 family of devices. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/sprujd4 Signed-off-by: Paresh Bhagat --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index 18f155cd06c8..3183089dcfbf 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -31,6 +31,12 @@ properties: - const: phytec,am62a-phycore-som - const: ti,am62a7 =20 + - description: K3 AM62D2 SoC and Boards + items: + - enum: + - ti,am62d2-evm + - const: ti,am62d2 + - description: K3 AM62P5 SoC and Boards items: - enum: --=20 2.34.1 From nobody Mon Feb 9 01:17:34 2026 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C51B426FD87; Thu, 1 May 2025 07:30:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746084608; cv=none; b=cBx9DRWqnXz1NbN0zJ8GbnMw4v6uhcw/jzmksmhwEzl86Wd+IR4cJ4BAg5LqJ653KmfCtRGci6ERUOaChaMDIN7sLOpUoSz9xTfGgEaQC4c2wFH/+rGoJ5yY3Et/JWzSj8cLhbbhDeTiDpwbe5fHmOkBFoHl23vbR99SGF7wUBE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746084608; c=relaxed/simple; bh=1A9CY0H/kYTojtxll//4SQPbJ+jWznvduyifJPT4qpI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=N2CidTB0aIANDfvvVYfw9Qf8Am9LgnlWOUA8ZhC8Pn7e/ZTPOOGX+3EaPTfrv2Ds2SO/160qTomjeH1qDvr01zLyq9LqBoefuy2r46Y1ATW4GfQSnm0YEqaVXqBmxDiwNkLWkJdbqqwUwsEPkuB5y7K+auuCaFdKtN/KNbXW6pU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=NApAoULN; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="NApAoULN" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5417U0BO3571459 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 1 May 2025 02:30:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746084601; bh=2nB2XrYs3/yr4cfRNXfAXTu6rjkWvNQLgoMjODS48vE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NApAoULNGwiNNsRrKxA2fzEhZVpm4/KiYsRE1wVAJJ8Hn0CFVaPtve//2TU0wLm8O nCv6cf68UE9Jz51iF3+aLI8S0C7kyEcJa9ovKzswJtKqzXijVD+i5Tx9MZenYK9JPG kNZzrOwf6SyPACWaXzZqlI6LW8RiL3m3oVScz+xo= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5417U0TQ014995 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 May 2025 02:30:00 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 May 2025 02:30:00 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 May 2025 02:30:00 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5417Tx6M102706; Thu, 1 May 2025 02:29:59 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , Subject: [PATCH 2/3] arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs Date: Thu, 1 May 2025 12:59:22 +0530 Message-ID: <20250501072923.1262414-3-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250501072923.1262414-1-p-bhagat@ti.com> References: <20250501072923.1262414-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Update k3-pinctrl file to include pin definitions for AM62D2 family of SoCs. Signed-off-by: Paresh Bhagat --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index cac7cccc1112..0cf57179c974 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -63,6 +63,9 @@ #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 +#define AM62DX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) +#define AM62DX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) + #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 --=20 2.34.1 From nobody Mon Feb 9 01:17:35 2026 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A8D41C6FE0; Thu, 1 May 2025 07:30:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746084627; cv=none; b=TocB2nTdXt0ZFByWFYsVyHj2gcijgCjN5OJOD/WMggvYDJ5lpjDUxyyt/duglw28oudbKgWX8nL7w6nb6PlQ6qh893E6T48XkRBOcuAq9119BF1q5XKOVCvDHZUNF0O6JjookDycxV+NEly3cWEUmJ4RAXuR7Ev8ZXSlvArr2uQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746084627; c=relaxed/simple; bh=MDYI5+hWjqP1ACN17bVmLlJaEwkApnSTgnKgnyD9itw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IssQoS23XCVpw0HaivzbrQphrHzQQp6VPP0ocvkKAOqV3lWIoPzUeEUNUlY1Dcp9+h0LLsSqAvNqMLGiLgZwKYLLYUd29n/sXZMpa3T07nJGELL3u+2sp0V9HLoePEFk5vt9zvG/vgtkdzmMPuJ9x//BU2Y9TDuBeK9kgIFHbMk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=SZ6trDkH; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="SZ6trDkH" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5417UIMu3571544 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 1 May 2025 02:30:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746084618; bh=AZeNmsECabU1Re7IS/fvy3fqmifS/ivFgzSSJC/EICs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SZ6trDkHepAIHEZEFGs1Dv6dWogVnDndSsFS4jIbby14LZF4MnvIQVHIzNFaSgXAC FfPbXSAJIh7/yB3lv8laI2lcTbemWqr8RmkpWlAyVhCas0k9GjupLH+6SZFPQlrg/r f/RK1Eb+A/EWOEhdjyVjoQqCktxiWoYASYGVYcFE= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5417UIBf059927 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 May 2025 02:30:18 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 May 2025 02:30:18 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 May 2025 02:30:18 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5417UHu1104714; Thu, 1 May 2025 02:30:18 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , Subject: [PATCH 3/3] arm64: dts: ti: Add support for AM62D2-EVM Date: Thu, 1 May 2025 12:59:23 +0530 Message-ID: <20250501072923.1262414-4-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250501072923.1262414-1-p-bhagat@ti.com> References: <20250501072923.1262414-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea AM62D EVM evaluation module (EVM) is a low-cost expandable platform board designed for TI=E2=80=99s AM62D2 SoC. It supports the following interfaces: * 4 GB LPDDR4 RAM * x2 Gigabit Ethernet expansion connectors * x4 3.5mm TRS Audio Jack Line In * x4 3.5mm TRS Audio Jack Line Out * x2 Audio expansion connectors * x1 Type-A USB 2.0, x1 Type-C dual-role device (DRD) USB 2.0 * x1 UHS-1 capable =C2=B5SD card slot * 32 GB eMMC Flash * 512 Mb OSPI NOR flash * x4 UARTs via USB 2.0-B * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs Add basic support for AM62D2-EVM. Schematics: https://www.ti.com/lit/zip/sprcal5 Signed-off-by: Paresh Bhagat --- arch/arm64/boot/dts/ti/Makefile | 3 + arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 449 +++++++++++++++++++++++ 2 files changed, 452 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62d2-evm.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 03d4cecfc001..80c6636a711d 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -32,6 +32,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am62-lp-sk-nand.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-phyboard-lyra-rdk.dtb =20 +# Boards with AM62Dx SoC +dtb-$(CONFIG_ARCH_K3) +=3D k3-am62d2-evm.dtb + # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-sk.dtb =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts new file mode 100644 index 000000000000..7a12ebe72c16 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * AM62D2 EVM: https://www.ti.com/lit/zip/sprcal5 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am62a7.dtsi" + +#include "k3-timesync-router.h" + +/ { + compatible =3D "ti,am62d2-evm", "ti,am62d2"; + model =3D "Texas Instruments AM62D2 EVM"; + + aliases { + serial0 =3D &wkup_uart0; + serial1 =3D &mcu_uart0; + serial2 =3D &main_uart0; + mmc1 =3D &sdhci1; + rtc0 =3D &wkup_rtc0; + }; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + memory@80000000 { + device_type =3D "memory"; + /* 4G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* global cma region */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x00 0x2000000>; + alloc-ranges =3D <0x00 0xc0000000 0x00 0x2000000>; + linux,cma-default; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0xf00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg =3D <0x00 0x9e780000 0x00 0x80000>; + alignment =3D <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment =3D <0x1000>; + no-map; + }; + }; + + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + }; + }; + + vout_pd: regulator-1 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vout_pd"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vmain_pd: load-switch { + /* Output of TPS22811 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vmain_pd"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vout_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-2 { + /* Output of TPS630702RNMR */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_5v0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpio =3D <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + vddshv_sdio: regulator-4 { + compatible =3D "regulator-gpio"; + regulator-name =3D "vddshv_sdio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vddshv_sdio_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + gpios =3D <&main_gpio1 31 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + }; +}; + +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins =3D < + AM62DX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */ + AM62DX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */ + AM62DX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */ + AM62DX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */ + >; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_uart0_pins_default>; + status =3D "reserved"; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x01c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ + AM62DX_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */ + AM62DX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C17) I2C1_SCL */ + AM62DX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (E17) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (M22) GPMC0_CSn2.I2C2_SCL = */ + AM62DX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (M20) GPMC0_CSn3.I2C2_SDA = */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x023c, PIN_INPUT, 0) /* (C21) MMC1_CMD */ + AM62DX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (E22) MMC1_CLK */ + AM62DX_IOPAD(0x0230, PIN_INPUT, 0) /* (B22) MMC1_DAT0 */ + AM62DX_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (D21) MMC1_DAT1 */ + AM62DX_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (C22) MMC1_DAT2 */ + AM62DX_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ + AM62DX_IOPAD(0x0240, PIN_INPUT, 0) /* (E18) MMC1_SDCD */ + AM62DX_IOPAD(0x0244, PIN_INPUT, 0) /* (D18) MMC1_SDWP */ + >; + }; + + main_mdio1_pins_default: main-mdio1-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ + AM62DX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ + >; + }; + + vddshv_sdio_pins_default: vddshv-sdio-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x1F4, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO1_31 */ + >; + }; +}; + +&mcu_pmx0 { + status =3D "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + AM62DX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */ + >; + }; +}; + +&mcu_gpio0 { + status =3D "okay"; +}; + +&main_i2c0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + clock-frequency =3D <400000>; + + typec_pd0: usb-power-controller@3f { + compatible =3D "ti,tps6598x"; + reg =3D <0x3f>; + + connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + self-powered; + data-role =3D "dual"; + power-role =3D "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint =3D <&usb0_hs_ep>; + }; + }; + }; + }; + + exp1: gpio@22 { + compatible =3D "ti,tca6424"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_gpio1_ioexp_intr_pins_default>; + + gpio-line-names =3D "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "MMC1_SD_EN", "VPP_EN", + "GPIO_DIX_RST", "IO_EXP_OPT_EN", + "DIX_INT", "GPIO_eMMC_RSTn", + "CPLD2_DONE", "CPLD2_INTN", + "CPLD1_DONE", "CPLD1_INTN", + "USB_TYPEA_OC_INDICATION", "PCM1_INT", + "PCM2_INT", "GPIO_PCM1_RST", + "TEST_GPIO2", "GPIO_PCM2_RST", + "IO_MCAN0_STB", "IO_MCAN1_STB", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + }; + + exp2: gpio@23 { + compatible =3D "ti,tca6424"; + reg =3D <0x23>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D "", "DAC_LAT_CTRL", + "CPLD1_JTAGENB", "CPLD1_PROGRAMN", + "CPLD2_JTAGENB", "CPLD2_PROGRAMN", + "", "", + "", "", + "", "", + "", "", + "", "", + "", "", + "SoC_I2C0_SCL", "SoC_I2C0_SDA"; + }; +}; + +&main_i2c1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c1_pins_default>; + clock-frequency =3D <100000>; + bootph-all; +}; + +&main_i2c2 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c2_pins_default>; + clock-frequency =3D <400000>; +}; + +&sdhci1 { + /* SD/MMC */ + status =3D "okay"; + vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vddshv_sdio>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mmc1_pins_default>; + disable-wp; +}; + +&main_gpio0 { + status =3D "okay"; +}; + +&main_gpio1 { + status =3D "okay"; +}; + +&main_gpio_intr { + status =3D "okay"; +}; + +&main_uart0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart0_pins_default>; + interrupts-extended =3D <&gic500 GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <&main_pmx0 0x1c8>; /* (D14) UART0_RXD PADCONFIG114 */ + interrupt-names =3D "irq", "wakeup"; +}; + +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status =3D "reserved"; +}; + +&usb0 { + usb-role-switch; + + port { + usb0_hs_ep: endpoint { + remote-endpoint =3D <&usb_con_hs>; + }; + }; +}; + +&mailbox0_cluster0 { + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region &wkup_r5fss0_core= 0_memory_region>; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster2 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region &mcu_r5fss0_core0_= memory_region>; +}; + +&c7x_0 { + mboxes =3D <&mailbox0_cluster1 &mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region &c7x_0_memory_region>; + status =3D "okay"; +}; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status =3D "reserved"; +}; + +×ync_router { + /* Use Time Sync Router to map GENF1 input to HW3_TS_PUSH output */ + mux-reg-masks-state =3D < + /* pps [cpsw cpts genf1] in17 -> out12 [cpsw cpts hw3_push] */ + K3_TS_OFFSET(12, 0x0001ffff, 17) + >; + status =3D "okay"; +}; --=20 2.34.1