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Wed, 30 Apr 2025 13:41:33 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:c5ac:bf15:f358:81a8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca56d5sm18098132f8f.32.2025.04.30.13.41.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 13:41:32 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 13/15] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation Date: Wed, 30 Apr 2025 21:41:10 +0100 Message-ID: <20250430204112.342123-14-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250430204112.342123-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250430204112.342123-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in `rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate supported display modes. On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as possible. To ensure compatibility with both RZ/G2L and RZ/V2H(P) SoCs, function pointers are introduced. Modify `rzg2l_mipi_dsi_startup()` to use `dphy_conf_clks` for clock configuration and `rzg2l_mipi_dsi_bridge_mode_valid()` to invoke `dphy_mode_clk_check` for mode validation. This change ensures proper operation across different SoC variants by allowing fine-grained control over clock configuration and mode validation. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v3->v4: - Replaced KILO with MILLI v2->v3: - Replaced unsigned long long with u64 v1->v2: - No changes --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 59 +++++++++++++------ 1 file changed, 42 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 66eef39af35e..df43ff59e08e 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -37,6 +37,10 @@ struct rzg2l_mipi_dsi_hw_info { int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); void (*dphy_late_init)(struct rzg2l_mipi_dsi *dsi); void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); + int (*dphy_conf_clks)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq, + u64 *hsfreq_millihz); + unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi, + unsigned long mode_freq); u32 phy_reg_offset; u32 link_reg_offset; unsigned long max_dclk; @@ -276,12 +280,36 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mip= i_dsi *dsi) reset_control_assert(dsi->rstc); } =20 +static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long = mode_freq, + u64 *hsfreq_millihz) +{ + unsigned long vclk_rate; + unsigned int bpp; + + clk_set_rate(dsi->vclk, mode_freq * MILLI); + /* + * Relationship between hsclk and vclk must follow + * vclk * bpp =3D hsclk * 8 * lanes + * where vclk: video clock (Hz) + * bpp: video pixel bit depth + * hsclk: DSI HS Byte clock frequency (Hz) + * lanes: number of data lanes + * + * hsclk(bit) =3D hsclk(byte) * 8 =3D hsfreq + */ + bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); + vclk_rate =3D clk_get_rate(dsi->vclk); + *hsfreq_millihz =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MI= LLI), + dsi->lanes); + + return 0; +} + static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, const struct drm_display_mode *mode) { - unsigned long hsfreq, vclk_rate; + unsigned long hsfreq; u64 hsfreq_millihz; - unsigned int bpp; u32 txsetr; u32 clstptsetr; u32 lptrnstsetr; @@ -295,21 +323,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_ds= i *dsi, if (ret < 0) return ret; =20 - clk_set_rate(dsi->vclk, mode->clock * MILLI); - - /* - * Relationship between hsclk and vclk must follow - * vclk * bpp =3D hsclk * 8 * lanes - * where vclk: video clock (Hz) - * bpp: video pixel bit depth - * hsclk: DSI HS Byte clock frequency (Hz) - * lanes: number of data lanes - * - * hsclk(bit) =3D hsclk(byte) * 8 =3D hsfreq - */ - bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); - vclk_rate =3D clk_get_rate(dsi->vclk); - hsfreq_millihz =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MIL= LI), dsi->lanes); + ret =3D dsi->info->dphy_conf_clks(dsi, mode->clock, &hsfreq_millihz); + if (ret < 0) + goto err_phy; =20 ret =3D dsi->info->dphy_init(dsi, hsfreq_millihz); if (ret < 0) @@ -616,6 +632,14 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *br= idge, if (mode->clock < dsi->info->min_dclk) return MODE_CLOCK_LOW; =20 + if (dsi->info->dphy_mode_clk_check) { + enum drm_mode_status status; + + status =3D dsi->info->dphy_mode_clk_check(dsi, mode->clock); + if (status !=3D MODE_OK) + return status; + } + return MODE_OK; } =20 @@ -835,6 +859,7 @@ static void rzg2l_mipi_dsi_remove(struct platform_devic= e *pdev) static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info =3D { .dphy_init =3D rzg2l_mipi_dsi_dphy_init, .dphy_exit =3D rzg2l_mipi_dsi_dphy_exit, + .dphy_conf_clks =3D rzg2l_dphy_conf_clks, .link_reg_offset =3D 0x10000, .max_dclk =3D 148500, .min_dclk =3D 5803, --=20 2.49.0