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Wed, 30 Apr 2025 13:41:29 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:c5ac:bf15:f358:81a8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca56d5sm18098132f8f.32.2025.04.30.13.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 13:41:28 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 10/15] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations Date: Wed, 30 Apr 2025 21:41:07 +0100 Message-ID: <20250430204112.342123-11-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250430204112.342123-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250430204112.342123-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve precision, especially for the RZ/V2H(P) SoC, where PLL dividers require high accuracy. These changes prepare the driver for upcoming RZ/V2H(P) SoC support. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v3->v4: - Used MILLI instead of KILO - Made use of mul_u32_u32() for multiplication v2->v3: - Replaced `unsigned long long` with `u64` - Replaced *_mhz with *_millihz` in functions v1->v2: - No changes --- --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index ed259627f5e8..a4c0dbae4a46 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -33,7 +33,7 @@ struct rzg2l_mipi_dsi; =20 struct rzg2l_mipi_dsi_hw_info { - int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq); + int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); u32 phy_reg_offset; u32 link_reg_offset; @@ -203,8 +203,9 @@ static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_d= si *dsi, u32 reg) */ =20 static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, - unsigned long hsfreq) + u64 hsfreq_millihz) { + unsigned long hsfreq =3D DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI); const struct rzg2l_mipi_dsi_timings *dphy_timings; unsigned int i; u32 dphyctrl0; @@ -277,6 +278,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, const struct drm_display_mode *mode) { unsigned long hsfreq, vclk_rate; + u64 hsfreq_millihz; unsigned int bpp; u32 txsetr; u32 clstptsetr; @@ -305,9 +307,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, */ bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); vclk_rate =3D clk_get_rate(dsi->vclk); - hsfreq =3D DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); + hsfreq_millihz =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MIL= LI), dsi->lanes); =20 - ret =3D dsi->info->dphy_init(dsi, hsfreq); + ret =3D dsi->info->dphy_init(dsi, hsfreq_millihz); if (ret < 0) goto err_phy; =20 @@ -315,6 +317,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, txsetr =3D TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN; rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr); =20 + hsfreq =3D DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI); /* * Global timings characteristic depends on high speed Clock Frequency * Currently MIPI DSI-IF just supports maximum FHD@60 with: @@ -778,7 +781,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device = *pdev) * mode->clock and format are not available. So initialize DPHY with * timing parameters for 80Mbps. */ - ret =3D dsi->info->dphy_init(dsi, 80000000); + ret =3D dsi->info->dphy_init(dsi, 80000000ULL * MILLI); if (ret < 0) goto err_phy; =20 --=20 2.49.0