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([82.78.167.166]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6ed6af86sm909390366b.133.2025.04.30.03.33.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 03:33:12 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, saravanak@google.com, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 6/8] arm64: dts: renesas: r9a08g045s33: Add PCIe node Date: Wed, 30 Apr 2025 13:32:34 +0300 Message-ID: <20250430103236.3511989-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430103236.3511989-1-claudiu.beznea.uj@bp.renesas.com> References: <20250430103236.3511989-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The RZ/G3S SoC has a variant (R9A08G045S33) which support PCIe. Add the PCIe node. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi b/arch/arm64/boo= t/dts/renesas/r9a08g045s33.dtsi index 3351f26c7a2a..d8e1dc80e56e 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi @@ -12,3 +12,73 @@ / { compatible =3D "renesas,r9a08g045s33", "renesas,r9a08g045"; }; + +&soc { + pcie: pcie@11e40000 { + compatible =3D "renesas,r9a08g045s33-pcie"; + reg =3D <0 0x11e40000 0 0x10000>; + ranges =3D <0x03000000 0 0x30000000 0 0x30000000 0 0x8000000>; + dma-ranges =3D <0x42000000 0 0x48000000 0 0x48000000 0 0x38000000>; + bus-range =3D <0x0 0xff>; + clocks =3D <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names =3D "aclk", "clkl1pm"; + resets =3D <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names =3D "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "int_serr", "int_serr_cor", "int_serr_nonfatal", + "int_serr_fatal", "axi_err_int", "inta_rc", + "intb_rc", "intc_rc", "intd_rc", + "intmsi_rc", "int_link_bandwidth", "int_pm_pme", + "dma_int", "pcie_evt_int", "msg_int", + "int_all"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intx 0>, /* INT A */ + <0 0 0 2 &pcie_intx 1>, /* INT B */ + <0 0 0 3 &pcie_intx 2>, /* INT C */ + <0 0 0 4 &pcie_intx 3>; /* INT D */ + device_type =3D "pci"; + num-lanes =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + power-domains =3D <&cpg>; + renesas,sysc =3D <&sysc>; + vendor-id =3D <0x1912>; + device-id =3D <0x0033>; + status =3D "disabled"; + + pcie_intx: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; + }; +}; --=20 2.43.0