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([82.78.167.166]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6ed6af86sm909390366b.133.2025.04.30.03.33.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 03:33:07 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, saravanak@google.com, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 4/8] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S Date: Wed, 30 Apr 2025 13:32:32 +0300 Message-ID: <20250430103236.3511989-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430103236.3511989-1-claudiu.beznea.uj@bp.renesas.com> References: <20250430103236.3511989-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express Base Specification 4.0. It is designed for root complex applications and features a single-lane (x1) implementation. Add documentation for it. The interrupts, interrupt-names, resets, reset-names, clocks, clock-names description were obtained from the hardware manual. Signed-off-by: Claudiu Beznea --- .../pci/renesas,r9a08g045s33-pcie.yaml | 242 ++++++++++++++++++ 1 file changed, 242 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/renesas,r9a08g045= s33-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pci= e.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.ya= ml new file mode 100644 index 000000000000..354f9c3be139 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,r9a08g045s33-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3S PCIe host controller + +maintainers: + - Claudiu Beznea + +description: + Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification + 4.0 and supports up to 5 GT/s (Gen2). + +properties: + compatible: + const: renesas,r9a08g045s33-pcie # RZ/G3S + + reg: + maxItems: 1 + + interrupts: + items: + - description: System error interrupt + - description: System error on correctable error interrupt + - description: System error on non-fatal error interrupt + - description: System error on fatal error interrupt + - description: AXI error interrupt + - description: INTA interrupt + - description: INTB interrupt + - description: INTC interrupt + - description: INTD interrupt + - description: MSI interrupt + - description: Link bandwidth interrupt + - description: PME interrupt + - description: DMA interrupt + - description: PCIe event interrupt + - description: Message interrupt + - description: All interrupts + + interrupt-names: + items: + - description: int_serr + - description: int_ser_cor + - description: int_serr_nonfatal + - description: int_serr_fatal + - description: axi_err_int + - description: inta_rc + - description: intb_rc + - description: intc_rc + - description: intd_rc + - description: intmsi_rc + - description: int_link_bandwidth + - description: int_pm_pme + - description: dma_int + - description: pcie_evt_int + - description: msg_int + - description: int_all + + clocks: + items: + - description: System clock + - description: PM control clock + + clock-names: + items: + - description: aclk + - description: clkl1pm + + resets: + items: + - description: AXI2PCIe Bridge reset + - description: Data link layer/transaction layer reset + - description: Transaction layer (ACLK domain) reset + - description: Transaction layer (PCLK domain) reset + - description: Physical layer reset + - description: Configuration register reset + - description: Configuration register reset + + reset-names: + items: + - description: aresetn + - description: rst_b + - description: rst_gp_b + - description: rst_ps_b + - description: rst_rsm_b + - description: rst_cfg_b + - description: rst_load_b + + power-domains: + maxItems: 1 + + dma-ranges: + description: + A single range for the inbound memory region. + maxItems: 1 + + renesas,sysc: + description: System controller phandle + $ref: /schemas/types.yaml#/definitions/phandle + + vendor-id: + const: 0x1912 + + device-id: + const: 0x0033 + + legacy-interrupt-controller: + description: Interrupt controller node for handling legacy PCI interru= pts + type: object + + properties: + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-controller: true + + interrupts: + items: + - description: INTA interrupt + - description: INTB interrupt + - description: INTC interrupt + - description: INTD interrupt + + required: + - "#address-cells" + - "#interrupt-cells" + - interrupt-controller + - interrupts + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - resets + - reset-names + - interrupts + - interrupt-names + - interrupt-map + - interrupt-map-mask + - power-domains + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - renesas,sysc + - vendor-id + - device-id + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + gic: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + pcie@11e40000 { + compatible =3D "renesas,r9a08g045s33-pcie"; + reg =3D <0 0x11e40000 0 0x10000>; + ranges =3D <0x03000000 0 0x30000000 0 0x30000000 0 0x8000000>; + dma-ranges =3D <0x42000000 0 0x48000000 0 0x48000000 0 0x80000= 00>; + bus-range =3D <0x0 0xff>; + clocks =3D <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names =3D "aclk", "clkl1pm"; + resets =3D <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names =3D "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "int_serr", "int_serr_cor", "int_serr_nonf= atal", + "int_serr_fatal", "axi_err_int", "inta_rc", + "intb_rc", "intc_rc", "intd_rc", + "intmsi_rc", "int_link_bandwidth", "int_pm_p= me", + "dma_int", "pcie_evt_int", "msg_int", + "int_all"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intx 0>, /* INT A */ + <0 0 0 2 &pcie_intx 1>, /* INT B */ + <0 0 0 3 &pcie_intx 2>, /* INT C */ + <0 0 0 4 &pcie_intx 3>; /* INT D */ + device_type =3D "pci"; + num-lanes =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + power-domains =3D <&cpg>; + renesas,sysc =3D <&sysc>; + vendor-id =3D <0x1912>; + device-id =3D <0x0033>; + + pcie_intx: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; + }; + }; + +... --=20 2.43.0