From nobody Sun Feb 8 07:07:16 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC417239082 for ; Wed, 30 Apr 2025 10:11:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007905; cv=none; b=mYbyj8zumdbReO2MTlDJRAKgP1B5Tkzdtn9y4etK0owT0uf5vxMjgIeWijgh3QkmK/bM4txTDkOSVMvKliZd2ScPBYEuefcEW3s5sgNLaIUtfRz8kHtZeQP6Wu+LR/hOQO0FC9yW4QuQ10+06CYviGur7SQUcRoYdM3f5vDN2zY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007905; c=relaxed/simple; bh=es5WtintKzim6+TJ9y2jeS+EHUpABz8zi35WxuN50N0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uyFm/leac6bMJJhNcrpw3iW5jM5D6pgsHhyBHQzh0tzXhTgtrOGCHdiruAfwgqhzdqS+AcdFU6lgK99SNlSk43yYiDbXsve7qeL5a2hMgbWyFL0KfV0XWg9GdY7tWVIi2iecZ7sVNVhCeLiTbSHIyiKCrIuqV7bsUeAS1FM1JAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=IF1me1Vv; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="IF1me1Vv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1746007903; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JM6eS1aq9/ITzi+UPUfeAHGUGQf2zr8846YAw9k0J2A=; b=IF1me1VvtXxrHoXt/qvuNeHwvtKRus0vxgxXam6twi79KvtaH2azGK0CDylBInUsSrDxol UbYOt7cvivay2xwDGVonhQu6Zd7QT1R8A/pk2N/Jv9xjeYDSnRPY/MfEC3zbKDBcaHhR7G o4T4y5JeKXmrYFokmwrGBPIlv99QNr4= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-168--rBw8kV7NuajxUPnOuDl8g-1; Wed, 30 Apr 2025 06:11:40 -0400 X-MC-Unique: -rBw8kV7NuajxUPnOuDl8g-1 X-Mimecast-MFC-AGG-ID: -rBw8kV7NuajxUPnOuDl8g_1746007898 Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 2F8ED1801A02; Wed, 30 Apr 2025 10:11:38 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.44.33.50]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id EB65819560B7; Wed, 30 Apr 2025 10:11:32 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Krzysztof Kozlowski , Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prathosh Satish , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Simon Horman , Lee Jones , Andy Shevchenko , Michal Schmidt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH net-next v6 1/8] dt-bindings: dpll: Add DPLL device and pin Date: Wed, 30 Apr 2025 12:11:19 +0200 Message-ID: <20250430101126.83708-2-ivecera@redhat.com> In-Reply-To: <20250430101126.83708-1-ivecera@redhat.com> References: <20250430101126.83708-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" Add a common DT schema for DPLL device and its associated pins. The DPLL (device phase-locked loop) is a device used for precise clock synchronization in networking and telecom hardware. The device includes one or more DPLLs (channels) and one or more physical input/output pins. Each DPLL channel is used either to provide a pulse-per-clock signal or to drive an Ethernet equipment clock. The input and output pins have the following properties: * label: specifies board label * connection type: specifies its usage depending on wiring * list of supported or allowed frequencies: depending on how the pin is connected and where) * embedded sync capability: indicates whether the pin supports this Reviewed-by: Krzysztof Kozlowski Signed-off-by: Ivan Vecera --- v5->v6: * no change v4->v5: * removed compilation output from the description v3->v4: * dropped $Ref from dpll-pin reg property * added maxItems to dpll-pin reg property * fixed paragraph in dpll-pin desc * dpll-pin type property renamed to connection-type v1->v3: * rewritten description for both device and pin * dropped num-dplls property * supported-frequencies property renamed to supported-frequencies-hz --- .../devicetree/bindings/dpll/dpll-device.yaml | 76 +++++++++++++++++++ .../devicetree/bindings/dpll/dpll-pin.yaml | 45 +++++++++++ MAINTAINERS | 2 + 3 files changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/dpll/dpll-device.yaml create mode 100644 Documentation/devicetree/bindings/dpll/dpll-pin.yaml diff --git a/Documentation/devicetree/bindings/dpll/dpll-device.yaml b/Docu= mentation/devicetree/bindings/dpll/dpll-device.yaml new file mode 100644 index 000000000000..fb8d7a9a3693 --- /dev/null +++ b/Documentation/devicetree/bindings/dpll/dpll-device.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dpll/dpll-device.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Digital Phase-Locked Loop (DPLL) Device + +maintainers: + - Ivan Vecera + +description: + Digital Phase-Locked Loop (DPLL) device is used for precise clock + synchronization in networking and telecom hardware. The device can + have one or more channels (DPLLs) and one or more physical input and + output pins. Each DPLL channel can either produce pulse-per-clock signal + or drive ethernet equipment clock. The type of each channel can be + indicated by dpll-types property. + +properties: + $nodename: + pattern: "^dpll(@.*)?$" + + "#address-cells": + const: 0 + + "#size-cells": + const: 0 + + dpll-types: + description: List of DPLL channel types, one per DPLL instance. + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + items: + enum: [pps, eec] + + input-pins: + type: object + description: DPLL input pins + unevaluatedProperties: false + + properties: + "#address-cells": + const: 1 + "#size-cells": + const: 0 + + patternProperties: + "^pin@[0-9a-f]+$": + $ref: /schemas/dpll/dpll-pin.yaml + unevaluatedProperties: false + + required: + - "#address-cells" + - "#size-cells" + + output-pins: + type: object + description: DPLL output pins + unevaluatedProperties: false + + properties: + "#address-cells": + const: 1 + "#size-cells": + const: 0 + + patternProperties: + "^pin@[0-9]+$": + $ref: /schemas/dpll/dpll-pin.yaml + unevaluatedProperties: false + + required: + - "#address-cells" + - "#size-cells" + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/dpll/dpll-pin.yaml b/Documen= tation/devicetree/bindings/dpll/dpll-pin.yaml new file mode 100644 index 000000000000..51db93b77306 --- /dev/null +++ b/Documentation/devicetree/bindings/dpll/dpll-pin.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dpll/dpll-pin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DPLL Pin + +maintainers: + - Ivan Vecera + +description: | + The DPLL pin is either a physical input or output pin that is provided + by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by + its physical order number that is stored in reg property and can have + an additional set of properties like supported (allowed) frequencies, + label, type and may support embedded sync. + + Note that the pin in this context has nothing to do with pinctrl. + +properties: + reg: + description: Hardware index of the DPLL pin. + maxItems: 1 + + connection-type: + description: Connection type of the pin + $ref: /schemas/types.yaml#/definitions/string + enum: [ext, gnss, int, mux, synce] + + esync-control: + description: Indicates whether the pin supports embedded sync function= ality. + type: boolean + + label: + description: String exposed as the pin board label + $ref: /schemas/types.yaml#/definitions/string + + supported-frequencies-hz: + description: List of supported frequencies for this pin, expressed in = Hz. + +required: + - reg + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index a7545b5abef9..1477fbda7378 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7195,6 +7195,8 @@ M: Arkadiusz Kubalewski M: Jiri Pirko L: netdev@vger.kernel.org S: Supported +F: Documentation/devicetree/bindings/dpll/dpll-device.yaml +F: Documentation/devicetree/bindings/dpll/dpll-pin.yaml F: Documentation/driver-api/dpll.rst F: drivers/dpll/* F: include/linux/dpll.h --=20 2.49.0 From nobody Sun Feb 8 07:07:16 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5947E248F48 for ; Wed, 30 Apr 2025 10:11:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007914; cv=none; b=Jc8T18F6AYMg93BnbKdiM+jqv0jykvaWorZken6l6JvpA0nVKQ1GjAvfCkX2jMsLJ+yZ8xfJQv17pAMMlKLvczLdpZ2TcttaAIoKv42h0D9uuMV+gGxtIRhsMYR9Cz/dbGQK/LYSMwUc1ja7hVDOEQsCzvx//t4zNtLaooAjRVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007914; c=relaxed/simple; bh=XTu13HUCjnLkPwxQ/H/XKaYBowvWqvHhZOqLV5oeU6k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kj3hbDhPPa/X4UjL2/ZAZCDmsKBVUMF4tiy8AUqwubtRpkO9RusB/iuArCmhT58a4OINMqNxp0DMzhmvZRSLDyVNTbVfqYwgvcef1IYeTgJFVv6Y0xU9KARpcnisRvEwkTDMjWrsIBVK9M3csaWmk9QOE1ihT5RuFcXKHZH1KUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=HvVcdxpP; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="HvVcdxpP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1746007911; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TD0tIUhPEy546OOelRb04g6ZuNomWXeXg1LQ3RsW7ok=; b=HvVcdxpPaBSZPG8+DOyaH5wjJokpmHf9KGVHZCCYoOgTMFnQKGljmWTzIBSU+yWedJLX9a 5Xk4m9CCFZAhMUQBZSLzfjkJk97im2udXAMlY7/uxuGzygw5GcRpQBMPX7rq32tIGPP4B5 Zo0zVsYN+rMpHtn5W3P/sAlYgKJHRUE= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-97-k6yLF-1dPFi5TPE4fMQZLQ-1; Wed, 30 Apr 2025 06:11:46 -0400 X-MC-Unique: k6yLF-1dPFi5TPE4fMQZLQ-1 X-Mimecast-MFC-AGG-ID: k6yLF-1dPFi5TPE4fMQZLQ_1746007904 Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id AE0601800264; Wed, 30 Apr 2025 10:11:43 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.44.33.50]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 9514E1956094; Wed, 30 Apr 2025 10:11:38 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Krzysztof Kozlowski , Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prathosh Satish , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Simon Horman , Lee Jones , Andy Shevchenko , Michal Schmidt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH net-next v6 2/8] dt-bindings: dpll: Add support for Microchip Azurite chip family Date: Wed, 30 Apr 2025 12:11:20 +0200 Message-ID: <20250430101126.83708-3-ivecera@redhat.com> In-Reply-To: <20250430101126.83708-1-ivecera@redhat.com> References: <20250430101126.83708-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" Add DT bindings for Microchip Azurite DPLL chip family. These chips provide up to 5 independent DPLL channels, 10 differential or single-ended inputs and 10 differential or 20 single-ended outputs. They can be connected via I2C or SPI busses. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Ivan Vecera --- v5->v6: * no change v4->v5: * removed compilation output from the description v3->v4: * fixed $Id * dpll-pin type property renamed to connection type v1->v3: * single file for both i2c & spi * 5 compatibles for all supported chips from the family --- .../bindings/dpll/microchip,zl30731.yaml | 115 ++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/dpll/microchip,zl3073= 1.yaml diff --git a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml = b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml new file mode 100644 index 000000000000..17747f754b84 --- /dev/null +++ b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Azurite DPLL device + +maintainers: + - Ivan Vecera + +description: + Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that + provides up to 5 independent DPLL channels, up to 10 differential or + single-ended inputs and 10 differential or 20 single-ended outputs. + These devices support both I2C and SPI interfaces. + +properties: + compatible: + enum: + - microchip,zl30731 + - microchip,zl30732 + - microchip,zl30733 + - microchip,zl30734 + - microchip,zl30735 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/dpll/dpll-device.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpll@70 { + compatible =3D "microchip,zl30732"; + reg =3D <0x70>; + dpll-types =3D "pps", "eec"; + + input-pins { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pin@0 { /* REF0P */ + reg =3D <0>; + connection-type =3D "ext"; + label =3D "Input 0"; + supported-frequencies-hz =3D /bits/ 64 <1 1000>; + }; + }; + + output-pins { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pin@3 { /* OUT1N */ + reg =3D <3>; + connection-type =3D "gnss"; + esync-control; + label =3D "Output 1"; + supported-frequencies-hz =3D /bits/ 64 <1 10000>; + }; + }; + }; + }; + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpll@70 { + compatible =3D "microchip,zl30731"; + reg =3D <0x70>; + spi-max-frequency =3D <12500000>; + + dpll-types =3D "pps"; + + input-pins { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pin@0 { /* REF0P */ + reg =3D <0>; + connection-type =3D "ext"; + label =3D "Input 0"; + supported-frequencies-hz =3D /bits/ 64 <1 1000>; + }; + }; + + output-pins { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pin@3 { /* OUT1N */ + reg =3D <3>; + connection-type =3D "gnss"; + esync-control; + label =3D "Output 1"; + supported-frequencies-hz =3D /bits/ 64 <1 10000>; + }; + }; + }; + }; +... --=20 2.49.0 From nobody Sun Feb 8 07:07:16 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C01ED248F67 for ; Wed, 30 Apr 2025 10:11:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007917; cv=none; b=sB2XV76DOQ69P/XV4wsMADBgXNK7roeUZqSRbtJ0GvZwelHLZNk/qdHk6Y1Cs2AtFYg+JnX0+jHsK6sUaXfGqSapPPO6yYoPUc5n0bPEwWmd2DyLVfczp5aVa32mIYqbdzvznoVwhIYWtD8V1V6/mTW+WCX2ujJ7ai0eOtidGSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007917; c=relaxed/simple; bh=5Hh5crfrd3Llgx+B040gzsUAjGkgpywj/V6UMnjwhs4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hhydlYUunjThsWEgY9XeyzL6kccXYL2K1VrYbvMrvEF9n2wMnZhKozis2O0L2jFavAX22+mIlgr6qyhXB4C9N6E+6pM5j2s8pXMq/1yw2W/r3YJwHq9cJVwFCHIeRFZU+NdvyCJO3L43lkiwUMnnt+KjcoAWFI2iXhOrRSMGGdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=dd6KfV8/; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="dd6KfV8/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1746007913; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4EkA0hadeV6TFvtRwZktHqVqQAI8ITM55RxyBejgVHo=; b=dd6KfV8/WLsbYEvtT1BoL6ryTVuuzfr3nOSSIzZ+1blFRh/6HRKPU+nJ3aKGCCwjA2fZct 9JPZ1eDnXEf58vWSdGnFhkXyc8pgz+Uc50fkAmc1iB6jCu9JBDcmFD0bdnhBrTGo6dxG2I ECzwVPrzjpEgzX+ztTM37LnlIpbQ53Q= Received: from mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-532-hp8saPVrPOqxgpk_dlYmug-1; Wed, 30 Apr 2025 06:11:51 -0400 X-MC-Unique: hp8saPVrPOqxgpk_dlYmug-1 X-Mimecast-MFC-AGG-ID: hp8saPVrPOqxgpk_dlYmug_1746007909 Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 323F31956086; Wed, 30 Apr 2025 10:11:49 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.44.33.50]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 1F6321955F24; Wed, 30 Apr 2025 10:11:43 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prathosh Satish , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Simon Horman , Lee Jones , Andy Shevchenko , Michal Schmidt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH net-next v6 3/8] mfd: Add Microchip ZL3073x support Date: Wed, 30 Apr 2025 12:11:21 +0200 Message-ID: <20250430101126.83708-4-ivecera@redhat.com> In-Reply-To: <20250430101126.83708-1-ivecera@redhat.com> References: <20250430101126.83708-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" Add base MFD driver for Microchip Azurite ZL3073x chip family. These chips provide DPLL and PHC (PTP) functionality and can be connected over I2C or SPI bus. The MFD driver handles basic communication and synchronization over the bus, as well as common functionality that are used by the DPLL driver (part 2) and by the PTP driver (to be added later). The chip family has the following characteristics: * up to 5 separate DPLL units (channels) * 5 synthesizers * 10 input pins (references) * 10 outputs * 20 output pins (output pin pair shares one output) * Each reference and output can operate in either differential or single-ended mode (differential mode uses 2 pins) * Each output is connected to one of the synthesizers * Each synthesizer is driven by one of the DPLL unit The device uses 7-bit addresses and 8-bits values. It exposes 8-, 16-, 32- and 48-bits registers in address range <0x000,0x77F>. Due to 7bit addressing, the range is organized into pages of 128 bytes, with each page containing a page selector register at address 0x7F. For reading/writing multi-byte registers, the device supports bulk transfers. Signed-off-by: Ivan Vecera --- v5->v6: * fixed condition for writing 48bit register value v4->v5: * added type-safe register access functions * register definition macros moved to include/linux/mfd/zl3073x-regs.h * register definition used only by MFD moved to drivers/mfd/zl3073x-regs.h v3->v4: * zl3073x_regs.h moved to drivers/mfd/ * maple as regcache * added and used general helper to read 16bit registers * removed mailbox mutex for now * removed parentheses in zl3073x_is_volatile_reg() * used dev_err_probe() in probe path * dropped inclusion * dropped unneccessary i2c_set_clientdata() and spi_set_drvdata() v2->v3: * added chip_info with valid chip ids and num of DPLLs for compatibles * regmap is using implicit locking * mailbox registers requires extra mutex to be held * added helpers to access registers * report device firmware and config version using dev_dbg * fixed regmap ranges * enabled rbtree regcache for page selector v1->v2: * fixed header issues * removed usage of of_match_ptr * added check for devm_mutex_init * removed commas after sentinels * removed variable initialization in zl3073x_i2c_probe() * moved device tables closer to their users * renamed zl3073x_dev_alloc() to zl3073x_devm_alloc() * removed empty zl3073x_dev_exit() * spidev renamed to spi * squashed together with device DT bindings * used dev_err_probe() instead of dev_err() during probe * added some function documentation DT bindings: * spliced to separate files for i2c and spi * fixed property order in DT bindings' examples * added description --- MAINTAINERS | 9 + drivers/mfd/Kconfig | 30 ++ drivers/mfd/Makefile | 5 + drivers/mfd/zl3073x-core.c | 472 +++++++++++++++++++++++++++++++ drivers/mfd/zl3073x-i2c.c | 66 +++++ drivers/mfd/zl3073x-regs.h | 17 ++ drivers/mfd/zl3073x-spi.c | 66 +++++ drivers/mfd/zl3073x.h | 31 ++ include/linux/mfd/zl3073x-regs.h | 66 +++++ include/linux/mfd/zl3073x.h | 35 +++ 10 files changed, 797 insertions(+) create mode 100644 drivers/mfd/zl3073x-core.c create mode 100644 drivers/mfd/zl3073x-i2c.c create mode 100644 drivers/mfd/zl3073x-regs.h create mode 100644 drivers/mfd/zl3073x-spi.c create mode 100644 drivers/mfd/zl3073x.h create mode 100644 include/linux/mfd/zl3073x-regs.h create mode 100644 include/linux/mfd/zl3073x.h diff --git a/MAINTAINERS b/MAINTAINERS index 1477fbda7378..0c34f28cba0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16052,6 +16052,15 @@ L: linux-wireless@vger.kernel.org S: Supported F: drivers/net/wireless/microchip/ =20 +MICROCHIP ZL3073X DRIVER +M: Ivan Vecera +M: Prathosh Satish +L: netdev@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml +F: drivers/mfd/zl3073x* +F: include/linux/mfd/zl3073x.h + MICROSEMI MIPS SOCS M: Alexandre Belloni M: UNGLinuxDriver@microchip.com diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 22b936310039..7d7902ec1d89 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2422,5 +2422,35 @@ config MFD_UPBOARD_FPGA To compile this driver as a module, choose M here: the module will be called upboard-fpga. =20 +config MFD_ZL3073X_CORE + tristate + select MFD_CORE + +config MFD_ZL3073X_I2C + tristate "Microchip Azurite DPLL/PTP/SyncE with I2C" + depends on I2C + select MFD_ZL3073X_CORE + select REGMAP_I2C + help + Say Y here if you want to build I2C support for the Microchip + Azurite DPLL/PTP/SyncE chip family. + + To compile this driver as a module, choose M here: the module + will be called zl3073x_i2c and you will also get zl3073x for + the core module. + +config MFD_ZL3073X_SPI + tristate "Microchip Azurite DPLL/PTP/SyncE with SPI" + depends on SPI + select MFD_ZL3073X_CORE + select REGMAP_SPI + help + Say Y here if you want to build SPI support for the Microchip + Azurite DPLL/PTP/SyncE chip family. + + To compile this driver as a module, choose M here: the module + will be called zl3073x_spi and you will also get zl3073x for + the core module. + endmenu endif diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 948cbdf42a18..76e2babc1538 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -290,3 +290,8 @@ obj-$(CONFIG_MFD_RSMU_I2C) +=3D rsmu_i2c.o rsmu_core.o obj-$(CONFIG_MFD_RSMU_SPI) +=3D rsmu_spi.o rsmu_core.o =20 obj-$(CONFIG_MFD_UPBOARD_FPGA) +=3D upboard-fpga.o + +zl3073x-y :=3D zl3073x-core.o +obj-$(CONFIG_MFD_ZL3073X_CORE) +=3D zl3073x.o +obj-$(CONFIG_MFD_ZL3073X_I2C) +=3D zl3073x-i2c.o +obj-$(CONFIG_MFD_ZL3073X_SPI) +=3D zl3073x-spi.o diff --git a/drivers/mfd/zl3073x-core.c b/drivers/mfd/zl3073x-core.c new file mode 100644 index 000000000000..c408aafb0f8a --- /dev/null +++ b/drivers/mfd/zl3073x-core.c @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "zl3073x.h" +#include "zl3073x-regs.h" + +/* Chip IDs for zl30731 */ +static const u16 zl30731_ids[] =3D { + 0x0E93, + 0x1E93, + 0x2E93, +}; + +/* Chip IDs for zl30732 */ +static const u16 zl30732_ids[] =3D { + 0x0E30, + 0x0E94, + 0x1E94, + 0x1F60, + 0x2E94, + 0x3FC4, +}; + +/* Chip IDs for zl30733 */ +static const u16 zl30733_ids[] =3D { + 0x0E95, + 0x1E95, + 0x2E95, +}; + +/* Chip IDs for zl30734 */ +static const u16 zl30734_ids[] =3D { + 0x0E96, + 0x1E96, + 0x2E96, +}; + +/* Chip IDs for zl30735 */ +static const u16 zl30735_ids[] =3D { + 0x0E97, + 0x1E97, + 0x2E97, +}; + +const struct zl3073x_chip_info zl3073x_chip_info[] =3D { + [ZL30731] =3D { + .ids =3D zl30731_ids, + .num_ids =3D ARRAY_SIZE(zl30731_ids), + .num_channels =3D 1, + }, + [ZL30732] =3D { + .ids =3D zl30732_ids, + .num_ids =3D ARRAY_SIZE(zl30732_ids), + .num_channels =3D 2, + }, + [ZL30733] =3D { + .ids =3D zl30733_ids, + .num_ids =3D ARRAY_SIZE(zl30733_ids), + .num_channels =3D 3, + }, + [ZL30734] =3D { + .ids =3D zl30734_ids, + .num_ids =3D ARRAY_SIZE(zl30734_ids), + .num_channels =3D 4, + }, + [ZL30735] =3D { + .ids =3D zl30735_ids, + .num_ids =3D ARRAY_SIZE(zl30735_ids), + .num_channels =3D 5, + }, +}; +EXPORT_SYMBOL_NS_GPL(zl3073x_chip_info, "ZL3073X"); + +#define ZL_RANGE_OFFSET 0x80 +#define ZL_PAGE_SIZE 0x80 +#define ZL_NUM_PAGES 15 +#define ZL_PAGE_SEL 0x7F +#define ZL_PAGE_SEL_MASK GENMASK(3, 0) +#define ZL_NUM_REGS (ZL_NUM_PAGES * ZL_PAGE_SIZE) + +/* Regmap range configuration */ +static const struct regmap_range_cfg zl3073x_regmap_range =3D { + .range_min =3D ZL_RANGE_OFFSET, + .range_max =3D ZL_RANGE_OFFSET + ZL_NUM_REGS - 1, + .selector_reg =3D ZL_PAGE_SEL, + .selector_mask =3D ZL_PAGE_SEL_MASK, + .selector_shift =3D 0, + .window_start =3D 0, + .window_len =3D ZL_PAGE_SIZE, +}; + +static bool +zl3073x_is_volatile_reg(struct device *dev __maybe_unused, unsigned int re= g) +{ + /* Only page selector is non-volatile */ + return reg !=3D ZL_PAGE_SEL; +} + +static const struct regmap_config zl3073x_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D ZL_RANGE_OFFSET + ZL_NUM_REGS - 1, + .ranges =3D &zl3073x_regmap_range, + .num_ranges =3D 1, + .cache_type =3D REGCACHE_MAPLE, + .volatile_reg =3D zl3073x_is_volatile_reg, +}; + +static bool +zl3073x_check_reg(struct zl3073x_dev *zldev, unsigned int reg, size_t size) +{ + /* Check the index is in valid range for indexed register */ + if (ZL_REG_OFFSET(reg) > ZL_REG_MAX_OFFSET(reg)) { + dev_err(zldev->dev, "Index out of range for reg 0x%04lx\n", + ZL_REG_ADDR(reg)); + return false; + } + /* Check the requested size corresponds to register size */ + if (ZL_REG_SIZE(reg) !=3D size) { + dev_err(zldev->dev, "Invalid size %zu for reg 0x%04lx\n", + size, ZL_REG_ADDR(reg)); + return false; + } + + return true; +} + +static int +zl3073x_read_reg(struct zl3073x_dev *zldev, unsigned int reg, void *val, + size_t size) +{ + int rc; + + if (!zl3073x_check_reg(zldev, reg, size)) + return -EINVAL; + + /* Map the register address to virtual range */ + reg =3D ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET; + + rc =3D regmap_bulk_read(zldev->regmap, reg, val, size); + if (rc) { + dev_err(zldev->dev, "Failed to read reg 0x%04x: %pe\n", reg, + ERR_PTR(rc)); + return rc; + } + + return 0; +} + +static int +zl3073x_write_reg(struct zl3073x_dev *zldev, unsigned int reg, const void = *val, + size_t size) +{ + int rc; + + if (!zl3073x_check_reg(zldev, reg, size)) + return -EINVAL; + + /* Map the register address to virtual range */ + reg =3D ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET; + + rc =3D regmap_bulk_write(zldev->regmap, reg, val, size); + if (rc) { + dev_err(zldev->dev, "Failed to write reg 0x%04x: %pe\n", reg, + ERR_PTR(rc)); + return rc; + } + + return 0; +} + +/** + * zl3073x_read_u8 - read value from 8bit register + * @zldev: zl3073x device pointer + * @reg: register to write to + * @val: value to write + * + * Reads value from given 8bit register. + * + * Returns: 0 on success, <0 on error + */ +int zl3073x_read_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 *val) +{ + return zl3073x_read_reg(zldev, reg, val, sizeof(*val)); +} +EXPORT_SYMBOL_NS_GPL(zl3073x_read_u8, "ZL3073X"); + +/** + * zl3073x_write_u8 - write value to 16bit register + * @zldev: zl3073x device pointer + * @reg: register to write to + * @val: value to write + * + * Writes value into given 8bit register. + * + * Returns: 0 on success, <0 on error + */ +int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val) +{ + return zl3073x_write_reg(zldev, reg, &val, sizeof(val)); +} +EXPORT_SYMBOL_NS_GPL(zl3073x_write_u8, "ZL3073X"); + +/** + * zl3073x_read_u16 - read value from 16bit register + * @zldev: zl3073x device pointer + * @reg: register to write to + * @val: value to write + * + * Reads value from given 16bit register. + * + * Returns: 0 on success, <0 on error + */ +int zl3073x_read_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 *val) +{ + int rc; + + rc =3D zl3073x_read_reg(zldev, reg, val, sizeof(*val)); + if (!rc) + be16_to_cpus(val); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(zl3073x_read_u16, "ZL3073X"); + +/** + * zl3073x_write_u16 - write value to 16bit register + * @zldev: zl3073x device pointer + * @reg: register to write to + * @val: value to write + * + * Writes value into given 16bit register. + * + * Returns: 0 on success, <0 on error + */ +int zl3073x_write_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 val) +{ + cpu_to_be16s(&val); + + return zl3073x_write_reg(zldev, reg, &val, sizeof(val)); +} +EXPORT_SYMBOL_NS_GPL(zl3073x_write_u16, "ZL3073X"); + +/** + * zl3073x_read_u32 - read value from 32bit register + * @zldev: zl3073x device pointer + * @reg: register to write to + * @val: value to write + * + * Reads value from given 32bit register. + * + * Returns: 0 on success, <0 on error + */ +int zl3073x_read_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 *val) +{ + int rc; + + rc =3D zl3073x_read_reg(zldev, reg, val, sizeof(*val)); + if (!rc) + be32_to_cpus(val); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(zl3073x_read_u32, "ZL3073X"); + +/** + * zl3073x_write_u32 - write value to 32bit register + * @zldev: zl3073x device pointer + * @reg: register to write to + * @val: value to write + * + * Writes value into given 32bit register. + * + * Returns: 0 on success, <0 on error + */ +int zl3073x_write_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 val) +{ + cpu_to_be32s(&val); + + return zl3073x_write_reg(zldev, reg, &val, sizeof(val)); +} +EXPORT_SYMBOL_NS_GPL(zl3073x_write_u32, "ZL3073X"); + +/** + * zl3073x_read_u48 - read value from 48bit register + * @zldev: zl3073x device pointer + * @reg: register to write to + * @val: value to write + * + * Reads value from given 48bit register. + * + * Returns: 0 on success, <0 on error + */ +int zl3073x_read_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 *val) +{ + u8 buf[6]; + int rc; + + rc =3D zl3073x_read_reg(zldev, reg, buf, sizeof(buf)); + if (!rc) + *val =3D get_unaligned_be48(buf); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(zl3073x_read_u48, "ZL3073X"); + +/** + * zl3073x_write_u48 - write value to 48bit register + * @zldev: zl3073x device pointer + * @reg: register to write to + * @val: value to write + * + * Writes value into given 48bit register. + * The value must be from the interval -S48_MIN to U48_MAX. + * + * Returns: 0 on success, <0 on error + */ +int zl3073x_write_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 val) +{ + u8 buf[6]; + + /* Check the value belongs to + * Any value >=3D S48_MIN has bits 47..63 set. + */ + if (val > GENMASK_ULL(47, 0) && val < GENMASK_ULL(63, 47)) { + dev_err(zldev->dev, "Value 0x%0llx out of range\n", val); + return -EINVAL; + } + + put_unaligned_be48(val, buf); + + return zl3073x_write_reg(zldev, reg, buf, sizeof(buf)); +} +EXPORT_SYMBOL_NS_GPL(zl3073x_write_u48, "ZL3073X"); + +/** + * zl3073x_poll_zero_u8 - wait for register to be cleared by device + * @zldev: zl3073x device pointer + * @reg: register to poll (has to be 8bit register) + * @mask: bit mask for polling + * + * Waits for bits specified by @mask in register @reg value to be cleared + * by the device. + * + * Returns: 0 on success, <0 on error + */ +int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 m= ask) +{ + /* Register polling sleep & timeout */ +#define ZL_POLL_SLEEP_US 10 +#define ZL_POLL_TIMEOUT_US 2000000 + unsigned int val; + + /* Check the register is 8bit */ + if (ZL_REG_SIZE(reg) !=3D 1) { + dev_err(zldev->dev, "Invalid reg 0x%04lx size for polling\n", + ZL_REG_ADDR(reg)); + return -EINVAL; + } + + /* Map the register address to virtual range */ + reg =3D ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET; + + return regmap_read_poll_timeout(zldev->regmap, reg, val, !(val & mask), + ZL_POLL_SLEEP_US, ZL_POLL_TIMEOUT_US); +} +EXPORT_SYMBOL_NS_GPL(zl3073x_poll_zero_u8, "ZL3073X"); + +/** + * zl3073x_devm_alloc - allocates zl3073x device structure + * @dev: pointer to device structure + * + * Allocates zl3073x device structure as device resource. + * + * Return: pointer to zl3073x device on success, error pointer on error + */ +struct zl3073x_dev *zl3073x_devm_alloc(struct device *dev) +{ + struct zl3073x_dev *zldev; + + zldev =3D devm_kzalloc(dev, sizeof(*zldev), GFP_KERNEL); + if (!zldev) + return ERR_PTR(-ENOMEM); + + zldev->dev =3D dev; + dev_set_drvdata(zldev->dev, zldev); + + return zldev; +} +EXPORT_SYMBOL_NS_GPL(zl3073x_devm_alloc, "ZL3073X"); + +/** + * zl3073x_dev_init_regmap_config - initialize regmap config + * @regmap_cfg: regmap_config structure to fill + * + * Initializes regmap config common for I2C and SPI. + */ +void zl3073x_dev_init_regmap_config(struct regmap_config *regmap_cfg) +{ + *regmap_cfg =3D zl3073x_regmap_config; +} +EXPORT_SYMBOL_NS_GPL(zl3073x_dev_init_regmap_config, "ZL3073X"); + +/** + * zl3073x_dev_probe - initialize zl3073x device + * @zldev: pointer to zl3073x device + * @chip_info: chip info based on compatible + * + * Common initialization of zl3073x device structure. + * + * Returns: 0 on success, <0 on error + */ +int zl3073x_dev_probe(struct zl3073x_dev *zldev, + const struct zl3073x_chip_info *chip_info) +{ + u16 id, revision, fw_ver; + unsigned int i; + u32 cfg_ver; + int rc; + + /* Read chip ID */ + rc =3D zl3073x_read_u16(zldev, ZL_REG_ID, &id); + if (rc) + return rc; + + /* Check it matches */ + for (i =3D 0; i < chip_info->num_ids; i++) { + if (id =3D=3D chip_info->ids[i]) + break; + } + + if (i =3D=3D chip_info->num_ids) { + return dev_err_probe(zldev->dev, -ENODEV, + "Unknown or non-match chip ID: 0x%0x\n", + id); + } + + /* Read revision, firmware version and custom config version */ + rc =3D zl3073x_read_u16(zldev, ZL_REG_REVISION, &revision); + if (rc) + return rc; + rc =3D zl3073x_read_u16(zldev, ZL_REG_FW_VER, &fw_ver); + if (rc) + return rc; + rc =3D zl3073x_read_u32(zldev, ZL_REG_CUSTOM_CONFIG_VER, &cfg_ver); + if (rc) + return rc; + + dev_dbg(zldev->dev, "ChipID(%X), ChipRev(%X), FwVer(%u)\n", id, + revision, fw_ver); + dev_dbg(zldev->dev, "Custom config version: %lu.%lu.%lu.%lu\n", + FIELD_GET(GENMASK(31, 24), cfg_ver), + FIELD_GET(GENMASK(23, 16), cfg_ver), + FIELD_GET(GENMASK(15, 8), cfg_ver), + FIELD_GET(GENMASK(7, 0), cfg_ver)); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(zl3073x_dev_probe, "ZL3073X"); + +MODULE_AUTHOR("Ivan Vecera "); +MODULE_DESCRIPTION("Microchip ZL3073x core driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/zl3073x-i2c.c b/drivers/mfd/zl3073x-i2c.c new file mode 100644 index 000000000000..da8bbd702d76 --- /dev/null +++ b/drivers/mfd/zl3073x-i2c.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include "zl3073x.h" + +static int zl3073x_i2c_probe(struct i2c_client *client) +{ + struct regmap_config regmap_cfg; + struct device *dev =3D &client->dev; + struct zl3073x_dev *zldev; + + zldev =3D zl3073x_devm_alloc(dev); + if (IS_ERR(zldev)) + return PTR_ERR(zldev); + + zl3073x_dev_init_regmap_config(®map_cfg); + + zldev->regmap =3D devm_regmap_init_i2c(client, ®map_cfg); + if (IS_ERR(zldev->regmap)) { + dev_err_probe(dev, PTR_ERR(zldev->regmap), + "Failed to initialize regmap\n"); + return PTR_ERR(zldev->regmap); + } + + return zl3073x_dev_probe(zldev, i2c_get_match_data(client)); +} + +static const struct i2c_device_id zl3073x_i2c_id[] =3D { + { "zl30731", .driver_data =3D (kernel_ulong_t)&zl3073x_chip_info[ZL30731]= }, + { "zl30732", .driver_data =3D (kernel_ulong_t)&zl3073x_chip_info[ZL30732]= }, + { "zl30733", .driver_data =3D (kernel_ulong_t)&zl3073x_chip_info[ZL30733]= }, + { "zl30734", .driver_data =3D (kernel_ulong_t)&zl3073x_chip_info[ZL30734]= }, + { "zl30735", .driver_data =3D (kernel_ulong_t)&zl3073x_chip_info[ZL30735]= }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(i2c, zl3073x_i2c_id); + +static const struct of_device_id zl3073x_i2c_of_match[] =3D { + { .compatible =3D "microchip,zl30731", .data =3D &zl3073x_chip_info[ZL307= 31] }, + { .compatible =3D "microchip,zl30732", .data =3D &zl3073x_chip_info[ZL307= 32] }, + { .compatible =3D "microchip,zl30733", .data =3D &zl3073x_chip_info[ZL307= 33] }, + { .compatible =3D "microchip,zl30734", .data =3D &zl3073x_chip_info[ZL307= 34] }, + { .compatible =3D "microchip,zl30735", .data =3D &zl3073x_chip_info[ZL307= 35] }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, zl3073x_i2c_of_match); + +static struct i2c_driver zl3073x_i2c_driver =3D { + .driver =3D { + .name =3D "zl3073x-i2c", + .of_match_table =3D zl3073x_i2c_of_match, + }, + .probe =3D zl3073x_i2c_probe, + .id_table =3D zl3073x_i2c_id, +}; +module_i2c_driver(zl3073x_i2c_driver); + +MODULE_AUTHOR("Ivan Vecera "); +MODULE_DESCRIPTION("Microchip ZL3073x I2C driver"); +MODULE_IMPORT_NS("ZL3073X"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/zl3073x-regs.h b/drivers/mfd/zl3073x-regs.h new file mode 100644 index 000000000000..6bb7ea1ef0b5 --- /dev/null +++ b/drivers/mfd/zl3073x-regs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ZL3073X_REGS_H +#define __ZL3073X_REGS_H + +#include + +/************************** + * Register Page 0, General + **************************/ + +#define ZL_REG_ID ZL_REG(0, 0x01, 2) +#define ZL_REG_REVISION ZL_REG(0, 0x03, 2) +#define ZL_REG_FW_VER ZL_REG(0, 0x05, 2) +#define ZL_REG_CUSTOM_CONFIG_VER ZL_REG(0, 0x07, 4) + +#endif /* __ZL3073X_REGS_H */ diff --git a/drivers/mfd/zl3073x-spi.c b/drivers/mfd/zl3073x-spi.c new file mode 100644 index 000000000000..962b6845c032 --- /dev/null +++ b/drivers/mfd/zl3073x-spi.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include "zl3073x.h" + +static int zl3073x_spi_probe(struct spi_device *spi) +{ + struct regmap_config regmap_cfg; + struct device *dev =3D &spi->dev; + struct zl3073x_dev *zldev; + + zldev =3D zl3073x_devm_alloc(dev); + if (IS_ERR(zldev)) + return PTR_ERR(zldev); + + zl3073x_dev_init_regmap_config(®map_cfg); + + zldev->regmap =3D devm_regmap_init_spi(spi, ®map_cfg); + if (IS_ERR(zldev->regmap)) { + dev_err_probe(dev, PTR_ERR(zldev->regmap), + "Failed to initialize regmap\n"); + return PTR_ERR(zldev->regmap); + } + + return zl3073x_dev_probe(zldev, spi_get_device_match_data(spi)); +} + +static const struct spi_device_id zl3073x_spi_id[] =3D { + { "zl30731", .driver_data =3D (kernel_ulong_t)&zl3073x_chip_info[ZL30731]= }, + { "zl30731", .driver_data =3D (kernel_ulong_t)&zl3073x_chip_info[ZL30732]= }, + { "zl30731", .driver_data =3D (kernel_ulong_t)&zl3073x_chip_info[ZL30733]= }, + { "zl30731", .driver_data =3D (kernel_ulong_t)&zl3073x_chip_info[ZL30734]= }, + { "zl30731", .driver_data =3D (kernel_ulong_t)&zl3073x_chip_info[ZL30735]= }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(spi, zl3073x_spi_id); + +static const struct of_device_id zl3073x_spi_of_match[] =3D { + { .compatible =3D "microchip,zl30731", .data =3D &zl3073x_chip_info[ZL307= 31] }, + { .compatible =3D "microchip,zl30732", .data =3D &zl3073x_chip_info[ZL307= 32] }, + { .compatible =3D "microchip,zl30733", .data =3D &zl3073x_chip_info[ZL307= 33] }, + { .compatible =3D "microchip,zl30734", .data =3D &zl3073x_chip_info[ZL307= 34] }, + { .compatible =3D "microchip,zl30735", .data =3D &zl3073x_chip_info[ZL307= 35] }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, zl3073x_spi_of_match); + +static struct spi_driver zl3073x_spi_driver =3D { + .driver =3D { + .name =3D "zl3073x-spi", + .of_match_table =3D zl3073x_spi_of_match, + }, + .probe =3D zl3073x_spi_probe, + .id_table =3D zl3073x_spi_id, +}; +module_spi_driver(zl3073x_spi_driver); + +MODULE_AUTHOR("Ivan Vecera "); +MODULE_DESCRIPTION("Microchip ZL3073x SPI driver"); +MODULE_IMPORT_NS("ZL3073X"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/zl3073x.h b/drivers/mfd/zl3073x.h new file mode 100644 index 000000000000..3a2fea61cf57 --- /dev/null +++ b/drivers/mfd/zl3073x.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ZL3073X_CORE_H +#define __ZL3073X_CORE_H + +struct device; +struct regmap_config; +struct zl3073x_dev; + +enum zl3073x_chip_type { + ZL30731, + ZL30732, + ZL30733, + ZL30734, + ZL30735, +}; + +struct zl3073x_chip_info { + const u16 *ids; + size_t num_ids; + int num_channels; +}; + +extern const struct zl3073x_chip_info zl3073x_chip_info[]; + +struct zl3073x_dev *zl3073x_devm_alloc(struct device *dev); +void zl3073x_dev_init_regmap_config(struct regmap_config *regmap_cfg); +int zl3073x_dev_probe(struct zl3073x_dev *zldev, + const struct zl3073x_chip_info *chip_info); + +#endif /* __ZL3073X_CORE_H */ diff --git a/include/linux/mfd/zl3073x-regs.h b/include/linux/mfd/zl3073x-r= egs.h new file mode 100644 index 000000000000..cd2baed244eb --- /dev/null +++ b/include/linux/mfd/zl3073x-regs.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __LINUX_MFD_ZL3073X_REGS_H +#define __LINUX_MFD_ZL3073X_REGS_H + +#include +#include + +/* + * Register address structure: + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + * 25 19 18 16 15 7 6 0 + * +------------------------------------------+ + * | max_offset | size | page | page_offset | + * +------------------------------------------+ + * + * page_offset ... <0x00..0x7F> + * page .......... HW page number + * size .......... register byte size (1, 2, 4 or 6) + * max_offset .... maximal offset for indexed registers + * (for non-indexed regs max_offset =3D=3D page_offset) + */ + +#define ZL_REG_OFFSET_MASK GENMASK(6, 0) +#define ZL_REG_PAGE_MASK GENMASK(15, 7) +#define ZL_REG_SIZE_MASK GENMASK(18, 16) +#define ZL_REG_MAX_OFFSET_MASK GENMASK(25, 19) +#define ZL_REG_ADDR_MASK GENMASK(15, 0) + +#define ZL_REG_OFFSET(_reg) FIELD_GET(ZL_REG_OFFSET_MASK, _reg) +#define ZL_REG_PAGE(_reg) FIELD_GET(ZL_REG_PAGE_MASK, _reg) +#define ZL_REG_MAX_OFFSET(_reg) FIELD_GET(ZL_REG_MAX_OFFSET_MASK, _reg) +#define ZL_REG_SIZE(_reg) FIELD_GET(ZL_REG_SIZE_MASK, _reg) +#define ZL_REG_ADDR(_reg) FIELD_GET(ZL_REG_ADDR_MASK, _reg) + +/** + * ZL_REG_IDX - define indexed register + * @_idx: index of register to access + * @_page: register page + * @_offset: register offset in page + * @_size: register byte size (1, 2, 4 or 6) + * @_items: number of register indices + * @_stride: stride between items in bytes + * + * All parameters except @_idx should be constant. + */ +#define ZL_REG_IDX(_idx, _page, _offset, _size, _items, _stride) \ + (FIELD_PREP(ZL_REG_OFFSET_MASK, \ + (_offset) + (_idx) * (_stride)) | \ + FIELD_PREP_CONST(ZL_REG_PAGE_MASK, _page) | \ + FIELD_PREP_CONST(ZL_REG_SIZE_MASK, _size) | \ + FIELD_PREP_CONST(ZL_REG_MAX_OFFSET_MASK, \ + (_offset) + ((_items) - 1) * (_stride))) + +/** + * ZL_REG - define simple (non-indexed) register + * @_page: register page + * @_offset: register offset in page + * @_size: register byte size (1, 2, 4 or 6) + * + * All parameters should be constant. + */ +#define ZL_REG(_page, _offset, _size) \ + ZL_REG_IDX(0, _page, _offset, _size, 1, 0) + +#endif /* __LINUX_MFD_ZL3073X_REGS_H */ diff --git a/include/linux/mfd/zl3073x.h b/include/linux/mfd/zl3073x.h new file mode 100644 index 000000000000..8df10b82e3c2 --- /dev/null +++ b/include/linux/mfd/zl3073x.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __LINUX_MFD_ZL3073X_H +#define __LINUX_MFD_ZL3073X_H + +#include + +struct device; +struct regmap; + +/** + * struct zl3073x_dev - zl3073x device + * @dev: pointer to device + * @regmap: regmap to access device registers + */ +struct zl3073x_dev { + struct device *dev; + struct regmap *regmap; +}; + +/********************** + * Registers operations + **********************/ + +int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 m= ask); +int zl3073x_read_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 *val); +int zl3073x_read_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 *val= ); +int zl3073x_read_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 *val= ); +int zl3073x_read_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 *val= ); +int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val); +int zl3073x_write_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 val= ); +int zl3073x_write_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 val= ); +int zl3073x_write_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 val= ); + +#endif /* __LINUX_MFD_ZL3073X_H */ --=20 2.49.0 From nobody Sun Feb 8 07:07:16 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0831524E4BF for ; Wed, 30 Apr 2025 10:12:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007922; cv=none; b=oxG7NlfEWmkgQsa11u3MSt7exH+a0x90FRqFiq0W+0jgFwfpwY5XdtodetV0cu0BLm6IY3rVXcaGriZqYtIn+Sl5saUeK2ckb0y/b5pShpjBKXinlU8fSe0ZgZHKkz0fZt2FiEaiSxERcgcstf+58ApOTXp/Lqn+u3NkMChKHU8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007922; c=relaxed/simple; bh=1GKVhGZIeSHrSFM1p8A1ycOlC+iuZov0PlsyJeC6Fh8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UqeVve3vpOLMv+X5pkoW6fgA3X5EDfcXUOL4z7qjc//4/hi1NHPPpJXtpK5P8yblb5Tn58m7+a2Z57jqiljhLDjhuI0bcdNZelt2ZzRLYhtHJYVY9rpWZAnjdY3KqV4yvDJpIYCJkoNu1oxkMFL+77R0rwYtjk3X89DtpDcn4go= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=QqpV9URB; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="QqpV9URB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1746007920; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XulpVzxDO61vMU5Om1r000qWddaCZ+Y+tGIvosGypbI=; b=QqpV9URBK88u/qYHGrsreBhcFZVIbZUCDblqjuONTqX+u7/9drVGEOa7dz5QDRWe+7352Q o5KIEBjD1LfjY+JIjJRCtAmndFZ4Upaseh51itGCOqG0C1uQiCnfcsLmiD2dfnizF6Yjlu wzuH9PDzwgQAzrdjG+5voQMM0nVTydk= Received: from mx-prod-mc-04.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-645-HKfAE1PfPrWeDjgGXM0xmw-1; Wed, 30 Apr 2025 06:11:56 -0400 X-MC-Unique: HKfAE1PfPrWeDjgGXM0xmw-1 X-Mimecast-MFC-AGG-ID: HKfAE1PfPrWeDjgGXM0xmw_1746007914 Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 384591955DCC; Wed, 30 Apr 2025 10:11:54 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.44.33.50]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 978CC1956094; Wed, 30 Apr 2025 10:11:49 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prathosh Satish , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Simon Horman , Lee Jones , Andy Shevchenko , Michal Schmidt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH net-next v6 4/8] mfd: zl3073x: Add support for devlink device info Date: Wed, 30 Apr 2025 12:11:22 +0200 Message-ID: <20250430101126.83708-5-ivecera@redhat.com> In-Reply-To: <20250430101126.83708-1-ivecera@redhat.com> References: <20250430101126.83708-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" Use devlink_alloc() to allocate zl3073x_dev structure, register the device as a devlink device, and add devlink callback to provide device info. Signed-off-by: Ivan Vecera --- v5->v6: * fixed devlink info firmware version to be running instead of fixed * added documentation for devlink info versions v4->v5: * use new register access helpers v3->v4: * pass error code from devm_add_action_or_reset() call v2->v3: * merged devlink device allocation, registration and device info callback v1->v2: * dependency on NET moved to MFD_ZL3073X_CORE in Kconfig * devlink register managed way --- Documentation/networking/devlink/index.rst | 1 + Documentation/networking/devlink/zl3073x.rst | 37 +++++++ drivers/mfd/Kconfig | 2 + drivers/mfd/zl3073x-core.c | 108 ++++++++++++++++++- 4 files changed, 146 insertions(+), 2 deletions(-) create mode 100644 Documentation/networking/devlink/zl3073x.rst diff --git a/Documentation/networking/devlink/index.rst b/Documentation/net= working/devlink/index.rst index 8319f43b5933..250ae71f4023 100644 --- a/Documentation/networking/devlink/index.rst +++ b/Documentation/networking/devlink/index.rst @@ -98,3 +98,4 @@ parameters, info versions, and other features it supports. iosm octeontx2 sfc + zl3073x diff --git a/Documentation/networking/devlink/zl3073x.rst b/Documentation/n= etworking/devlink/zl3073x.rst new file mode 100644 index 000000000000..9a6744fb2e86 --- /dev/null +++ b/Documentation/networking/devlink/zl3073x.rst @@ -0,0 +1,37 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +zl3073x devlink support +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This document describes the devlink features implemented by the ``zl3073x`` +device driver. + +Info versions +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The ``zl3073x`` driver reports the following versions + +.. list-table:: devlink info versions implemented + :widths: 5 5 5 90 + + * - Name + - Type + - Example + - Description + * - ``asic.id`` + - fixed + - 1E94 + - Chip identification number + * - ``asic.rev`` + - fixed + - 300 + - Chip revision number + * - ``fw`` + - running + - 7006 + - Firmware version number + * - ``cfg.custom_ver`` + - running + - 1.3.0.1 + - Device configuration version customized by OEM diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 7d7902ec1d89..e4eca15af175 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2424,6 +2424,8 @@ config MFD_UPBOARD_FPGA =20 config MFD_ZL3073X_CORE tristate + depends on NET + select NET_DEVLINK select MFD_CORE =20 config MFD_ZL3073X_I2C diff --git a/drivers/mfd/zl3073x-core.c b/drivers/mfd/zl3073x-core.c index c408aafb0f8a..079550682510 100644 --- a/drivers/mfd/zl3073x-core.c +++ b/drivers/mfd/zl3073x-core.c @@ -8,8 +8,11 @@ #include #include #include +#include #include +#include #include +#include #include "zl3073x.h" #include "zl3073x-regs.h" =20 @@ -375,6 +378,83 @@ int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, un= signed int reg, u8 mask) } EXPORT_SYMBOL_NS_GPL(zl3073x_poll_zero_u8, "ZL3073X"); =20 +/** + * zl3073x_devlink_info_get - Devlink device info callback + * @devlink: devlink structure pointer + * @req: devlink request pointer to store information + * @extack: netlink extack pointer to report errors + * + * Return: 0 on success, <0 on error + */ +static int zl3073x_devlink_info_get(struct devlink *devlink, + struct devlink_info_req *req, + struct netlink_ext_ack *extack) +{ + struct zl3073x_dev *zldev =3D devlink_priv(devlink); + u16 id, revision, fw_ver; + char buf[16]; + u32 cfg_ver; + int rc; + + rc =3D zl3073x_read_u16(zldev, ZL_REG_ID, &id); + if (rc) + return rc; + + snprintf(buf, sizeof(buf), "%X", id); + rc =3D devlink_info_version_fixed_put(req, + DEVLINK_INFO_VERSION_GENERIC_ASIC_ID, + buf); + if (rc) + return rc; + + rc =3D zl3073x_read_u16(zldev, ZL_REG_REVISION, &revision); + if (rc) + return rc; + + snprintf(buf, sizeof(buf), "%X", revision); + rc =3D devlink_info_version_fixed_put(req, + DEVLINK_INFO_VERSION_GENERIC_ASIC_REV, + buf); + if (rc) + return rc; + + rc =3D zl3073x_read_u16(zldev, ZL_REG_FW_VER, &fw_ver); + if (rc) + return rc; + + snprintf(buf, sizeof(buf), "%u", fw_ver); + rc =3D devlink_info_version_running_put(req, + DEVLINK_INFO_VERSION_GENERIC_FW, + buf); + if (rc) + return rc; + + rc =3D zl3073x_read_u32(zldev, ZL_REG_CUSTOM_CONFIG_VER, &cfg_ver); + if (rc) + return rc; + + /* No custom config version */ + if (cfg_ver =3D=3D U32_MAX) + return 0; + + snprintf(buf, sizeof(buf), "%lu.%lu.%lu.%lu", + FIELD_GET(GENMASK(31, 24), cfg_ver), + FIELD_GET(GENMASK(23, 16), cfg_ver), + FIELD_GET(GENMASK(15, 8), cfg_ver), + FIELD_GET(GENMASK(7, 0), cfg_ver)); + + return devlink_info_version_running_put(req, "cfg.custom_ver", buf); +} + +static const struct devlink_ops zl3073x_devlink_ops =3D { + .info_get =3D zl3073x_devlink_info_get, +}; + +static void zl3073x_devlink_free(void *ptr) +{ + devlink_free(ptr); +} + /** * zl3073x_devm_alloc - allocates zl3073x device structure * @dev: pointer to device structure @@ -386,11 +466,19 @@ EXPORT_SYMBOL_NS_GPL(zl3073x_poll_zero_u8, "ZL3073X"); struct zl3073x_dev *zl3073x_devm_alloc(struct device *dev) { struct zl3073x_dev *zldev; + struct devlink *devlink; + int rc; =20 - zldev =3D devm_kzalloc(dev, sizeof(*zldev), GFP_KERNEL); - if (!zldev) + devlink =3D devlink_alloc(&zl3073x_devlink_ops, sizeof(*zldev), dev); + if (!devlink) return ERR_PTR(-ENOMEM); =20 + /* Add devres action to free devlink device */ + rc =3D devm_add_action_or_reset(dev, zl3073x_devlink_free, devlink); + if (rc) + return ERR_PTR(rc); + + zldev =3D devlink_priv(devlink); zldev->dev =3D dev; dev_set_drvdata(zldev->dev, zldev); =20 @@ -410,6 +498,11 @@ void zl3073x_dev_init_regmap_config(struct regmap_conf= ig *regmap_cfg) } EXPORT_SYMBOL_NS_GPL(zl3073x_dev_init_regmap_config, "ZL3073X"); =20 +static void zl3073x_devlink_unregister(void *ptr) +{ + devlink_unregister(ptr); +} + /** * zl3073x_dev_probe - initialize zl3073x device * @zldev: pointer to zl3073x device @@ -423,6 +516,7 @@ int zl3073x_dev_probe(struct zl3073x_dev *zldev, const struct zl3073x_chip_info *chip_info) { u16 id, revision, fw_ver; + struct devlink *devlink; unsigned int i; u32 cfg_ver; int rc; @@ -463,6 +557,16 @@ int zl3073x_dev_probe(struct zl3073x_dev *zldev, FIELD_GET(GENMASK(15, 8), cfg_ver), FIELD_GET(GENMASK(7, 0), cfg_ver)); =20 + /* Register the device as devlink device */ + devlink =3D priv_to_devlink(zldev); + devlink_register(devlink); + + /* Add devres action to unregister devlink device */ + rc =3D devm_add_action_or_reset(zldev->dev, zl3073x_devlink_unregister, + devlink); + if (rc) + return rc; + return 0; } EXPORT_SYMBOL_NS_GPL(zl3073x_dev_probe, "ZL3073X"); --=20 2.49.0 From nobody Sun Feb 8 07:07:16 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD6D624729A for ; Wed, 30 Apr 2025 10:12:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007933; cv=none; b=i5p9UKbdfmV1KYhbW5L5PXj/+PSUPm+xCvi+MWVrwChK4Zi8hmPkd2H9dmoBQVyvmlXJq7oQKIchXZJfsF2iC2KClHR+FMAJQhGy/7a4Z1d9mPFyDFZB60aehRPIFny/EIbHNxA0CgAtNnTK7brsC8H90oCdYo5TTIe7Qr/jhUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007933; c=relaxed/simple; bh=FUN5iesvZIB15oVD5+kjdSiETFouMpoSDwpkgdOWONo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tUxpqhSGHOosjDw0hkzf9AcvpM1xq8p4/geD+Bt9CqXYqUJKsECe84+lS+EnUCaUFVtmGA1LQy814sS82fvYf/G46ujmozmISTUPyxEw7ll0BIp1JkUta1iBugrbc3taNmVbItbOmCytI+UuchEsunxC1+3BtbwHs5zNTnGu2ZE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=LJ+1vYBH; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="LJ+1vYBH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1746007928; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DvlamrKvIRy0y8V7iGg6C04u4JBbaSuDm4R9vBWsHHc=; b=LJ+1vYBHy4nN+bmWkYxboVWB3iHamhPHbkuiAUwJpe6gXUsmB1Yu0DjNnceqAlDSjTJBL4 TV4c9curXBQ/NGXS4uRAt7nyA7/bQe2RifxabBY89BgLLe10CoJxiW8QIFu5XuJud9PSm0 gzwqcHRHhg4qmMfY8z6hjPWy65DtneY= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-45-GZu9xsAiP5qGY3xFO8IXAw-1; Wed, 30 Apr 2025 06:12:04 -0400 X-MC-Unique: GZu9xsAiP5qGY3xFO8IXAw-1 X-Mimecast-MFC-AGG-ID: GZu9xsAiP5qGY3xFO8IXAw_1746007919 Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id B5C7D1800877; Wed, 30 Apr 2025 10:11:59 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.44.33.50]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 9FFEE19560B7; Wed, 30 Apr 2025 10:11:54 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prathosh Satish , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Simon Horman , Lee Jones , Andy Shevchenko , Michal Schmidt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH net-next v6 5/8] mfd: zl3073x: Protect operations requiring multiple register accesses Date: Wed, 30 Apr 2025 12:11:23 +0200 Message-ID: <20250430101126.83708-6-ivecera@redhat.com> In-Reply-To: <20250430101126.83708-1-ivecera@redhat.com> References: <20250430101126.83708-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" Registers located on page 10 and above are called mailbox-type registers. Each page represents a mailbox and is used to read from and write to configuration of a specific object (DPLL, output, reference or synth). Each mailbox page contains a mask register, which selects an index of the target object to interact with and a semaphore register, which indicates the requested operation. The remaining registers within the page are latch registers, which are populated by the firmware during read operations or by the driver prior to write operations. Operations with these registers requires multiple register reads, writes and polls and all of them need to be done atomically. So add multiop_lock mutex to protect such operations and check the mutex is held by the caller when it's accessing registers from page 10 and above. Signed-off-by: Ivan Vecera --- v5->v6: * no change v4->v5: * dropped mailbox API and replaced by an ability to protect multi-op accesses v3->v4: * completely reworked mailbox access v1->v3: * dropped ZL3073X_MB_OP macro usage --- drivers/mfd/zl3073x-core.c | 14 ++++++++++++++ include/linux/mfd/zl3073x.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/drivers/mfd/zl3073x-core.c b/drivers/mfd/zl3073x-core.c index 079550682510..a12cfc7eb6ff 100644 --- a/drivers/mfd/zl3073x-core.c +++ b/drivers/mfd/zl3073x-core.c @@ -121,6 +121,12 @@ static const struct regmap_config zl3073x_regmap_confi= g =3D { static bool zl3073x_check_reg(struct zl3073x_dev *zldev, unsigned int reg, size_t size) { + /* Check that multiop lock is held when accessing registers + * from page 10 and above. + */ + if (ZL_REG_PAGE(reg) >=3D 10) + lockdep_assert_held(&zldev->multiop_lock); + /* Check the index is in valid range for indexed register */ if (ZL_REG_OFFSET(reg) > ZL_REG_MAX_OFFSET(reg)) { dev_err(zldev->dev, "Index out of range for reg 0x%04lx\n", @@ -557,6 +563,14 @@ int zl3073x_dev_probe(struct zl3073x_dev *zldev, FIELD_GET(GENMASK(15, 8), cfg_ver), FIELD_GET(GENMASK(7, 0), cfg_ver)); =20 + /* Initialize mutex for operations where multiple reads, writes + * and/or polls are required to be done atomically. + */ + rc =3D devm_mutex_init(zldev->dev, &zldev->multiop_lock); + if (rc) + return dev_err_probe(zldev->dev, rc, + "Failed to initialize mutex\n"); + /* Register the device as devlink device */ devlink =3D priv_to_devlink(zldev); devlink_register(devlink); diff --git a/include/linux/mfd/zl3073x.h b/include/linux/mfd/zl3073x.h index 8df10b82e3c2..a42a275577c4 100644 --- a/include/linux/mfd/zl3073x.h +++ b/include/linux/mfd/zl3073x.h @@ -3,6 +3,7 @@ #ifndef __LINUX_MFD_ZL3073X_H #define __LINUX_MFD_ZL3073X_H =20 +#include #include =20 struct device; @@ -12,10 +13,12 @@ struct regmap; * struct zl3073x_dev - zl3073x device * @dev: pointer to device * @regmap: regmap to access device registers + * @multiop_lock: to serialize multiple register operations */ struct zl3073x_dev { struct device *dev; struct regmap *regmap; + struct mutex multiop_lock; }; =20 /********************** --=20 2.49.0 From nobody Sun Feb 8 07:07:16 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9415258CD0 for ; Wed, 30 Apr 2025 10:12:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007936; cv=none; b=EVirUAy2k3m0H40QfuYNB2gAK0AvQbbvWbB/o4p5iSSy/IeoHYGNhuras2lfKlqTHpdBgLSrAww8dTj+/7V23Nv511YAo1fpp0Z7IttQm9gc+Imvxa7/EgawuC+LF4ja2uOu+/3mTUeXVUWV5uaxCpExBlkfcS0qZFtp3mxcjkM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007936; c=relaxed/simple; bh=F2ICcp1VN30PSvJ6FW5pzvlH4pPfz83/+I0OOGuKJIM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WIp5wTEeBkUq8MAxkQpHRnXln/kEtWee0Ez1SEVlMWyZRiL24inkXx4OKdCT0GmdS45MJftkZMj0aP2i9IuzhTD4IKxAY7Juc9BTcnCA7m+DHfONV2RnmzbDqxN4PssZlrw9krUmfpVbsDGPYKSMHXQ+JNhEBXjL7epOYXn/b3Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=JP0vBeWL; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="JP0vBeWL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1746007933; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5BI7OKJLiayDgDcMCjkm647pCc/mn18BjvQG+fwO128=; b=JP0vBeWLv4ntUvy0lk2A9c8aEoxOaTTHkXDDtHr9cvqcpwiG07usC+UuQ9P/M+Eh46OCHo XI4I0h60N8BEaGdjGAnu940MyoXhRwHHt5h3smc+oKN6Tp6PEX7KR35qZk8vBqlbG5YnNj k1oxHfxx0QSYl6kHa2RUo3mjdYSAbf4= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-176-IB6oMRvLPJiqp__6HzClsg-1; Wed, 30 Apr 2025 06:12:08 -0400 X-MC-Unique: IB6oMRvLPJiqp__6HzClsg-1 X-Mimecast-MFC-AGG-ID: IB6oMRvLPJiqp__6HzClsg_1746007925 Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 4F7371956088; Wed, 30 Apr 2025 10:12:05 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.44.33.50]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 1022D1956094; Wed, 30 Apr 2025 10:11:59 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prathosh Satish , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Simon Horman , Lee Jones , Andy Shevchenko , Michal Schmidt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH net-next v6 6/8] mfd: zl3073x: Fetch invariants during probe Date: Wed, 30 Apr 2025 12:11:24 +0200 Message-ID: <20250430101126.83708-7-ivecera@redhat.com> In-Reply-To: <20250430101126.83708-1-ivecera@redhat.com> References: <20250430101126.83708-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" Several configuration parameters will remain constant at runtime, so we can load them during probe to avoid excessive reads from the hardware. These parameters will be frequently accessed by the DPLL sub-device driver (in follow-up series), and later by the PHC/PTP sub-device driver. Read the following parameters from the device during probe and store them for later use: * frequencies of the synthesizers and their associated DPLL channels * enablement and type (single-ended or differential) of input pins * associated synthesizers, signal format, and enablement status of outputs Signed-off-by: Ivan Vecera --- v5->v6: * no change v4->v5: * updated to use new register API v3->v4: * adjusted for new mailbox API v2->v3: * dropped usage of macros for generating helper functions v1->v2: * fixed and added inline documentation --- drivers/mfd/zl3073x-core.c | 251 +++++++++++++++++++++++++++++++ drivers/mfd/zl3073x-regs.h | 37 +++++ include/linux/mfd/zl3073x-regs.h | 22 +++ include/linux/mfd/zl3073x.h | 151 +++++++++++++++++++ 4 files changed, 461 insertions(+) diff --git a/drivers/mfd/zl3073x-core.c b/drivers/mfd/zl3073x-core.c index a12cfc7eb6ff..135fb9ba7f19 100644 --- a/drivers/mfd/zl3073x-core.c +++ b/drivers/mfd/zl3073x-core.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -504,6 +505,251 @@ void zl3073x_dev_init_regmap_config(struct regmap_con= fig *regmap_cfg) } EXPORT_SYMBOL_NS_GPL(zl3073x_dev_init_regmap_config, "ZL3073X"); =20 +static int +zl3073x_mb_op(struct zl3073x_dev *zldev, unsigned int op_reg, u8 op_val, + unsigned int mask_reg, u16 mask_val) +{ + int rc; + + /* Set mask for the operation */ + rc =3D zl3073x_write_u16(zldev, mask_reg, mask_val); + if (rc) + return rc; + + /* Trigger the operation */ + rc =3D zl3073x_write_u8(zldev, op_reg, op_val); + if (rc) + return rc; + + /* Wait for the operation to actually finish */ + return zl3073x_poll_zero_u8(zldev, op_reg, op_val); +} + +/** + * zl3073x_input_state_fetch - get input state + * @zldev: pointer to zl3073x_dev structure + * @index: input pin index to fetch state for + * + * Function fetches information for the given input reference that are + * invariant and stores them for later use. + * + * Return: 0 on success, <0 on error + */ +static int +zl3073x_input_state_fetch(struct zl3073x_dev *zldev, u8 index) +{ + struct zl3073x_input *input; + u8 ref_config; + int rc; + + input =3D &zldev->input[index]; + + /* If the input is differential then the configuration for N-pin + * reference is ignored and P-pin config is used for both. + */ + if (zl3073x_is_n_pin(index) && + zl3073x_input_is_diff(zldev, index - 1)) { + input->enabled =3D zl3073x_input_is_enabled(zldev, index - 1); + input->diff =3D true; + + return 0; + } + + guard(mutex)(&zldev->multiop_lock); + + /* Read reference configuration */ + rc =3D zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, + ZL_REG_REF_MB_MASK, BIT(index)); + if (rc) + return rc; + + /* Read ref_config register */ + rc =3D zl3073x_read_u8(zldev, ZL_REG_REF_CONFIG, &ref_config); + if (rc) + return rc; + + input->enabled =3D FIELD_GET(ZL_REF_CONFIG_ENABLE, ref_config); + input->diff =3D FIELD_GET(ZL_REF_CONFIG_DIFF_EN, ref_config); + + dev_dbg(zldev->dev, "INPUT%u is %s and configured as %s\n", index, + input->enabled ? "enabled" : "disabled", + input->diff ? "differential" : "single-ended"); + + return rc; +} + +/** + * zl3073x_output_state_fetch - get output state + * @zldev: pointer to zl3073x_dev structure + * @index: output index to fetch state for + * + * Function fetches information for the given output (not output pin) + * that are invariant and stores them for later use. + * + * Return: 0 on success, <0 on error + */ +static int +zl3073x_output_state_fetch(struct zl3073x_dev *zldev, u8 index) +{ + struct zl3073x_output *output; + u8 output_ctrl, output_mode; + int rc; + + output =3D &zldev->output[index]; + + /* Read output configuration */ + rc =3D zl3073x_read_u8(zldev, ZL_REG_OUTPUT_CTRL(index), &output_ctrl); + if (rc) + return rc; + + /* Store info about output enablement and synthesizer the output + * is connected to. + */ + output->enabled =3D FIELD_GET(ZL_OUTPUT_CTRL_EN, output_ctrl); + output->synth =3D FIELD_GET(ZL_OUTPUT_CTRL_SYNTH_SEL, output_ctrl); + + dev_dbg(zldev->dev, "OUTPUT%u is %s, connected to SYNTH%u\n", + index, output->enabled ? "enabled" : "disabled", output->synth); + + guard(mutex)(&zldev->multiop_lock); + + /* Read output configuration */ + rc =3D zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, + ZL_REG_OUTPUT_MB_MASK, BIT(index)); + if (rc) + return rc; + + /* Read output_mode */ + rc =3D zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode); + if (rc) + return rc; + + /* Extract and store output signal format */ + output->signal_format =3D FIELD_GET(ZL_OUTPUT_MODE_SIGNAL_FORMAT, + output_mode); + + dev_dbg(zldev->dev, "OUTPUT%u has signal format 0x%02x\n", index, + output->signal_format); + + return rc; +} + +/** + * zl3073x_synth_state_fetch - get synth state + * @zldev: pointer to zl3073x_dev structure + * @index: synth index to fetch state for + * + * Function fetches information for the given synthesizer that are + * invariant and stores them for later use. + * + * Return: 0 on success, <0 on error + */ +static int +zl3073x_synth_state_fetch(struct zl3073x_dev *zldev, u8 index) +{ + u16 base, num, denom; + u8 synth_ctrl; + u32 mult; + int rc; + + /* Read synth control register */ + rc =3D zl3073x_read_u8(zldev, ZL_REG_SYNTH_CTRL(index), &synth_ctrl); + if (rc) + return rc; + + /* Extract and store DPLL channel the synth is driven by */ + zldev->synth[index].dpll =3D FIELD_GET(ZL_SYNTH_CTRL_DPLL_SEL, + synth_ctrl); + + dev_dbg(zldev->dev, "SYNTH%u is connected to DPLL%u\n", index, + zldev->synth[index].dpll); + + guard(mutex)(&zldev->multiop_lock); + + /* Read synth configuration */ + rc =3D zl3073x_mb_op(zldev, ZL_REG_SYNTH_MB_SEM, ZL_SYNTH_MB_SEM_RD, + ZL_REG_SYNTH_MB_MASK, BIT(index)); + if (rc) + return rc; + + /* The output frequency is determined by the following formula: + * base * multiplier * numerator / denominator + * + * Read registers with these values + */ + rc =3D zl3073x_read_u16(zldev, ZL_REG_SYNTH_FREQ_BASE, &base); + if (rc) + return rc; + + rc =3D zl3073x_read_u32(zldev, ZL_REG_SYNTH_FREQ_MULT, &mult); + if (rc) + return rc; + + rc =3D zl3073x_read_u16(zldev, ZL_REG_SYNTH_FREQ_M, &num); + if (rc) + return rc; + + rc =3D zl3073x_read_u16(zldev, ZL_REG_SYNTH_FREQ_N, &denom); + if (rc) + return rc; + + /* Check denominator for zero to avoid div by 0 */ + if (!denom) { + dev_err(zldev->dev, + "Zero divisor for SYNTH%u retrieved from device\n", + index); + return -EINVAL; + } + + /* Compute and store synth frequency */ + zldev->synth[index].freq =3D mul_u64_u32_div(mul_u32_u32(base, mult), + num, denom); + + dev_dbg(zldev->dev, "SYNTH%u frequency: %llu Hz\n", index, + zldev->synth[index].freq); + + return rc; +} + +static int +zl3073x_dev_state_fetch(struct zl3073x_dev *zldev) +{ + int rc; + u8 i; + + for (i =3D 0; i < ZL3073X_NUM_INPUTS; i++) { + rc =3D zl3073x_input_state_fetch(zldev, i); + if (rc) { + dev_err(zldev->dev, + "Failed to fetch input state: %pe\n", + ERR_PTR(rc)); + return rc; + } + } + + for (i =3D 0; i < ZL3073X_NUM_SYNTHS; i++) { + rc =3D zl3073x_synth_state_fetch(zldev, i); + if (rc) { + dev_err(zldev->dev, + "Failed to fetch synth state: %pe\n", + ERR_PTR(rc)); + return rc; + } + } + + for (i =3D 0; i < ZL3073X_NUM_OUTPUTS; i++) { + rc =3D zl3073x_output_state_fetch(zldev, i); + if (rc) { + dev_err(zldev->dev, + "Failed to fetch output state: %pe\n", + ERR_PTR(rc)); + return rc; + } + } + + return rc; +} + static void zl3073x_devlink_unregister(void *ptr) { devlink_unregister(ptr); @@ -571,6 +817,11 @@ int zl3073x_dev_probe(struct zl3073x_dev *zldev, return dev_err_probe(zldev->dev, rc, "Failed to initialize mutex\n"); =20 + /* Fetch device state */ + rc =3D zl3073x_dev_state_fetch(zldev); + if (rc) + return rc; + /* Register the device as devlink device */ devlink =3D priv_to_devlink(zldev); devlink_register(devlink); diff --git a/drivers/mfd/zl3073x-regs.h b/drivers/mfd/zl3073x-regs.h index 6bb7ea1ef0b5..dcd278acab4b 100644 --- a/drivers/mfd/zl3073x-regs.h +++ b/drivers/mfd/zl3073x-regs.h @@ -14,4 +14,41 @@ #define ZL_REG_FW_VER ZL_REG(0, 0x05, 2) #define ZL_REG_CUSTOM_CONFIG_VER ZL_REG(0, 0x07, 4) =20 +/*********************************** + * Register Page 9, Synth and Output + ***********************************/ + +#define ZL_REG_SYNTH_CTRL(_idx) \ + ZL_REG_IDX(_idx, 9, 0x00, 1, ZL3073X_NUM_SYNTHS, 1) +#define ZL_SYNTH_CTRL_EN BIT(0) +#define ZL_SYNTH_CTRL_DPLL_SEL GENMASK(6, 4) + +#define ZL_REG_OUTPUT_CTRL(_idx) \ + ZL_REG_IDX(_idx, 9, 0x28, 1, ZL3073X_NUM_OUTPUTS, 1) +#define ZL_OUTPUT_CTRL_EN BIT(0) +#define ZL_OUTPUT_CTRL_SYNTH_SEL GENMASK(6, 4) + +/******************************* + * Register Page 10, Ref Mailbox + *******************************/ + +#define ZL_REG_REF_CONFIG ZL_REG(10, 0x0d, 1) +#define ZL_REF_CONFIG_ENABLE BIT(0) +#define ZL_REF_CONFIG_DIFF_EN BIT(2) + +/********************************* + * Register Page 13, Synth Mailbox + *********************************/ + +#define ZL_REG_SYNTH_MB_MASK ZL_REG(13, 0x02, 2) + +#define ZL_REG_SYNTH_MB_SEM ZL_REG(13, 0x04, 1) +#define ZL_SYNTH_MB_SEM_WR BIT(0) +#define ZL_SYNTH_MB_SEM_RD BIT(1) + +#define ZL_REG_SYNTH_FREQ_BASE ZL_REG(13, 0x06, 2) +#define ZL_REG_SYNTH_FREQ_MULT ZL_REG(13, 0x08, 4) +#define ZL_REG_SYNTH_FREQ_M ZL_REG(13, 0x0c, 2) +#define ZL_REG_SYNTH_FREQ_N ZL_REG(13, 0x0e, 2) + #endif /* __ZL3073X_REGS_H */ diff --git a/include/linux/mfd/zl3073x-regs.h b/include/linux/mfd/zl3073x-r= egs.h index cd2baed244eb..d94bd389f9a7 100644 --- a/include/linux/mfd/zl3073x-regs.h +++ b/include/linux/mfd/zl3073x-regs.h @@ -63,4 +63,26 @@ #define ZL_REG(_page, _offset, _size) \ ZL_REG_IDX(0, _page, _offset, _size, 1, 0) =20 +/******************************* + * Register Page 10, Ref Mailbox + *******************************/ + +#define ZL_REG_REF_MB_MASK ZL_REG(10, 0x02, 2) + +#define ZL_REG_REF_MB_SEM ZL_REG(10, 0x04, 1) +#define ZL_REF_MB_SEM_WR BIT(0) +#define ZL_REF_MB_SEM_RD BIT(1) + +/********************************** + * Register Page 14, Output Mailbox + **********************************/ +#define ZL_REG_OUTPUT_MB_MASK ZL_REG(14, 0x02, 2) + +#define ZL_REG_OUTPUT_MB_SEM ZL_REG(14, 0x04, 1) +#define ZL_OUTPUT_MB_SEM_WR BIT(0) +#define ZL_OUTPUT_MB_SEM_RD BIT(1) + +#define ZL_REG_OUTPUT_MODE ZL_REG(14, 0x05, 1) +#define ZL_OUTPUT_MODE_SIGNAL_FORMAT GENMASK(7, 4) + #endif /* __LINUX_MFD_ZL3073X_REGS_H */ diff --git a/include/linux/mfd/zl3073x.h b/include/linux/mfd/zl3073x.h index a42a275577c4..da4b7ae6a89e 100644 --- a/include/linux/mfd/zl3073x.h +++ b/include/linux/mfd/zl3073x.h @@ -9,16 +9,63 @@ struct device; struct regmap; =20 +/* + * Hardware limits for ZL3073x chip family + */ +#define ZL3073X_NUM_INPUTS 10 +#define ZL3073X_NUM_OUTPUTS 10 +#define ZL3073X_NUM_SYNTHS 5 + +/** + * struct zl3073x_input - input invariant info + * @enabled: input is enabled or disabled + * @diff: true if input is differential + */ +struct zl3073x_input { + bool enabled; + bool diff; +}; + +/** + * struct zl3073x_output - output invariant info + * @enabled: output is enabled or disabled + * @synth: synthesizer the output is connected to + * @signal_format: output signal format + */ +struct zl3073x_output { + bool enabled; + u8 synth; + u8 signal_format; +}; + +/** + * struct zl3073x_synth - synthesizer invariant info + * @freq: synthesizer frequency + * @dpll: ID of DPLL the synthesizer is driven by + */ +struct zl3073x_synth { + u64 freq; + u8 dpll; +}; + /** * struct zl3073x_dev - zl3073x device * @dev: pointer to device * @regmap: regmap to access device registers * @multiop_lock: to serialize multiple register operations + * @input: array of inputs' invariants + * @output: array of outputs' invariants + * @synth: array of synthesizers' invariants */ struct zl3073x_dev { struct device *dev; struct regmap *regmap; struct mutex multiop_lock; + + /* Invariants */ + struct zl3073x_input input[ZL3073X_NUM_INPUTS]; + struct zl3073x_output output[ZL3073X_NUM_OUTPUTS]; + struct zl3073x_synth synth[ZL3073X_NUM_SYNTHS]; }; =20 /********************** @@ -35,4 +82,108 @@ int zl3073x_write_u16(struct zl3073x_dev *zldev, unsign= ed int reg, u16 val); int zl3073x_write_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 val= ); int zl3073x_write_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 val= ); =20 +static inline +bool zl3073x_is_n_pin(u8 index) +{ + /* P-pins indices are even while N-pins are odd */ + return index & 1; +} + +static inline +bool zl3073x_is_p_pin(u8 index) +{ + return !zl3073x_is_n_pin(index); +} + +/** + * zl3073x_input_is_diff - check if the given input ref is differential + * @zldev: pointer to zl3073x device + * @index: output index + * + * Return: true if input is differential, false if input is single-ended + */ +static inline +bool zl3073x_input_is_diff(struct zl3073x_dev *zldev, u8 index) +{ + return zldev->input[index].diff; +} + +/** + * zl3073x_input_is_enabled - check if the given input ref is enabled + * @zldev: pointer to zl3073x device + * @index: input index + * + * Return: true if input is enabled, false if input is disabled + */ +static inline +bool zl3073x_input_is_enabled(struct zl3073x_dev *zldev, u8 index) +{ + return zldev->input[index].enabled; +} + +/** + * zl3073x_output_is_enabled - check if the given output is enabled + * @zldev: pointer to zl3073x device + * @index: output index + * + * Return: true if output is enabled, false if output is disabled + */ +static inline +u8 zl3073x_output_is_enabled(struct zl3073x_dev *zldev, u8 index) +{ + return zldev->output[index].enabled; +} + +/** + * zl3073x_output_signal_format_get - get output signal format + * @zldev: pointer to zl3073x device + * @index: output index + * + * Return: signal format of given output + */ +static inline +u8 zl3073x_output_signal_format_get(struct zl3073x_dev *zldev, u8 index) +{ + return zldev->output[index].signal_format; +} + +/** + * zl3073x_output_synth_get - get synth connected to given output + * @zldev: pointer to zl3073x device + * @index: output index + * + * Return: index of synth connected to given output. + */ +static inline +u8 zl3073x_output_synth_get(struct zl3073x_dev *zldev, u8 index) +{ + return zldev->output[index].synth; +} + +/** + * zl3073x_synth_dpll_get - get DPLL ID the synth is driven by + * @zldev: pointer to zl3073x device + * @index: synth index + * + * Return: ID of DPLL the given synthetizer is driven by + */ +static inline +u64 zl3073x_synth_dpll_get(struct zl3073x_dev *zldev, u8 index) +{ + return zldev->synth[index].dpll; +} + +/** + * zl3073x_synth_freq_get - get synth current freq + * @zldev: pointer to zl3073x device + * @index: synth index + * + * Return: frequency of given synthetizer + */ +static inline +u64 zl3073x_synth_freq_get(struct zl3073x_dev *zldev, u8 index) +{ + return zldev->synth[index].freq; +} + #endif /* __LINUX_MFD_ZL3073X_H */ --=20 2.49.0 From nobody Sun Feb 8 07:07:16 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3DB6259C8A for ; Wed, 30 Apr 2025 10:12:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007939; cv=none; b=lkmHaWrfjszMKcn55USIheZ0/nnjU5Ilm20IFZCrCpKj/qf3a6i4dYa8haKoSNhregSdqdFdfFuwjQEHaj6tTdUgjvfXJX2l1VPO/PuH5SIVQ10yEa7HWiN2J3oxOPUOu7/m5dvbXbBjyk/1JXjb0Q5+8lAC506eZdu2Bw6j2d4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007939; c=relaxed/simple; bh=HISn2Wkw29SIz8wUPeKPvDbv1xtSft5HQ3zkKAZ8L70=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rl09JDyh27W4+mpaJoWlXEgQrsF+qqKTs1YmfPspBRzHBMSMuJDn0hzjY3NRkTlUxI9MRzuXuI0wWlWw6/zV4X01+AYbJmzQwySO1JW5mupS9opoxEBG3Xb9JR1t+BB1KsttOBy+2sOcZKZH8S7/BpKOFawMlK7ah+9JgSxTFsw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=HzZMQVMI; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="HzZMQVMI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1746007936; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DnVjjebiMP5z10HLeFIpV6rcUK3VD7GtbWLDD8lWnns=; b=HzZMQVMIk/UQzRxNkEENDjsIFo2REBP3WyYOuIIS6Lodyj6cU7yC8WHXKmjAEn1BSwCruh YxDAIE/7sUArqDwHXGqFj2UXYDAO8FcIlXzt+khHPN2/eKtK1EFw0ba0LK6XnUR90eSr/M cgSjLnwmg6RGNW634Hxz39kdUEmizIc= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-470-0LzvmMHqOJC7DI_Ua_7w6g-1; Wed, 30 Apr 2025 06:12:12 -0400 X-MC-Unique: 0LzvmMHqOJC7DI_Ua_7w6g-1 X-Mimecast-MFC-AGG-ID: 0LzvmMHqOJC7DI_Ua_7w6g_1746007930 Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 4FD2118001EA; Wed, 30 Apr 2025 10:12:10 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.44.33.50]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id B488D19560B7; Wed, 30 Apr 2025 10:12:05 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prathosh Satish , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Simon Horman , Lee Jones , Andy Shevchenko , Michal Schmidt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH net-next v6 7/8] mfd: zl3073x: Add clock_id field Date: Wed, 30 Apr 2025 12:11:25 +0200 Message-ID: <20250430101126.83708-8-ivecera@redhat.com> In-Reply-To: <20250430101126.83708-1-ivecera@redhat.com> References: <20250430101126.83708-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" Add .clock_id to zl3073x_dev structure that will be used by later commits introducing DPLL driver. The clock ID is required for DPLL device registration. To generate this ID, use chip ID read during device initialization. In case where multiple zl3073x based chips are present, the chip ID is shifted and lower bits are filled by an unique value - using the I2C device address for I2C connections and the chip-select value for SPI connections. Signed-off-by: Ivan Vecera v5->v6: * no change --- drivers/mfd/zl3073x-core.c | 6 +++++- drivers/mfd/zl3073x-i2c.c | 4 +++- drivers/mfd/zl3073x-spi.c | 4 +++- drivers/mfd/zl3073x.h | 2 +- include/linux/mfd/zl3073x.h | 2 ++ 5 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/zl3073x-core.c b/drivers/mfd/zl3073x-core.c index 135fb9ba7f19..050dc57c90c3 100644 --- a/drivers/mfd/zl3073x-core.c +++ b/drivers/mfd/zl3073x-core.c @@ -759,13 +759,14 @@ static void zl3073x_devlink_unregister(void *ptr) * zl3073x_dev_probe - initialize zl3073x device * @zldev: pointer to zl3073x device * @chip_info: chip info based on compatible + * @dev_id: device ID to be used as part of clock ID * * Common initialization of zl3073x device structure. * * Returns: 0 on success, <0 on error */ int zl3073x_dev_probe(struct zl3073x_dev *zldev, - const struct zl3073x_chip_info *chip_info) + const struct zl3073x_chip_info *chip_info, u8 dev_id) { u16 id, revision, fw_ver; struct devlink *devlink; @@ -809,6 +810,9 @@ int zl3073x_dev_probe(struct zl3073x_dev *zldev, FIELD_GET(GENMASK(15, 8), cfg_ver), FIELD_GET(GENMASK(7, 0), cfg_ver)); =20 + /* Use chip ID and given dev ID as clock ID */ + zldev->clock_id =3D ((u64)id << 8) | dev_id; + /* Initialize mutex for operations where multiple reads, writes * and/or polls are required to be done atomically. */ diff --git a/drivers/mfd/zl3073x-i2c.c b/drivers/mfd/zl3073x-i2c.c index da8bbd702d76..e00277f87de9 100644 --- a/drivers/mfd/zl3073x-i2c.c +++ b/drivers/mfd/zl3073x-i2c.c @@ -27,7 +27,9 @@ static int zl3073x_i2c_probe(struct i2c_client *client) return PTR_ERR(zldev->regmap); } =20 - return zl3073x_dev_probe(zldev, i2c_get_match_data(client)); + /* Initialize device and use I2C address as dev ID */ + return zl3073x_dev_probe(zldev, i2c_get_match_data(client), + client->addr); } =20 static const struct i2c_device_id zl3073x_i2c_id[] =3D { diff --git a/drivers/mfd/zl3073x-spi.c b/drivers/mfd/zl3073x-spi.c index 962b6845c032..368001ae19db 100644 --- a/drivers/mfd/zl3073x-spi.c +++ b/drivers/mfd/zl3073x-spi.c @@ -27,7 +27,9 @@ static int zl3073x_spi_probe(struct spi_device *spi) return PTR_ERR(zldev->regmap); } =20 - return zl3073x_dev_probe(zldev, spi_get_device_match_data(spi)); + /* Initialize device and use SPI chip select value as dev ID */ + return zl3073x_dev_probe(zldev, spi_get_device_match_data(spi), + spi_get_chipselect(spi, 0)); } =20 static const struct spi_device_id zl3073x_spi_id[] =3D { diff --git a/drivers/mfd/zl3073x.h b/drivers/mfd/zl3073x.h index 3a2fea61cf57..abd1ab9a56de 100644 --- a/drivers/mfd/zl3073x.h +++ b/drivers/mfd/zl3073x.h @@ -26,6 +26,6 @@ extern const struct zl3073x_chip_info zl3073x_chip_info[]; struct zl3073x_dev *zl3073x_devm_alloc(struct device *dev); void zl3073x_dev_init_regmap_config(struct regmap_config *regmap_cfg); int zl3073x_dev_probe(struct zl3073x_dev *zldev, - const struct zl3073x_chip_info *chip_info); + const struct zl3073x_chip_info *chip_info, u8 dev_id); =20 #endif /* __ZL3073X_CORE_H */ diff --git a/include/linux/mfd/zl3073x.h b/include/linux/mfd/zl3073x.h index da4b7ae6a89e..1512e8c7cc7b 100644 --- a/include/linux/mfd/zl3073x.h +++ b/include/linux/mfd/zl3073x.h @@ -53,6 +53,7 @@ struct zl3073x_synth { * @dev: pointer to device * @regmap: regmap to access device registers * @multiop_lock: to serialize multiple register operations + * @clock_id: clock id of the device * @input: array of inputs' invariants * @output: array of outputs' invariants * @synth: array of synthesizers' invariants @@ -61,6 +62,7 @@ struct zl3073x_dev { struct device *dev; struct regmap *regmap; struct mutex multiop_lock; + u64 clock_id; =20 /* Invariants */ struct zl3073x_input input[ZL3073X_NUM_INPUTS]; --=20 2.49.0 From nobody Sun Feb 8 07:07:16 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBFC525A32A for ; Wed, 30 Apr 2025 10:12:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007943; cv=none; b=os99yGcms/w42kzlZihidZhuuzrlWXaIiWb5XmvH4b7EmhOPiONDc0a6awoeWKD+H8iD0C4IRN7dZikWnuaxj3a5BrZ/VtZzdrp4HcFOnkUVGdutb32CScZG12BYXPNzTk0tTovzMHR41DqyHdfhFWFnPMfa7IV5V6vxIdWVCEw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746007943; c=relaxed/simple; bh=ecy6qqaWhM2xobngJ8fvS5peWhfAmVtAcOtECYDOYpw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KvFd63swOej+SkE/V2EkimvinbrjjN2gd3MejS/aGrta1jaX8jT1F9YFanDmLxl8hcBZ90+QNDvpybGkxl5IVGBmVWhpFTLTmZ+F8ecbGXdTwyWjbUzpes7RRvs64uDxZ+RXpMMDG2d8FsnZ3IncWM6nKrIiAn+m3wqjQHtTtuA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=XnAck9fM; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="XnAck9fM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1746007940; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Djj8tsy+Ba85/DDYqso23/cXw9EWu4CIgtP3vOGRebo=; b=XnAck9fMZyFrvN1r8OSs+tjuUcNimVFH5H33s48lR6gTDHGMfsoXJ+nXiX4VM+ZojP8G38 fmoK0v/eHzqUFFoOz7wFHAzWyFAcx+fFhRCJcwS5vhiLEvy5g5jGsYanrwCEBR4cSp6fab k5mYZDWLCtHc+7Z0JbWwrn9jsYp8U3o= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-509-UUO7kGRMOp2Up6SB1LyAMg-1; Wed, 30 Apr 2025 06:12:17 -0400 X-MC-Unique: UUO7kGRMOp2Up6SB1LyAMg-1 X-Mimecast-MFC-AGG-ID: UUO7kGRMOp2Up6SB1LyAMg_1746007935 Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 648CC19560AA; Wed, 30 Apr 2025 10:12:15 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.44.33.50]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id B53BA1956094; Wed, 30 Apr 2025 10:12:10 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prathosh Satish , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Simon Horman , Lee Jones , Andy Shevchenko , Michal Schmidt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH net-next v6 8/8] mfd: zl3073x: Register DPLL sub-device during init Date: Wed, 30 Apr 2025 12:11:26 +0200 Message-ID: <20250430101126.83708-9-ivecera@redhat.com> In-Reply-To: <20250430101126.83708-1-ivecera@redhat.com> References: <20250430101126.83708-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" Register DPLL sub-devices to expose the functionality provided by ZL3073x chip family. Each sub-device represents one of the available DPLL channels. Signed-off-by: Ivan Vecera --- v4->v6: * no change v3->v4: * use static mfd cells --- drivers/mfd/zl3073x-core.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mfd/zl3073x-core.c b/drivers/mfd/zl3073x-core.c index 050dc57c90c3..3e665cdf228f 100644 --- a/drivers/mfd/zl3073x-core.c +++ b/drivers/mfd/zl3073x-core.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -755,6 +756,14 @@ static void zl3073x_devlink_unregister(void *ptr) devlink_unregister(ptr); } =20 +static const struct mfd_cell zl3073x_dpll_cells[] =3D { + MFD_CELL_BASIC("zl3073x-dpll", NULL, NULL, 0, 0), + MFD_CELL_BASIC("zl3073x-dpll", NULL, NULL, 0, 1), + MFD_CELL_BASIC("zl3073x-dpll", NULL, NULL, 0, 2), + MFD_CELL_BASIC("zl3073x-dpll", NULL, NULL, 0, 3), + MFD_CELL_BASIC("zl3073x-dpll", NULL, NULL, 0, 4), +}; + /** * zl3073x_dev_probe - initialize zl3073x device * @zldev: pointer to zl3073x device @@ -826,6 +835,16 @@ int zl3073x_dev_probe(struct zl3073x_dev *zldev, if (rc) return rc; =20 + /* Add DPLL sub-device cell for each DPLL channel */ + rc =3D devm_mfd_add_devices(zldev->dev, PLATFORM_DEVID_AUTO, + zl3073x_dpll_cells, chip_info->num_channels, + NULL, 0, NULL); + if (rc) { + dev_err_probe(zldev->dev, rc, + "Failed to add DPLL sub-device\n"); + return rc; + } + /* Register the device as devlink device */ devlink =3D priv_to_devlink(zldev); devlink_register(devlink); --=20 2.49.0