From nobody Tue Feb 10 08:27:05 2026 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D56751E4110; Wed, 30 Apr 2025 09:37:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005860; cv=none; b=oY2dXWppXU5RgIUcFy5oEyLFzs0QleQ8OcgCH1P9/hZfHnQye6QeZSVOnCJVWRUoJUWejNnzy7I8IoiWJTPXncB9f4q2UfRsVgU2a02wpf3nxVeBeB/QpKhz6wzx8RNVKwD4/+gFKRofYgcVGY5gHgSF6mW2I6R+Ldnz+VtU8o0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005860; c=relaxed/simple; bh=qxO/xtbbsRETCfRTxQMQ51jc6BVPTrXbzWxsxhpi5PE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mKzvWFxTUQximHnR3tORE76OBj23Ycno2xEKuZUND+2lrZyCY5eigdAtjeLVuOdBEJ/0E9fzEYR0prIGofVYHC2vF8hn8wrb0xAL2l6idWGz9uqA8gop97T3WB+y/60LSXDisdl8Ti3cO3koyGn0K5wGLyy5/NrUTARrmd95Ng0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4ZnXBN2NZ5z13Kxs; Wed, 30 Apr 2025 17:36:28 +0800 (CST) Received: from kwepemk100013.china.huawei.com (unknown [7.202.194.61]) by mail.maildlp.com (Postfix) with ESMTPS id 5DF41180B5F; Wed, 30 Apr 2025 17:37:36 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemk100013.china.huawei.com (7.202.194.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 30 Apr 2025 17:37:35 +0800 From: Jijie Shao To: , , , , , CC: , , , , , , , , , Subject: [PATCH net 4/4] net: hns3: defer calling ptp_clock_register() Date: Wed, 30 Apr 2025 17:30:52 +0800 Message-ID: <20250430093052.2400464-5-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20250430093052.2400464-1-shaojijie@huawei.com> References: <20250430093052.2400464-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemk100013.china.huawei.com (7.202.194.61) Content-Type: text/plain; charset="utf-8" From: Jian Shen Currently the ptp_clock_register() is called before relative ptp resource ready. It may cause unexpected result when upper layer called the ptp API during the timewindow. Fix it by moving the ptp_clock_register() to the function end. Fixes: 0bf5eb788512 ("net: hns3: add support for PTP") Signed-off-by: Jian Shen Signed-off-by: Jijie Shao Reviewed-by: Vadim Fedorenko --- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c b/drive= rs/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c index 59cc9221185f..ec581d4b696f 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c @@ -440,6 +440,13 @@ static int hclge_ptp_create_clock(struct hclge_dev *hd= ev) ptp->info.settime64 =3D hclge_ptp_settime; =20 ptp->info.n_alarm =3D 0; + + spin_lock_init(&ptp->lock); + ptp->io_base =3D hdev->hw.hw.io_base + HCLGE_PTP_REG_OFFSET; + ptp->ts_cfg.rx_filter =3D HWTSTAMP_FILTER_NONE; + ptp->ts_cfg.tx_type =3D HWTSTAMP_TX_OFF; + hdev->ptp =3D ptp; + ptp->clock =3D ptp_clock_register(&ptp->info, &hdev->pdev->dev); if (IS_ERR(ptp->clock)) { dev_err(&hdev->pdev->dev, @@ -451,12 +458,6 @@ static int hclge_ptp_create_clock(struct hclge_dev *hd= ev) return -ENODEV; } =20 - spin_lock_init(&ptp->lock); - ptp->io_base =3D hdev->hw.hw.io_base + HCLGE_PTP_REG_OFFSET; - ptp->ts_cfg.rx_filter =3D HWTSTAMP_FILTER_NONE; - ptp->ts_cfg.tx_type =3D HWTSTAMP_TX_OFF; - hdev->ptp =3D ptp; - return 0; } =20 --=20 2.33.0