From nobody Mon Feb 9 05:19:24 2026 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D8C4231847; Wed, 30 Apr 2025 09:37:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005859; cv=none; b=QmawMkf+aNluAYCEOig5hpKWcmm/HEpDflo2HpD8LpgwMffdXN61Ps2unTSU92tICKNWiLE9FF6I0Q3UttZPDHvar5khfIqUlRidh8Hd/bkoEYu0fEpZxOoIiKBNePkta42pzOnqnQZP750gHVoQTghJ381rDLbjobDH9CXJEmY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005859; c=relaxed/simple; bh=0v7ilCFkbQmhtmvd1gF7S9J2MIgROCWEV8xJ/yGDEn0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AAQfVnMPZHSR2Vl1JNYJI7QKNdfj6wYREPu/M2bbPvBqdQSSASQhD6NOci16Nnmp+97RUsOSGCQjFZ7p8szliz10Qq1XMgV6nsuYyJqvw17Ih9pWgRrCFRlPv/bwIQ/AaZrHEpA34vmyMyVfxmd8Jd0/ApcODAFdudTfQMMYf0c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4ZnXC91W2vz2TSFP; Wed, 30 Apr 2025 17:37:09 +0800 (CST) Received: from kwepemk100013.china.huawei.com (unknown [7.202.194.61]) by mail.maildlp.com (Postfix) with ESMTPS id AF8221400DA; Wed, 30 Apr 2025 17:37:34 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemk100013.china.huawei.com (7.202.194.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 30 Apr 2025 17:37:34 +0800 From: Jijie Shao To: , , , , , CC: , , , , , , , , , Subject: [PATCH net 1/4] net: hns3: store rx VLAN tag offload state for VF Date: Wed, 30 Apr 2025 17:30:49 +0800 Message-ID: <20250430093052.2400464-2-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20250430093052.2400464-1-shaojijie@huawei.com> References: <20250430093052.2400464-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemk100013.china.huawei.com (7.202.194.61) Content-Type: text/plain; charset="utf-8" From: Jian Shen The VF driver missed to store the rx VLAN tag strip state when user change the rx VLAN tag offload state. And it will default to enable the rx vlan tag strip when re-init VF device after reset. So if user disable rx VLAN tag offload, and trig reset, then the HW will still strip the VLAN tag from packet nad fill into RX BD, but the VF driver will ignore it for rx VLAN tag offload disabled. It may cause the rx VLAN tag dropped. Fixes: b2641e2ad456 ("net: hns3: Add support of hardware rx-vlan-offload to= HNS3 VF driver") Signed-off-by: Jian Shen Signed-off-by: Jijie Shao Reviewed-by: Simon Horman --- .../hisilicon/hns3/hns3vf/hclgevf_main.c | 25 ++++++++++++++----- .../hisilicon/hns3/hns3vf/hclgevf_main.h | 1 + 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/dr= ivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c index 9ba767740a04..dada42e7e0ec 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c @@ -1292,9 +1292,8 @@ static void hclgevf_sync_vlan_filter(struct hclgevf_d= ev *hdev) rtnl_unlock(); } =20 -static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool en= able) +static int hclgevf_en_hw_strip_rxvtag_cmd(struct hclgevf_dev *hdev, bool e= nable) { - struct hclgevf_dev *hdev =3D hclgevf_ae_get_hdev(handle); struct hclge_vf_to_pf_msg send_msg; =20 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, @@ -1303,6 +1302,19 @@ static int hclgevf_en_hw_strip_rxvtag(struct hnae3_h= andle *handle, bool enable) return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); } =20 +static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool en= able) +{ + struct hclgevf_dev *hdev =3D hclgevf_ae_get_hdev(handle); + int ret; + + ret =3D hclgevf_en_hw_strip_rxvtag_cmd(hdev, enable); + if (ret) + return ret; + + hdev->rxvtag_strip_en =3D enable; + return 0; +} + static int hclgevf_reset_tqp(struct hnae3_handle *handle) { #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U @@ -2204,12 +2216,13 @@ static int hclgevf_rss_init_hw(struct hclgevf_dev *= hdev) tc_valid, tc_size); } =20 -static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) +static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev, + bool rxvtag_strip_en) { struct hnae3_handle *nic =3D &hdev->nic; int ret; =20 - ret =3D hclgevf_en_hw_strip_rxvtag(nic, true); + ret =3D hclgevf_en_hw_strip_rxvtag(nic, rxvtag_strip_en); if (ret) { dev_err(&hdev->pdev->dev, "failed to enable rx vlan offload, ret =3D %d\n", ret); @@ -2879,7 +2892,7 @@ static int hclgevf_reset_hdev(struct hclgevf_dev *hde= v) if (ret) return ret; =20 - ret =3D hclgevf_init_vlan_config(hdev); + ret =3D hclgevf_init_vlan_config(hdev, hdev->rxvtag_strip_en); if (ret) { dev_err(&hdev->pdev->dev, "failed(%d) to initialize VLAN config\n", ret); @@ -2994,7 +3007,7 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev) goto err_config; } =20 - ret =3D hclgevf_init_vlan_config(hdev); + ret =3D hclgevf_init_vlan_config(hdev, true); if (ret) { dev_err(&hdev->pdev->dev, "failed(%d) to initialize VLAN config\n", ret); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/dr= ivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h index cccef3228461..0208425ab594 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h @@ -253,6 +253,7 @@ struct hclgevf_dev { int *vector_irq; =20 bool gro_en; + bool rxvtag_strip_en; =20 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; =20 --=20 2.33.0 From nobody Mon Feb 9 05:19:24 2026 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E8A7231856; Wed, 30 Apr 2025 09:37:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005860; cv=none; b=cJf5eiVaycubksM0LKyZWPVNiehIFL/+ItaUL9APATEeIXSTPKA3JUG+nDzeVZuSsgA5nVMsUKAQHRTm5AOaIOcwAU1k+ZXgFlLig4Oep4RbPxUsKvoScWiRnKXCaW3XdZmMEfsZBrOg5yUn4FJSDkXtnRLnXrwQBUNHiIqwLQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005860; c=relaxed/simple; bh=AVe8bi1I1ViZWvopug5JZatl5xXWmJufC4tlm4oZN08=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Wed, 30 Apr 2025 17:37:34 +0800 From: Jijie Shao To: , , , , , CC: , , , , , , , , , Subject: [PATCH net 2/4] net: hns3: fix an interrupt residual problem Date: Wed, 30 Apr 2025 17:30:50 +0800 Message-ID: <20250430093052.2400464-3-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20250430093052.2400464-1-shaojijie@huawei.com> References: <20250430093052.2400464-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemk100013.china.huawei.com (7.202.194.61) Content-Type: text/plain; charset="utf-8" From: Yonglong Liu When a VF is passthrough to a VM, and the VM is killed, the reported interrupt may not been handled, it will remain, and won't be clear by the nic engine even with a flr or tqp reset. When the VM restart, the interrupt of the first vector may be dropped by the second enable_irq in vfio, see the issue below: https://gitlab.com/qemu-project/qemu/-/issues/2884#note_2423361621 We notice that the vfio has always behaved this way, and the interrupt is a residue of the nic engine, so we fix the problem by moving the vector enable process out of the enable_irq loop. Fixes: 08a100689d4b ("net: hns3: re-organize vector handle") Signed-off-by: Yonglong Liu Signed-off-by: Jijie Shao --- .../net/ethernet/hisilicon/hns3/hns3_enet.c | 82 +++++++++---------- 1 file changed, 39 insertions(+), 43 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/= ethernet/hisilicon/hns3/hns3_enet.c index 9ff797fb36c4..b03b8758c777 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c @@ -473,20 +473,14 @@ static void hns3_mask_vector_irq(struct hns3_enet_tqp= _vector *tqp_vector, writel(mask_en, tqp_vector->mask_addr); } =20 -static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) +static void hns3_irq_enable(struct hns3_enet_tqp_vector *tqp_vector) { napi_enable(&tqp_vector->napi); enable_irq(tqp_vector->vector_irq); - - /* enable vector */ - hns3_mask_vector_irq(tqp_vector, 1); } =20 -static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) +static void hns3_irq_disable(struct hns3_enet_tqp_vector *tqp_vector) { - /* disable vector */ - hns3_mask_vector_irq(tqp_vector, 0); - disable_irq(tqp_vector->vector_irq); napi_disable(&tqp_vector->napi); cancel_work_sync(&tqp_vector->rx_group.dim.work); @@ -707,11 +701,42 @@ static int hns3_set_rx_cpu_rmap(struct net_device *ne= tdev) return 0; } =20 +static void hns3_enable_irqs_and_tqps(struct net_device *netdev) +{ + struct hns3_nic_priv *priv =3D netdev_priv(netdev); + struct hnae3_handle *h =3D priv->ae_handle; + u16 i; + + for (i =3D 0; i < priv->vector_num; i++) + hns3_irq_enable(&priv->tqp_vector[i]); + + for (i =3D 0; i < priv->vector_num; i++) + hns3_mask_vector_irq(&priv->tqp_vector[i], 1); + + for (i =3D 0; i < h->kinfo.num_tqps; i++) + hns3_tqp_enable(h->kinfo.tqp[i]); +} + +static void hns3_disable_irqs_and_tqps(struct net_device *netdev) +{ + struct hns3_nic_priv *priv =3D netdev_priv(netdev); + struct hnae3_handle *h =3D priv->ae_handle; + u16 i; + + for (i =3D 0; i < h->kinfo.num_tqps; i++) + hns3_tqp_disable(h->kinfo.tqp[i]); + + for (i =3D 0; i < priv->vector_num; i++) + hns3_mask_vector_irq(&priv->tqp_vector[i], 0); + + for (i =3D 0; i < priv->vector_num; i++) + hns3_irq_disable(&priv->tqp_vector[i]); +} + static int hns3_nic_net_up(struct net_device *netdev) { struct hns3_nic_priv *priv =3D netdev_priv(netdev); struct hnae3_handle *h =3D priv->ae_handle; - int i, j; int ret; =20 ret =3D hns3_nic_reset_all_ring(h); @@ -720,23 +745,13 @@ static int hns3_nic_net_up(struct net_device *netdev) =20 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); =20 - /* enable the vectors */ - for (i =3D 0; i < priv->vector_num; i++) - hns3_vector_enable(&priv->tqp_vector[i]); - - /* enable rcb */ - for (j =3D 0; j < h->kinfo.num_tqps; j++) - hns3_tqp_enable(h->kinfo.tqp[j]); + hns3_enable_irqs_and_tqps(netdev); =20 /* start the ae_dev */ ret =3D h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; if (ret) { set_bit(HNS3_NIC_STATE_DOWN, &priv->state); - while (j--) - hns3_tqp_disable(h->kinfo.tqp[j]); - - for (j =3D i - 1; j >=3D 0; j--) - hns3_vector_disable(&priv->tqp_vector[j]); + hns3_disable_irqs_and_tqps(netdev); } =20 return ret; @@ -823,17 +838,9 @@ static void hns3_reset_tx_queue(struct hnae3_handle *h) static void hns3_nic_net_down(struct net_device *netdev) { struct hns3_nic_priv *priv =3D netdev_priv(netdev); - struct hnae3_handle *h =3D hns3_get_handle(netdev); const struct hnae3_ae_ops *ops; - int i; =20 - /* disable vectors */ - for (i =3D 0; i < priv->vector_num; i++) - hns3_vector_disable(&priv->tqp_vector[i]); - - /* disable rcb */ - for (i =3D 0; i < h->kinfo.num_tqps; i++) - hns3_tqp_disable(h->kinfo.tqp[i]); + hns3_disable_irqs_and_tqps(netdev); =20 /* stop ae_dev */ ops =3D priv->ae_handle->ae_algo->ops; @@ -5864,8 +5871,6 @@ int hns3_set_channels(struct net_device *netdev, void hns3_external_lb_prepare(struct net_device *ndev, bool if_running) { struct hns3_nic_priv *priv =3D netdev_priv(ndev); - struct hnae3_handle *h =3D priv->ae_handle; - int i; =20 if (!if_running) return; @@ -5876,11 +5881,7 @@ void hns3_external_lb_prepare(struct net_device *nde= v, bool if_running) netif_carrier_off(ndev); netif_tx_disable(ndev); =20 - for (i =3D 0; i < priv->vector_num; i++) - hns3_vector_disable(&priv->tqp_vector[i]); - - for (i =3D 0; i < h->kinfo.num_tqps; i++) - hns3_tqp_disable(h->kinfo.tqp[i]); + hns3_disable_irqs_and_tqps(ndev); =20 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet * during reset process, because driver may not be able @@ -5896,7 +5897,6 @@ void hns3_external_lb_restore(struct net_device *ndev= , bool if_running) { struct hns3_nic_priv *priv =3D netdev_priv(ndev); struct hnae3_handle *h =3D priv->ae_handle; - int i; =20 if (!if_running) return; @@ -5912,11 +5912,7 @@ void hns3_external_lb_restore(struct net_device *nde= v, bool if_running) =20 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); =20 - for (i =3D 0; i < priv->vector_num; i++) - hns3_vector_enable(&priv->tqp_vector[i]); - - for (i =3D 0; i < h->kinfo.num_tqps; i++) - hns3_tqp_enable(h->kinfo.tqp[i]); + hns3_enable_irqs_and_tqps(ndev); =20 netif_tx_wake_all_queues(ndev); =20 --=20 2.33.0 From nobody Mon Feb 9 05:19:24 2026 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3AFA23814A; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4ZnX7b0cYhzLpfn; Wed, 30 Apr 2025 17:34:03 +0800 (CST) Received: from kwepemk100013.china.huawei.com (unknown [7.202.194.61]) by mail.maildlp.com (Postfix) with ESMTPS id CA5F71400D4; Wed, 30 Apr 2025 17:37:35 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemk100013.china.huawei.com (7.202.194.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 30 Apr 2025 17:37:35 +0800 From: Jijie Shao To: , , , , , CC: , , , , , , , , , Subject: [PATCH net 3/4] net: hns3: fixed debugfs tm_qset size Date: Wed, 30 Apr 2025 17:30:51 +0800 Message-ID: <20250430093052.2400464-4-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20250430093052.2400464-1-shaojijie@huawei.com> References: <20250430093052.2400464-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemk100013.china.huawei.com (7.202.194.61) Content-Type: text/plain; charset="utf-8" From: Hao Lan The size of the tm_qset file of debugfs is limited to 64 KB, which is too small in the scenario with 1280 qsets. The size needs to be expanded to 1 MB. Fixes: 5e69ea7ee2a6 ("net: hns3: refactor the debugfs process") Signed-off-by: Hao Lan Signed-off-by: Peiyang Wang Signed-off-by: Jijie Shao --- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/n= et/ethernet/hisilicon/hns3/hns3_debugfs.c index 09749e9f7398..4e5d8bc39a1b 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c @@ -61,7 +61,7 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] =3D { .name =3D "tm_qset", .cmd =3D HNAE3_DBG_CMD_TM_QSET, .dentry =3D HNS3_DBG_DENTRY_TM, - .buf_len =3D HNS3_DBG_READ_LEN, + .buf_len =3D HNS3_DBG_READ_LEN_1MB, .init =3D hns3_dbg_common_file_init, }, { --=20 2.33.0 From nobody Mon Feb 9 05:19:24 2026 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D56751E4110; Wed, 30 Apr 2025 09:37:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005860; cv=none; b=oY2dXWppXU5RgIUcFy5oEyLFzs0QleQ8OcgCH1P9/hZfHnQye6QeZSVOnCJVWRUoJUWejNnzy7I8IoiWJTPXncB9f4q2UfRsVgU2a02wpf3nxVeBeB/QpKhz6wzx8RNVKwD4/+gFKRofYgcVGY5gHgSF6mW2I6R+Ldnz+VtU8o0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746005860; c=relaxed/simple; bh=qxO/xtbbsRETCfRTxQMQ51jc6BVPTrXbzWxsxhpi5PE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mKzvWFxTUQximHnR3tORE76OBj23Ycno2xEKuZUND+2lrZyCY5eigdAtjeLVuOdBEJ/0E9fzEYR0prIGofVYHC2vF8hn8wrb0xAL2l6idWGz9uqA8gop97T3WB+y/60LSXDisdl8Ti3cO3koyGn0K5wGLyy5/NrUTARrmd95Ng0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4ZnXBN2NZ5z13Kxs; Wed, 30 Apr 2025 17:36:28 +0800 (CST) Received: from kwepemk100013.china.huawei.com (unknown [7.202.194.61]) by mail.maildlp.com (Postfix) with ESMTPS id 5DF41180B5F; Wed, 30 Apr 2025 17:37:36 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemk100013.china.huawei.com (7.202.194.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 30 Apr 2025 17:37:35 +0800 From: Jijie Shao To: , , , , , CC: , , , , , , , , , Subject: [PATCH net 4/4] net: hns3: defer calling ptp_clock_register() Date: Wed, 30 Apr 2025 17:30:52 +0800 Message-ID: <20250430093052.2400464-5-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20250430093052.2400464-1-shaojijie@huawei.com> References: <20250430093052.2400464-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemk100013.china.huawei.com (7.202.194.61) Content-Type: text/plain; charset="utf-8" From: Jian Shen Currently the ptp_clock_register() is called before relative ptp resource ready. It may cause unexpected result when upper layer called the ptp API during the timewindow. Fix it by moving the ptp_clock_register() to the function end. Fixes: 0bf5eb788512 ("net: hns3: add support for PTP") Signed-off-by: Jian Shen Signed-off-by: Jijie Shao Reviewed-by: Vadim Fedorenko --- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c b/drive= rs/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c index 59cc9221185f..ec581d4b696f 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c @@ -440,6 +440,13 @@ static int hclge_ptp_create_clock(struct hclge_dev *hd= ev) ptp->info.settime64 =3D hclge_ptp_settime; =20 ptp->info.n_alarm =3D 0; + + spin_lock_init(&ptp->lock); + ptp->io_base =3D hdev->hw.hw.io_base + HCLGE_PTP_REG_OFFSET; + ptp->ts_cfg.rx_filter =3D HWTSTAMP_FILTER_NONE; + ptp->ts_cfg.tx_type =3D HWTSTAMP_TX_OFF; + hdev->ptp =3D ptp; + ptp->clock =3D ptp_clock_register(&ptp->info, &hdev->pdev->dev); if (IS_ERR(ptp->clock)) { dev_err(&hdev->pdev->dev, @@ -451,12 +458,6 @@ static int hclge_ptp_create_clock(struct hclge_dev *hd= ev) return -ENODEV; } =20 - spin_lock_init(&ptp->lock); - ptp->io_base =3D hdev->hw.hw.io_base + HCLGE_PTP_REG_OFFSET; - ptp->ts_cfg.rx_filter =3D HWTSTAMP_FILTER_NONE; - ptp->ts_cfg.tx_type =3D HWTSTAMP_TX_OFF; - hdev->ptp =3D ptp; - return 0; } =20 --=20 2.33.0