From nobody Sat Feb 7 21:24:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0065225D6 for ; Wed, 30 Apr 2025 02:12:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745979152; cv=none; b=Rd2VpDUPXStzCwkncwGedfwQI3HkE5tkAiQZsqn/A3m3ajyMlT244GICQQaJQ2WLMGt9uoK6OrX0gImJrPHB9UEmtGoOb8kMrObGwctD7vAoBKNMKuGZIJYTEpos93nWq7jxZMgdsXkWtrL6kpKbxYqMQzzjpaM7+DysOplAsBQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745979152; c=relaxed/simple; bh=TsW6iiQMHrbRcDeOb2lZOXIeT7zOl9AAlV1AoMoXfRw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Pu/Y69KNJqu+pR9OSQLBPrQeg4vblgm+X31yD319UBaFsrhUqOd152YJSC/+CcxIV3DMg+OgyG2Xee4OuhTNLTTtei6w840JGUHoypFZDAAzqgRRpUMw+ocdHbVLBdYvI9ZEJnZgDzGxIfQZkbXE69+ylxniLTGljgj6jcxIh6M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hWd3DdM3; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hWd3DdM3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745979151; x=1777515151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TsW6iiQMHrbRcDeOb2lZOXIeT7zOl9AAlV1AoMoXfRw=; b=hWd3DdM3zr1oooe/SwFXVc66MlMBxfs1TutR5e6evlon9JZU9inJC5kJ s3jC9y4WavGdXHnqfouZZ53OFoKBDE7yBNOw1KQsISX9g323xWvmuGQIP sU3ftKvPjJDOpDhnxpbNscYwV/KyTtt11GNP/oodLYct+R4EZJgj45IMP 0ciCqy2uwYRuT7u92iwhkx4q6HdIxnpSrxf9ylRaN9/j1z5BJu95cT52+ BZQbYcK59j+i7glW3c0yiFsZ5qGFb9iRsuqVp4mm3yiguEk/jtPuhwol1 OXKiWaQsBuHEfMOgOpDsHb6F6cds5SL0Jp7Xp4xgub38M/ocOau6TXXkz Q==; X-CSE-ConnectionGUID: PRdpQR1tSuK694LQhQBl0g== X-CSE-MsgGUID: wD5yQArvTXCk0Sfz1cN0/A== X-IronPort-AV: E=McAfee;i="6700,10204,11418"; a="51288503" X-IronPort-AV: E=Sophos;i="6.15,250,1739865600"; d="scan'208";a="51288503" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2025 19:11:07 -0700 X-CSE-ConnectionGUID: Ot3vTq4aRmy6eNFfo25DYA== X-CSE-MsgGUID: ws3JhXoOQsCWcIt9shNF/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,250,1739865600"; d="scan'208";a="134303443" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa008.fm.intel.com with ESMTP; 29 Apr 2025 19:11:04 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 1/2] iommu/vt-d: Use ida to manage domain id Date: Wed, 30 Apr 2025 10:11:34 +0800 Message-ID: <20250430021135.2370244-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430021135.2370244-1-baolu.lu@linux.intel.com> References: <20250430021135.2370244-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch the intel iommu driver to use the ida mechanism for managing domain IDs, replacing the previous fixed-size bitmap. The previous approach allocated a bitmap large enough to cover the maximum number of domain IDs supported by the hardware, regardless of the actual number of domains in use. This led to unnecessary memory consumption, especially on systems supporting a large number of iommu units but only utilizing a small number of domain IDs. The ida allocator dynamically manages the allocation and freeing of integer IDs, only consuming memory for the IDs that are currently in use. This significantly optimizes memory usage compared to the fixed-size bitmap. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe --- drivers/iommu/intel/dmar.c | 3 ++ drivers/iommu/intel/iommu.c | 80 ++++++++----------------------------- drivers/iommu/intel/iommu.h | 19 +++++++-- 3 files changed, 34 insertions(+), 68 deletions(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index e540092d664d..0e35969c026b 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1099,6 +1099,8 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) spin_lock_init(&iommu->device_rbtree_lock); mutex_init(&iommu->iopf_lock); iommu->node =3D NUMA_NO_NODE; + spin_lock_init(&iommu->lock); + ida_init(&iommu->domain_ida); =20 ver =3D readl(iommu->reg + DMAR_VER_REG); pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", @@ -1195,6 +1197,7 @@ static void free_iommu(struct intel_iommu *iommu) if (iommu->reg) unmap_iommu(iommu); =20 + ida_destroy(&iommu->domain_ida); ida_free(&dmar_seq_ids, iommu->seq_id); kfree(iommu); } diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index b29da2d96d0b..39832d2125be 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1289,52 +1289,13 @@ static void iommu_disable_translation(struct intel_= iommu *iommu) raw_spin_unlock_irqrestore(&iommu->register_lock, flag); } =20 -static int iommu_init_domains(struct intel_iommu *iommu) -{ - u32 ndomains; - - ndomains =3D cap_ndoms(iommu->cap); - pr_debug("%s: Number of Domains supported <%d>\n", - iommu->name, ndomains); - - spin_lock_init(&iommu->lock); - - iommu->domain_ids =3D bitmap_zalloc(ndomains, GFP_KERNEL); - if (!iommu->domain_ids) - return -ENOMEM; - - /* - * If Caching mode is set, then invalid translations are tagged - * with domain-id 0, hence we need to pre-allocate it. We also - * use domain-id 0 as a marker for non-allocated domain-id, so - * make sure it is not used for a real domain. - */ - set_bit(0, iommu->domain_ids); - - /* - * Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid - * entry for first-level or pass-through translation modes should - * be programmed with a domain id different from those used for - * second-level or nested translation. We reserve a domain id for - * this purpose. This domain id is also used for identity domain - * in legacy mode. - */ - set_bit(FLPT_DEFAULT_DID, iommu->domain_ids); - - return 0; -} - static void disable_dmar_iommu(struct intel_iommu *iommu) { - if (!iommu->domain_ids) - return; - /* * All iommu domains must have been detached from the devices, * hence there should be no domain IDs in use. */ - if (WARN_ON(bitmap_weight(iommu->domain_ids, cap_ndoms(iommu->cap)) - > NUM_RESERVED_DID)) + if (WARN_ON(!ida_is_empty(&iommu->domain_ida))) return; =20 if (iommu->gcmd & DMA_GCMD_TE) @@ -1343,11 +1304,6 @@ static void disable_dmar_iommu(struct intel_iommu *i= ommu) =20 static void free_dmar_iommu(struct intel_iommu *iommu) { - if (iommu->domain_ids) { - bitmap_free(iommu->domain_ids); - iommu->domain_ids =3D NULL; - } - if (iommu->copied_tables) { bitmap_free(iommu->copied_tables); iommu->copied_tables =3D NULL; @@ -1380,7 +1336,6 @@ static bool first_level_by_default(struct intel_iommu= *iommu) int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *io= mmu) { struct iommu_domain_info *info, *curr; - unsigned long ndomains; int num, ret =3D -ENOSPC; =20 if (domain->domain.type =3D=3D IOMMU_DOMAIN_SVA) @@ -1399,14 +1354,13 @@ int domain_attach_iommu(struct dmar_domain *domain,= struct intel_iommu *iommu) return 0; } =20 - ndomains =3D cap_ndoms(iommu->cap); - num =3D find_first_zero_bit(iommu->domain_ids, ndomains); - if (num >=3D ndomains) { + num =3D ida_alloc_range(&iommu->domain_ida, IDA_START_DID, + cap_ndoms(iommu->cap) - 1, GFP_ATOMIC); + if (num < 0) { pr_err("%s: No free domain ids\n", iommu->name); goto err_unlock; } =20 - set_bit(num, iommu->domain_ids); info->refcnt =3D 1; info->did =3D num; info->iommu =3D iommu; @@ -1421,7 +1375,7 @@ int domain_attach_iommu(struct dmar_domain *domain, s= truct intel_iommu *iommu) return 0; =20 err_clear: - clear_bit(info->did, iommu->domain_ids); + ida_free(&iommu->domain_ida, info->did); err_unlock: spin_unlock(&iommu->lock); kfree(info); @@ -1438,7 +1392,7 @@ void domain_detach_iommu(struct dmar_domain *domain, = struct intel_iommu *iommu) spin_lock(&iommu->lock); info =3D xa_load(&domain->iommu_array, iommu->seq_id); if (--info->refcnt =3D=3D 0) { - clear_bit(info->did, iommu->domain_ids); + ida_free(&iommu->domain_ida, info->did); xa_erase(&domain->iommu_array, iommu->seq_id); domain->nid =3D NUMA_NO_NODE; kfree(info); @@ -2042,7 +1996,7 @@ static int copy_context_table(struct intel_iommu *iom= mu, =20 did =3D context_domain_id(&ce); if (did >=3D 0 && did < cap_ndoms(iommu->cap)) - set_bit(did, iommu->domain_ids); + ida_alloc_range(&iommu->domain_ida, did, did, GFP_KERNEL); =20 set_context_copied(iommu, bus, devfn); new_ce[idx] =3D ce; @@ -2169,11 +2123,6 @@ static int __init init_dmars(void) } =20 intel_iommu_init_qi(iommu); - - ret =3D iommu_init_domains(iommu); - if (ret) - goto free_iommu; - init_translation_status(iommu); =20 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { @@ -2651,9 +2600,7 @@ static int intel_iommu_add(struct dmar_drhd_unit *dma= ru) if (iommu->gcmd & DMA_GCMD_TE) iommu_disable_translation(iommu); =20 - ret =3D iommu_init_domains(iommu); - if (ret =3D=3D 0) - ret =3D iommu_alloc_root_entry(iommu); + ret =3D iommu_alloc_root_entry(iommu); if (ret) goto out; =20 @@ -2972,9 +2919,14 @@ static ssize_t domains_used_show(struct device *dev, struct device_attribute *attr, char *buf) { struct intel_iommu *iommu =3D dev_to_intel_iommu(dev); - return sysfs_emit(buf, "%d\n", - bitmap_weight(iommu->domain_ids, - cap_ndoms(iommu->cap))); + unsigned int count =3D 0; + int id; + + for (id =3D 0; id < cap_ndoms(iommu->cap); id++) + if (ida_exists(&iommu->domain_ida, id)) + count++; + + return sysfs_emit(buf, "%d\n", count); } static DEVICE_ATTR_RO(domains_used); =20 diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index c4916886da5a..25faf3aadd24 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -722,7 +722,7 @@ struct intel_iommu { unsigned char name[16]; /* Device Name */ =20 #ifdef CONFIG_INTEL_IOMMU - unsigned long *domain_ids; /* bitmap of domains */ + struct ida domain_ida; /* domain id allocator */ unsigned long *copied_tables; /* bitmap of copied tables */ spinlock_t lock; /* protect context, domain ids */ struct root_entry *root_entry; /* virtual address */ @@ -809,11 +809,22 @@ static inline struct dmar_domain *to_dmar_domain(stru= ct iommu_domain *dom) } =20 /* - * Domain ID reserved for pasid entries programmed for first-level - * only and pass-through transfer modes. + * Domain ID 0 and 1 are reserved: + * + * If Caching mode is set, then invalid translations are tagged + * with domain-id 0, hence we need to pre-allocate it. We also + * use domain-id 0 as a marker for non-allocated domain-id, so + * make sure it is not used for a real domain. + * + * Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid + * entry for first-level or pass-through translation modes should + * be programmed with a domain id different from those used for + * second-level or nested translation. We reserve a domain id for + * this purpose. This domain id is also used for identity domain + * in legacy mode. */ #define FLPT_DEFAULT_DID 1 -#define NUM_RESERVED_DID 2 +#define IDA_START_DID 2 =20 /* Retrieve the domain ID which has allocated to the domain */ static inline u16 --=20 2.43.0 From nobody Sat Feb 7 21:24:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6BB4136672 for ; Wed, 30 Apr 2025 02:12:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745979163; cv=none; b=OK7PhHmHAyKYQurfCPxRuhlTOXG0NZNh/V4nEADhW8N18kj5+GGL3C27/Rs5gttRyxM2ppe7dHMLJYXFMCJFcZJjzi4608rSpD4uUrPpQcMbvOVAJNfXfLZG+qLPXjLDuI6HuTcy7UagG8M+jzV5ul+NWb86YuGds9R3PxZdqtE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745979163; c=relaxed/simple; bh=FM02bmLzHhRN90m6daMRPbkQqrtiylJ5mWsbFxoCrZE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CAH3892+YBoGI2fp7aN1ThWz/Ip2WfFLulQXtExYQnXIBTRu8yvNichp6zhwSpkoxpYJ5M0XQYfmpJc+KnRfOiIor/YO3x7pk4VPFsllzfp6SycSfi1Tb9GX0b9dQ6bNvALGwQkiM+IlUbhI667i4yRzUehggi8Ni6o9fki0b/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EpRTYGCj; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EpRTYGCj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745979162; x=1777515162; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FM02bmLzHhRN90m6daMRPbkQqrtiylJ5mWsbFxoCrZE=; b=EpRTYGCjOrj0wrYzzOTnS8CTQIU81ZOuqPb7OcUz8wpksZJUtrdQyi8l Sl4l3RSOUde9/oJO9yfXONlws3UkFTAs4PUZptfpEWWVmypAkw9d1MmFg y+QSQ8C6ESiEdAE1x0bQPFG+Lf6dBA2IRyXNWoVjiksaxv/x6BllH8HDw Ub4DUWLYs2j0grKljc+JVuL4N2ygoW6lqE5iXau/YTRdcqfBhWy/04WRU V7PACsMG2JIsC91kykkj0SWAk7Fsy6PRygKU74j6EKxNWRjjFCcWOvgs5 owm7gy6AhvWBVtHHthm7pZQMWTqHYAvDIRkbR47XKyP1qlhMASlV2uG9Y Q==; X-CSE-ConnectionGUID: itrveXiOR32KN77B+8QaUQ== X-CSE-MsgGUID: Xb4lZPESTde/otrFXoJ2zw== X-IronPort-AV: E=McAfee;i="6700,10204,11418"; a="51288592" X-IronPort-AV: E=Sophos;i="6.15,250,1739865600"; d="scan'208";a="51288592" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2025 19:11:09 -0700 X-CSE-ConnectionGUID: t+c1xYagRt6BEnpPgqHVmA== X-CSE-MsgGUID: tCMvU5U8TQePZATUwOhbeA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,250,1739865600"; d="scan'208";a="134303468" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa008.fm.intel.com with ESMTP; 29 Apr 2025 19:11:06 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 2/2] iommu/vt-d: Replace spin_lock with mutex to protect domain ida Date: Wed, 30 Apr 2025 10:11:35 +0800 Message-ID: <20250430021135.2370244-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430021135.2370244-1-baolu.lu@linux.intel.com> References: <20250430021135.2370244-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The domain ID allocator is currently protected by a spin_lock. However, ida_alloc_range can potentially block if it needs to allocate memory to grow its internal structures. Replace the spin_lock with a mutex which allows sleep on block. Thus, the memory allocation flags can be updated from GFP_ATOMIC to GFP_KERNEL to allow blocking memory allocations if necessary. Introduce a new mutex, did_lock, specifically for protecting the domain ida. The existing spinlock will remain for protecting other intel_iommu fields. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe --- drivers/iommu/intel/dmar.c | 1 + drivers/iommu/intel/iommu.c | 12 ++++-------- drivers/iommu/intel/iommu.h | 2 ++ 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index 0e35969c026b..9e17e8e56308 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1101,6 +1101,7 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) iommu->node =3D NUMA_NO_NODE; spin_lock_init(&iommu->lock); ida_init(&iommu->domain_ida); + mutex_init(&iommu->did_lock); =20 ver =3D readl(iommu->reg + DMAR_VER_REG); pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 39832d2125be..d117417975d8 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1345,17 +1345,16 @@ int domain_attach_iommu(struct dmar_domain *domain,= struct intel_iommu *iommu) if (!info) return -ENOMEM; =20 - spin_lock(&iommu->lock); + guard(mutex)(&iommu->did_lock); curr =3D xa_load(&domain->iommu_array, iommu->seq_id); if (curr) { curr->refcnt++; - spin_unlock(&iommu->lock); kfree(info); return 0; } =20 num =3D ida_alloc_range(&iommu->domain_ida, IDA_START_DID, - cap_ndoms(iommu->cap) - 1, GFP_ATOMIC); + cap_ndoms(iommu->cap) - 1, GFP_KERNEL); if (num < 0) { pr_err("%s: No free domain ids\n", iommu->name); goto err_unlock; @@ -1365,19 +1364,17 @@ int domain_attach_iommu(struct dmar_domain *domain,= struct intel_iommu *iommu) info->did =3D num; info->iommu =3D iommu; curr =3D xa_cmpxchg(&domain->iommu_array, iommu->seq_id, - NULL, info, GFP_ATOMIC); + NULL, info, GFP_KERNEL); if (curr) { ret =3D xa_err(curr) ? : -EBUSY; goto err_clear; } =20 - spin_unlock(&iommu->lock); return 0; =20 err_clear: ida_free(&iommu->domain_ida, info->did); err_unlock: - spin_unlock(&iommu->lock); kfree(info); return ret; } @@ -1389,7 +1386,7 @@ void domain_detach_iommu(struct dmar_domain *domain, = struct intel_iommu *iommu) if (domain->domain.type =3D=3D IOMMU_DOMAIN_SVA) return; =20 - spin_lock(&iommu->lock); + guard(mutex)(&iommu->did_lock); info =3D xa_load(&domain->iommu_array, iommu->seq_id); if (--info->refcnt =3D=3D 0) { ida_free(&iommu->domain_ida, info->did); @@ -1397,7 +1394,6 @@ void domain_detach_iommu(struct dmar_domain *domain, = struct intel_iommu *iommu) domain->nid =3D NUMA_NO_NODE; kfree(info); } - spin_unlock(&iommu->lock); } =20 static void domain_exit(struct dmar_domain *domain) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 25faf3aadd24..5f140892fae0 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -722,6 +722,8 @@ struct intel_iommu { unsigned char name[16]; /* Device Name */ =20 #ifdef CONFIG_INTEL_IOMMU + /* mutex to protect domain_ida */ + struct mutex did_lock; struct ida domain_ida; /* domain id allocator */ unsigned long *copied_tables; /* bitmap of copied tables */ spinlock_t lock; /* protect context, domain ids */ --=20 2.43.0