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Tue, 29 Apr 2025 18:27:24 -0700 (PDT) From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Chen Wang , Inochi Amaoto , Alexander Sverdlin , Thomas Bonnefille Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH 4/4] riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number Date: Wed, 30 Apr 2025 09:26:53 +0800 Message-ID: <20250430012654.235830-5-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250430012654.235830-1-inochiama@gmail.com> References: <20250430012654.235830-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since riscv and arm architecture use different interrupt definitions, use a macro SOC_PERIPHERAL_IRQ mask this difference. Signed-off-by: Alexander Sverdlin Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 ++ arch/riscv/boot/dts/sophgo/cv180x.dtsi | 44 ++++++++++++------------- arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 2 ++ arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +- arch/riscv/boot/dts/sophgo/sg2002.dtsi | 2 ++ 5 files changed, 29 insertions(+), 23 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi index d0a627c086fb..88707cc13fb4 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2023 Jisheng Zhang */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include "cv180x-cpus.dtsi" #include "cv180x.dtsi" diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/s= ophgo/cv180x.dtsi index a4f957302094..ad5052bf36e5 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -38,7 +38,7 @@ porta: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <60 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -56,7 +56,7 @@ portb: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <61 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -74,7 +74,7 @@ portc: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -92,7 +92,7 @@ portd: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <63 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -100,7 +100,7 @@ saradc: adc@30f0000 { compatible =3D "sophgo,cv1800b-saradc"; reg =3D <0x030f0000 0x1000>; clocks =3D <&clk CLK_SARADC>; - interrupts =3D <100 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -125,7 +125,7 @@ i2c0: i2c@4000000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; clock-names =3D "ref", "pclk"; - interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -136,7 +136,7 @@ i2c1: i2c@4010000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; clock-names =3D "ref", "pclk"; - interrupts =3D <50 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -147,7 +147,7 @@ i2c2: i2c@4020000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; clock-names =3D "ref", "pclk"; - interrupts =3D <51 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -158,7 +158,7 @@ i2c3: i2c@4030000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; clock-names =3D "ref", "pclk"; - interrupts =3D <52 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -169,14 +169,14 @@ i2c4: i2c@4040000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; clock-names =3D "ref", "pclk"; - interrupts =3D <53 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 uart0: serial@4140000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04140000 0x100>; - interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART0>, <&clk CLK_APB_UART0>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -187,7 +187,7 @@ uart0: serial@4140000 { uart1: serial@4150000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04150000 0x100>; - interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART1>, <&clk CLK_APB_UART1>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -198,7 +198,7 @@ uart1: serial@4150000 { uart2: serial@4160000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04160000 0x100>; - interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART2>, <&clk CLK_APB_UART2>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -209,7 +209,7 @@ uart2: serial@4160000 { uart3: serial@4170000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04170000 0x100>; - interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART3>, <&clk CLK_APB_UART3>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -224,7 +224,7 @@ spi0: spi@4180000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <54 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -235,7 +235,7 @@ spi1: spi@4190000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <55 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -246,7 +246,7 @@ spi2: spi@41a0000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <56 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -257,14 +257,14 @@ spi3: spi@41b0000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <57 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 uart4: serial@41c0000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x041c0000 0x100>; - interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART4>, <&clk CLK_APB_UART4>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -275,7 +275,7 @@ uart4: serial@41c0000 { sdhci0: mmc@4310000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4310000 0x1000>; - interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_SD0>, <&clk CLK_SD0>; clock-names =3D "core", "bus"; @@ -285,7 +285,7 @@ sdhci0: mmc@4310000 { sdhci1: mmc@4320000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4320000 0x1000>; - interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_SD1>, <&clk CLK_SD1>; clock-names =3D "core", "bus"; @@ -295,7 +295,7 @@ sdhci1: mmc@4320000 { dmac: dma-controller@4330000 { compatible =3D "snps,axi-dma-1.01a"; reg =3D <0x04330000 0x1000>; - interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; clock-names =3D "core-clk", "cfgr-clk"; #dma-cells =3D <1>; diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/= sophgo/cv1812h.dtsi index d9580a2e1e7f..0974955e4e05 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2023 Inochi Amaoto */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include #include "cv180x-cpus.dtsi" diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/s= ophgo/cv181x.dtsi index 5fd14dd1b14f..bbdb30653e9a 100644 --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi @@ -11,7 +11,7 @@ soc { emmc: mmc@4300000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4300000 0x1000>; - interrupts =3D <34 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_EMMC>, <&clk CLK_EMMC>; clock-names =3D "core", "bus"; diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2002.dtsi index 60709df12a22..6f09c9199102 100644 --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2024 Thomas Bonnefille */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include #include "cv180x-cpus.dtsi" --=20 2.49.0