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Tue, 29 Apr 2025 18:27:14 -0700 (PDT) From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Chen Wang , Inochi Amaoto , Alexander Sverdlin , Thomas Bonnefille Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH 1/4] riscv: dts: sophgo: Move all soc specific device into soc dtsi file Date: Wed, 30 Apr 2025 09:26:50 +0800 Message-ID: <20250430012654.235830-2-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250430012654.235830-1-inochiama@gmail.com> References: <20250430012654.235830-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Although the cv1800b/cv1812h/sg2000/sg2002 share most peripherals, some basic peripherals, like clock, pinctrl, clint and plint, are not shared. These are caused by not only historical reason (plic, clint), but also the fact the device is not the same (clock, pinctrl). It is good to override device compatible when the soc number is small, but now it is a burden for maintenance, and it is kind of annoyed to explain why using override. So it is time to move this out of the common peripheral header. Move all soc related peripherla device from common peripheral header to the soc specific header to get rid of most compatible override. Signed-off-by: Inochi Amaoto Reviewed-by: Alexander Sverdlin Reviewed-by: Yixun Lan --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 38 +++++++++++++++++-------- arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 38 +++++++++++++++++-------- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 22 -------------- arch/riscv/boot/dts/sophgo/sg2002.dtsi | 38 +++++++++++++++++-------- 4 files changed, 78 insertions(+), 58 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi index aa1f5df100f0..fc9e6b56790f 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -15,23 +15,37 @@ memory@80000000 { }; =20 soc { + interrupt-parent =3D <&plic>; + dma-noncoherent; + pinctrl: pinctrl@3001000 { compatible =3D "sophgo,cv1800b-pinctrl"; reg =3D <0x03001000 0x1000>, <0x05027000 0x1000>; reg-names =3D "sys", "rtc"; }; + + clk: clock-controller@3002000 { + compatible =3D "sophgo,cv1800-clk"; + reg =3D <0x03002000 0x1000>; + clocks =3D <&osc>; + #clock-cells =3D <1>; + }; + + plic: interrupt-controller@70000000 { + compatible =3D "sophgo,cv1800b-plic", "thead,c900-plic"; + reg =3D <0x70000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + riscv,ndev =3D <101>; + }; + + clint: timer@74000000 { + compatible =3D "sophgo,cv1800b-clint", "thead,c900-clint"; + reg =3D <0x74000000 0x10000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; + }; }; }; - -&plic { - compatible =3D "sophgo,cv1800b-plic", "thead,c900-plic"; -}; - -&clint { - compatible =3D "sophgo,cv1800b-clint", "thead,c900-clint"; -}; - -&clk { - compatible =3D "sophgo,cv1800-clk"; -}; diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/= sophgo/cv1812h.dtsi index 8a1b95c5116b..fcea4376fb79 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -17,23 +17,37 @@ memory@80000000 { }; =20 soc { + interrupt-parent =3D <&plic>; + dma-noncoherent; + pinctrl: pinctrl@3001000 { compatible =3D "sophgo,cv1812h-pinctrl"; reg =3D <0x03001000 0x1000>, <0x05027000 0x1000>; reg-names =3D "sys", "rtc"; }; + + clk: clock-controller@3002000 { + compatible =3D "sophgo,cv1810-clk"; + reg =3D <0x03002000 0x1000>; + clocks =3D <&osc>; + #clock-cells =3D <1>; + }; + + plic: interrupt-controller@70000000 { + compatible =3D "sophgo,cv1812h-plic", "thead,c900-plic"; + reg =3D <0x70000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + riscv,ndev =3D <101>; + }; + + clint: timer@74000000 { + compatible =3D "sophgo,cv1812h-clint", "thead,c900-clint"; + reg =3D <0x74000000 0x10000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; + }; }; }; - -&plic { - compatible =3D "sophgo,cv1812h-plic", "thead,c900-plic"; -}; - -&clint { - compatible =3D "sophgo,cv1812h-clint", "thead,c900-clint"; -}; - -&clk { - compatible =3D "sophgo,cv1810-clk"; -}; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/s= ophgo/cv18xx.dtsi index c18822ec849f..805b694aa814 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -49,18 +49,10 @@ osc: oscillator { =20 soc { compatible =3D "simple-bus"; - interrupt-parent =3D <&plic>; #address-cells =3D <1>; #size-cells =3D <1>; - dma-noncoherent; ranges; =20 - clk: clock-controller@3002000 { - reg =3D <0x03002000 0x1000>; - clocks =3D <&osc>; - #clock-cells =3D <1>; - }; - gpio0: gpio@3020000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0x3020000 0x1000>; @@ -344,19 +336,5 @@ dmac: dma-controller@4330000 { snps,data-width =3D <4>; status =3D "disabled"; }; - - plic: interrupt-controller@70000000 { - reg =3D <0x70000000 0x4000000>; - interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <2>; - riscv,ndev =3D <101>; - }; - - clint: timer@74000000 { - reg =3D <0x74000000 0x10000>; - interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; - }; }; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2002.dtsi index 7f79de33163c..df133831bd3e 100644 --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -17,27 +17,41 @@ memory@80000000 { }; =20 soc { + interrupt-parent =3D <&plic>; + dma-noncoherent; + pinctrl: pinctrl@3001000 { compatible =3D "sophgo,sg2002-pinctrl"; reg =3D <0x03001000 0x1000>, <0x05027000 0x1000>; reg-names =3D "sys", "rtc"; }; + + clk: clock-controller@3002000 { + compatible =3D "sophgo,sg2000-clk"; + reg =3D <0x03002000 0x1000>; + clocks =3D <&osc>; + #clock-cells =3D <1>; + }; + + plic: interrupt-controller@70000000 { + compatible =3D "sophgo,sg2002-plic", "thead,c900-plic"; + reg =3D <0x70000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + riscv,ndev =3D <101>; + }; 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charset="utf-8" As sg2000 and sg2002 can boot from an arm a53 core, it is not suitable to left the riscv cpu definition in the common peripheral header. Move the riscv related device into a separate header file, so the arm subsystem can reuse the common peripheral header. Signed-off-by: Alexander Sverdlin Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 + arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi | 36 +++++++++++++++++++++ arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 1 + arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 29 ----------------- arch/riscv/boot/dts/sophgo/sg2002.dtsi | 1 + 5 files changed, 39 insertions(+), 29 deletions(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi index fc9e6b56790f..91bf4563e1f9 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include "cv180x-cpus.dtsi" #include "cv18xx.dtsi" =20 / { diff --git a/arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi b/arch/riscv/boot/= dts/sophgo/cv180x-cpus.dtsi new file mode 100644 index 000000000000..93fd9e47a195 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2023 Inochi Amaoto + */ + +/ { + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <25000000>; + + cpu0: cpu@0 { + compatible =3D "thead,c906", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <65536>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/= sophgo/cv1812h.dtsi index fcea4376fb79..cc094b3f585f 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include "cv180x-cpus.dtsi" #include "cv18xx.dtsi" #include "cv181x.dtsi" =20 diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/s= ophgo/cv18xx.dtsi index 805b694aa814..a4f957302094 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -12,35 +12,6 @@ / { #address-cells =3D <1>; #size-cells =3D <1>; =20 - cpus: cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - timebase-frequency =3D <25000000>; - - cpu0: cpu@0 { - compatible =3D "thead,c906", "riscv"; - device_type =3D "cpu"; - reg =3D <0>; - d-cache-block-size =3D <64>; - d-cache-sets =3D <512>; - d-cache-size =3D <65536>; - i-cache-block-size =3D <64>; - i-cache-sets =3D <128>; - i-cache-size =3D <32768>; - mmu-type =3D "riscv,sv39"; - riscv,isa =3D "rv64imafdc"; - riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; - - cpu0_intc: interrupt-controller { - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells =3D <1>; - }; - }; - }; - osc: oscillator { compatible =3D "fixed-clock"; clock-output-names =3D "osc_25m"; diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2002.dtsi index df133831bd3e..6f02de9b0982 100644 --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include "cv180x-cpus.dtsi" #include "cv18xx.dtsi" #include "cv181x.dtsi" =20 --=20 2.49.0 From nobody Sun Feb 8 06:49:56 2026 Received: from mail-qv1-f49.google.com (mail-qv1-f49.google.com [209.85.219.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0751A1442F4; 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charset="utf-8" As the cv18xx.dtsi serves as a common peripheral header for all riscv cv180x/cv181x/sg200x SoCs, it not cover the entire cv18xx series as there is cv182x and cv183x. So rename the header file to make it precise. Signed-off-by: Inochi Amaoto Reviewed-by: Alexander Sverdlin --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +- arch/riscv/boot/dts/sophgo/{cv18xx.dtsi =3D> cv180x.dtsi} | 0 arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 2 +- arch/riscv/boot/dts/sophgo/sg2002.dtsi | 2 +- 4 files changed, 3 insertions(+), 3 deletions(-) rename arch/riscv/boot/dts/sophgo/{cv18xx.dtsi =3D> cv180x.dtsi} (100%) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi index 91bf4563e1f9..d0a627c086fb 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -5,7 +5,7 @@ =20 #include #include "cv180x-cpus.dtsi" -#include "cv18xx.dtsi" +#include "cv180x.dtsi" =20 / { compatible =3D "sophgo,cv1800b"; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/s= ophgo/cv180x.dtsi similarity index 100% rename from arch/riscv/boot/dts/sophgo/cv18xx.dtsi rename to arch/riscv/boot/dts/sophgo/cv180x.dtsi diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/= sophgo/cv1812h.dtsi index cc094b3f585f..d9580a2e1e7f 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -6,7 +6,7 @@ #include #include #include "cv180x-cpus.dtsi" -#include "cv18xx.dtsi" +#include "cv180x.dtsi" #include "cv181x.dtsi" =20 / { diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2002.dtsi index 6f02de9b0982..60709df12a22 100644 --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -6,7 +6,7 @@ #include #include #include "cv180x-cpus.dtsi" -#include "cv18xx.dtsi" +#include "cv180x.dtsi" #include "cv181x.dtsi" =20 / { --=20 2.49.0 From nobody Sun Feb 8 06:49:56 2026 Received: from mail-qt1-f172.google.com (mail-qt1-f172.google.com [209.85.160.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E39E17A2E8; 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Tue, 29 Apr 2025 18:27:25 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with UTF8SMTPSA id d75a77b69052e-47ea16938d9sm86424311cf.55.2025.04.29.18.27.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 18:27:24 -0700 (PDT) From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Chen Wang , Inochi Amaoto , Alexander Sverdlin , Thomas Bonnefille Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH 4/4] riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number Date: Wed, 30 Apr 2025 09:26:53 +0800 Message-ID: <20250430012654.235830-5-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250430012654.235830-1-inochiama@gmail.com> References: <20250430012654.235830-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since riscv and arm architecture use different interrupt definitions, use a macro SOC_PERIPHERAL_IRQ mask this difference. Signed-off-by: Alexander Sverdlin Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 ++ arch/riscv/boot/dts/sophgo/cv180x.dtsi | 44 ++++++++++++------------- arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 2 ++ arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +- arch/riscv/boot/dts/sophgo/sg2002.dtsi | 2 ++ 5 files changed, 29 insertions(+), 23 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi index d0a627c086fb..88707cc13fb4 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2023 Jisheng Zhang */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include "cv180x-cpus.dtsi" #include "cv180x.dtsi" diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/s= ophgo/cv180x.dtsi index a4f957302094..ad5052bf36e5 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -38,7 +38,7 @@ porta: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <60 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -56,7 +56,7 @@ portb: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <61 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -74,7 +74,7 @@ portc: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -92,7 +92,7 @@ portd: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <63 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -100,7 +100,7 @@ saradc: adc@30f0000 { compatible =3D "sophgo,cv1800b-saradc"; reg =3D <0x030f0000 0x1000>; clocks =3D <&clk CLK_SARADC>; - interrupts =3D <100 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -125,7 +125,7 @@ i2c0: i2c@4000000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; clock-names =3D "ref", "pclk"; - interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -136,7 +136,7 @@ i2c1: i2c@4010000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; clock-names =3D "ref", "pclk"; - interrupts =3D <50 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -147,7 +147,7 @@ i2c2: i2c@4020000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; clock-names =3D "ref", "pclk"; - interrupts =3D <51 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -158,7 +158,7 @@ i2c3: i2c@4030000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; clock-names =3D "ref", "pclk"; - interrupts =3D <52 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -169,14 +169,14 @@ i2c4: i2c@4040000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; clock-names =3D "ref", "pclk"; - interrupts =3D <53 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 uart0: serial@4140000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04140000 0x100>; - interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART0>, <&clk CLK_APB_UART0>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -187,7 +187,7 @@ uart0: serial@4140000 { uart1: serial@4150000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04150000 0x100>; - interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART1>, <&clk CLK_APB_UART1>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -198,7 +198,7 @@ uart1: serial@4150000 { uart2: serial@4160000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04160000 0x100>; - interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART2>, <&clk CLK_APB_UART2>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -209,7 +209,7 @@ uart2: serial@4160000 { uart3: serial@4170000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04170000 0x100>; - interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART3>, <&clk CLK_APB_UART3>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -224,7 +224,7 @@ spi0: spi@4180000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <54 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -235,7 +235,7 @@ spi1: spi@4190000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <55 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -246,7 +246,7 @@ spi2: spi@41a0000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <56 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -257,14 +257,14 @@ spi3: spi@41b0000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <57 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 uart4: serial@41c0000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x041c0000 0x100>; - interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART4>, <&clk CLK_APB_UART4>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -275,7 +275,7 @@ uart4: serial@41c0000 { sdhci0: mmc@4310000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4310000 0x1000>; - interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_SD0>, <&clk CLK_SD0>; clock-names =3D "core", "bus"; @@ -285,7 +285,7 @@ sdhci0: mmc@4310000 { sdhci1: mmc@4320000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4320000 0x1000>; - interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_SD1>, <&clk CLK_SD1>; clock-names =3D "core", "bus"; @@ -295,7 +295,7 @@ sdhci1: mmc@4320000 { dmac: dma-controller@4330000 { compatible =3D "snps,axi-dma-1.01a"; reg =3D <0x04330000 0x1000>; - interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; clock-names =3D "core-clk", "cfgr-clk"; #dma-cells =3D <1>; diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/= sophgo/cv1812h.dtsi index d9580a2e1e7f..0974955e4e05 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2023 Inochi Amaoto */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include #include "cv180x-cpus.dtsi" diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/s= ophgo/cv181x.dtsi index 5fd14dd1b14f..bbdb30653e9a 100644 --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi @@ -11,7 +11,7 @@ soc { emmc: mmc@4300000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4300000 0x1000>; - interrupts =3D <34 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_EMMC>, <&clk CLK_EMMC>; clock-names =3D "core", "bus"; diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2002.dtsi index 60709df12a22..6f09c9199102 100644 --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2024 Thomas Bonnefille */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include #include "cv180x-cpus.dtsi" --=20 2.49.0