From nobody Tue Apr 7 01:04:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A4D8370D73; Tue, 17 Mar 2026 09:32:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773739944; cv=none; b=KDamJW5Xq89EeiM/osDW+LhUcjqhwTiX6CpY/GGJ/YCADv2bqa2Lvq8UP1gedB3FhgW7WcjKtYVDc3eSAJNPPS+xY8s9wpAPf9dM5NHZj8BLvAxwGEUU4L+eQj74XOw8sYiRGCj6tZT3B9g6XEdinR1jIwEXfYnybhakhNOY07I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773739944; c=relaxed/simple; bh=vi4e3/G+GT0yYW4Lnppucac1AE/42afeV4FuzhAojdo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EYNSORpKSpawqGX2mL8VqVYKLvYY3jlQfgYXw3CZYPnEMdieOfCO/g2pcyP7S9wE6et+GH7dkW5qE5Ub+9WWjXMQF7tvIqHcVvNkP2zU4bYd36vb3VBzi80lY9wJS1Ikcv64ajSVsNRF2QmKtP3mC/SMfahKbozHdjNSx1VrFpQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nN9Dysq+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nN9Dysq+" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4309DC2BCC4; Tue, 17 Mar 2026 09:32:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773739944; bh=vi4e3/G+GT0yYW4Lnppucac1AE/42afeV4FuzhAojdo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=nN9Dysq+BpJJavWaN+HAaTp5D1t5NGWBV3K1bcmpTiMtvVocGeSQZ3cA+RwH5EqLm qhmOTFeiZC9VNOxC6DjEU7aicDpZMoHkwcU06WpL9t3H4Ze1qidDn6psayfv3MT3+/ VjXXpgMni7RRyoQSBziOthR7ekRH0vyafsJZt//iBD7D9f76SDxB7wipmakVWqwj3c 0QfTpjpEer7lMnzXo1GrQa2542yXWi/+DyewEG6Uxij/pYm5iRo85uSGrLDH766T8f BxL5+S/usXp6Wv317Vezp2bNywl1f93PYnixLbNz4ZuVWr0gSYl3fk2fBtkmGbODzs pw5nHw8bn1uLA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A848F33829; Tue, 17 Mar 2026 09:32:24 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 17 Mar 2026 10:32:24 +0100 Subject: [PATCH v2 6/9] arm64: dts: rockchip: add vicap node to rk3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-rk3588-vicap-v2-6-77de5ee9048e@collabora.com> References: <20250430-rk3588-vicap-v2-0-77de5ee9048e@collabora.com> In-Reply-To: <20250430-rk3588-vicap-v2-0-77de5ee9048e@collabora.com> To: Mehdi Djait , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Jagan Teki , =?utf-8?q?=D0=9A=D1=83=D0=B7=D0=BD=D0=B5=D1=86=D0=BE=D0=B2_=D0=9C=D0=B8=D1=85=D0=B0=D0=B8=D0=BB?= , Sebastian Reichel , Nicolas Dufresne , Collabora Kernel Team , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773739942; l=3247; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=5m1TI1JCn0xwCW+Lu2Bsv0EUfJ/OG5gXux9j14Zr9GY=; b=Jr6sXsKfwnr0bmWI3Yvmdj194JbzH2OSGEd5CZTQy08iQxtnCkpLO4pfJQ5WcGS6oatN9qCbh 8oRfDgSG5L1AnZmZxUKteBXGrPXuUmMArbhP500bubx4cmhP3jz2axb X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add the device tree node for the RK3588 Video Capture (VICAP) unit. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 91 +++++++++++++++++++++++= ++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 6c593b0255c3..9c5b68fd02c7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1430,6 +1430,89 @@ av1d: video-codec@fdc70000 { resets =3D <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, = <&cru SRST_P_AV1_BIU>; }; =20 + vicap: video-capture@fdce0000 { + compatible =3D "rockchip,rk3588-vicap"; + reg =3D <0x0 0xfdce0000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_CSIHOST0>, + <&cru ICLK_CSIHOST1>; + clock-names =3D "aclk", "hclk", "dclk", "iclk0", "iclk1"; + iommus =3D <&vicap_mmu>; + power-domains =3D <&power RK3588_PD_VI>; + resets =3D <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_CSIHOST0_VICAP>, + <&cru SRST_CSIHOST1_VICAP>, + <&cru SRST_CSIHOST2_VICAP>, + <&cru SRST_CSIHOST3_VICAP>, + <&cru SRST_CSIHOST4_VICAP>, + <&cru SRST_CSIHOST5_VICAP>; + reset-names =3D "arst", "hrst", "drst", "irst0", "irst1", + "irst2", "irst3", "irst4", "irst5"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + vicap_dvp: port@0 { + reg =3D <0>; + }; + + vicap_mipi0: port@1 { + reg =3D <1>; + }; + + vicap_mipi1: port@2 { + reg =3D <2>; + }; + + vicap_mipi2: port@3 { + reg =3D <3>; + + vicap_mipi2_input: endpoint { + remote-endpoint =3D <&csi2_output>; + }; + }; + + vicap_mipi3: port@4 { + reg =3D <4>; + }; + + vicap_mipi4: port@5 { + reg =3D <5>; + + vicap_mipi4_input: endpoint { + remote-endpoint =3D <&csi4_output>; + }; + }; + + vicap_mipi5: port@6 { + reg =3D <6>; + }; + + vicap_toisp0: port@10 { + reg =3D <10>; + }; + + vicap_toisp1: port@11 { + reg =3D <11>; + }; + }; + }; + + vicap_mmu: iommu@fdce0800 { + compatible =3D "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdce0800 0x0 0x40>, <0x0 0xfdce0900 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names =3D "aclk", "iface"; + #iommu-cells =3D <0>; + power-domains =3D <&power RK3588_PD_VI>; + rockchip,disable-mmu-reset; + status =3D "disabled"; + }; + csi2: csi@fdd30000 { compatible =3D "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; reg =3D <0x0 0xfdd30000 0x0 0x10000>; @@ -1452,6 +1535,10 @@ csi2_in: port@0 { =20 csi2_out: port@1 { reg =3D <1>; + + csi2_output: endpoint { + remote-endpoint =3D <&vicap_mipi2_input>; + }; }; }; }; @@ -1478,6 +1565,10 @@ csi4_in: port@0 { =20 csi4_out: port@1 { reg =3D <1>; + + csi4_output: endpoint { + remote-endpoint =3D <&vicap_mipi4_input>; + }; }; }; }; --=20 2.39.5