From nobody Tue Apr 7 12:57:29 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA7933AD503; Fri, 13 Mar 2026 15:20:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773415246; cv=none; b=O+iNq6MMcVcA6mVpbgu1q+yLXPlx/fa+W+wv4lW5yiJO7Led1iw/OLjpwNsoradyUOFl88MFK0J/R7gt5JPKs8nqrkJMgFqQkZ3SXb3qfzjt6Hie/PnQu4TUxpEQAofZwlRtF7lTSPatiKPZs4twQgGOSBsWr4nLTzfiFeMgYZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773415246; c=relaxed/simple; bh=FhTQ5SVdxITPm8tDe0bW/0ZG36G8hCk0e58aJbKwRGQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Pm/8TKKKKW86SjIo7ZryJSyAu6Nr9BJW3jJtFrrwQThMtNNnCM+JyxsFyPtPuBMRKBrKp8hhWmN004SxgEOkmV9ngmJ+95F9HdMFlw0KN9CbTxPYp4u6RqPRoQsd3fNFE1dkRrjvusSOct17CoP7a2If5iaKQvT1/CSDOr6MxJk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Usqoq4eu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Usqoq4eu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6F570C2BC87; Fri, 13 Mar 2026 15:20:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773415246; bh=FhTQ5SVdxITPm8tDe0bW/0ZG36G8hCk0e58aJbKwRGQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Usqoq4eujdp/ykdqtdOMtfmZZCceIAhKYKuh7KzHk5jzBRbVLuQiF0uGRszoT1z7/ VMipIWN3SPKq/rcXOTBcVzRDa1l5ULLW/HHjS0x/j7H5l6UFYJZfyZKsjHuPNfb66i VV8SXyZ/L0Qfs+KZCVovydewPhYnA1R6RCBcqgLILMOLa2/Hj21oaPXRSkvwE0nKNE 1hbt41eGXS4vPpCn2CPm+nxzRodSg4ou5VzT7t+2M7/8PVLP+jZU/8FMHbB1T7o0sb wYKNE6gjTAQktjc5rJDBBuooKjipTBFTwEuBITzNe9CsnoJYYY9Z8XizFnfoFV2XwX 633Eg1KIKZ7yQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65ADE105F7BC; Fri, 13 Mar 2026 15:20:46 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Fri, 13 Mar 2026 16:20:47 +0100 Subject: [PATCH DONOTMERGE 5/9] arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-rk3588-vicap-v1-5-b3bddf749914@collabora.com> References: <20250430-rk3588-vicap-v1-0-b3bddf749914@collabora.com> In-Reply-To: <20250430-rk3588-vicap-v1-0-b3bddf749914@collabora.com> To: Mehdi Djait , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Jagan Teki , =?utf-8?q?=D0=9A=D1=83=D0=B7=D0=BD=D0=B5=D1=86=D0=BE=D0=B2_=D0=9C=D0=B8=D1=85=D0=B0=D0=B8=D0=BB?= , Sebastian Reichel , Nicolas Dufresne , Collabora Kernel Team , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773415244; l=2664; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=5oU0klzEB2FubzgZ+1XdUaBRRnzqz5jTIQAtdWBAHeM=; b=9XFhFOGOTKJeatU9czWomdBIwqBazjGoUPrY+Ii0pHpmta8bfcJzBj1veZEg0TtAR6BAet7Jz J5dzoQVl+6TAGzP/TYqPNvw1PWuktisY7B8caLtSFBLTUez+q0Q4les X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch This patch is discussed over at https://lore.kernel.org/all/20260305-rk3588-csi2rx-v2-0-79d01b615486@collab= ora.com included here for testing purposes only. The Rockchip RK3588 features six MIPI CSI-2 receiver units: - MIPI0: connected to MIPI DCPHY0 (not supported) - MIPI1: connected to MIPI DCPHY1 (not supported) - MIPI2: connected to MIPI DPHY0 - MIPI3: connected to MIPI DPHY0-1 (not supported) - MIPI4: connected to MIPI DPHY1 - MIPI5: connected to MIPI DPHY1-1 (not supported) As the MIPI DCPHYs as well as the split DPHY mode of the DPHYs are not yet supported, add only the device tree nodes for the MIPI2 and MIPI4 units. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 52 +++++++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 7fe9593d8c19..6c593b0255c3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1430,6 +1430,58 @@ av1d: video-codec@fdc70000 { resets =3D <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, = <&cru SRST_P_AV1_BIU>; }; =20 + csi2: csi@fdd30000 { + compatible =3D "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg =3D <0x0 0xfdd30000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "err1", "err2"; + clocks =3D <&cru PCLK_CSI_HOST_2>; + phys =3D <&csi_dphy0>; + power-domains =3D <&power RK3588_PD_VI>; + resets =3D <&cru SRST_P_CSI_HOST_2>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_in: port@0 { + reg =3D <0>; + }; + + csi2_out: port@1 { + reg =3D <1>; + }; + }; + }; + + csi4: csi@fdd50000 { + compatible =3D "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg =3D <0x0 0xfdd50000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "err1", "err2"; + clocks =3D <&cru PCLK_CSI_HOST_4>; + phys =3D <&csi_dphy1>; + power-domains =3D <&power RK3588_PD_VI>; + resets =3D <&cru SRST_P_CSI_HOST_4>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi4_in: port@0 { + reg =3D <0>; + }; + + csi4_out: port@1 { + reg =3D <1>; + }; + }; + }; + vop: vop@fdd90000 { compatible =3D "rockchip,rk3588-vop"; reg =3D <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; --=20 2.39.5