From nobody Tue Feb 10 00:44:18 2026 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CB4D1E4110 for ; Wed, 30 Apr 2025 09:03:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003797; cv=none; b=eZiOZtkAqv49GlIF85l+exzkWIMu0iqDKZY2iQwR00I6UQ4rkKLHTmGh+Libq4TCYBTvMQuKfqUkfV18RImmlm3UTnAcXTjUJyXMHia9uMdAT6r/4G7CD7Aj8KQqPLzDslJqGCg0D020AGJ+YQoGQajeT/4VbqDBZuQf7ikeD8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003797; c=relaxed/simple; bh=4SBDb8RMix1AfTeAapS22vbsprNHW5kDlKivkfzgJb4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LR3jle9mTixzfUyNi2crIC4ssxoxUnAXo/gaFjcqqe7J7IKMkf5nbk3utRwtTNWx+nkNXysWBGZP+zrB/6fpu4XMI5cxyEuZh0FTOTYVpKIMEBulZQIC7i7qJuT+V/7o/i+HQ8NU9Xgjjon4FXi00EVkt0puSuH9fGS9yObwz1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=SCR2iUJo; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SCR2iUJo" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-5f6214f189bso13644857a12.2 for ; Wed, 30 Apr 2025 02:03:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746003793; x=1746608593; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=UsPhnEzsIjMyr2jWNVlW883QIlYElONTjUn31M/bDFU=; b=SCR2iUJouxyuhKI6WT29nyLHmzdiyJvYz0wS2PbWU3IhUKJXILJm7DFm1JvPbEPUbN +YZhPJgw/cKXms9tA/5A4Vce8D6AtQVLpZMpt+a5eMmj9T9JMQ900kqNN21C9PUSKgl6 XweOc73qhilqfh11BHe2WICOT29sjPVcSvaC95w2Eeq2nRice1RA6s9pv5s5NBoJ80qP 9iSoDsiDiJVFm9VYClO/oAgAhoBdSEQpMjfw11/7bVs5tOWx//l0cEWN2783ffpGZKor MRKEO7XQBs6GzKwjO6oVzv+MBmS+l75eFnG0BIUFKUP7/QA8JET+RL1PmvGVQc/ebUTy ilJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746003793; x=1746608593; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UsPhnEzsIjMyr2jWNVlW883QIlYElONTjUn31M/bDFU=; b=O3Fxq8QlQKp+H9RVhCWk1gAM7VZ6ppFjokRfTbErg0tptU7ehl5HWa34FYp1fcFUO/ Hr/9AOcHzVTm5fwgjipiJB1kyt/fGxgNOfWm1QzVtVDIlGSHOZsnOmvc2fXC6Y6Phzln AJb4EekZ7R+lKMH8IlP44vRw9M8kVMJns5tLB5cDBOVfxccaJ59wtdiPuI8C6mTjzA7r B0NobH6uBparWLsv50yn2GWGEEOUN1LDF5UZucrAHW/q9t9flkkrV71BY6rqDdE1SNsx j5O1a91+cSQFK4ZP3a+I+iHYrx8erqc1HdbaMVpLO9apDAbzfiwH+YzH3t/ov2xEq1yJ JV/g== X-Forwarded-Encrypted: i=1; AJvYcCWGlJIYa8tbm5di7zqX2FlwVsTOhw8X7Nv/aIdajSfN3WYgVG/5GjU/kNFH/SaX7pDJHAE8aWLNfSMU4oA=@vger.kernel.org X-Gm-Message-State: AOJu0YyQ0O88Mc3OEgzmyQOe9Dq2PzF4SYomVT4kZ+SQkD+4cpdl3M46 kbxOELYLUH/KbDeJ8T068f9tW1l9tU5ApXZ2p9qZkPBlB8Ii3Hilxd7ocuU2ELA= X-Gm-Gg: ASbGncvnLT4C+4OViNIUYE3hIALe7XiflOaoB71JPEAGBZxunyGIHPDOXo6UkE9R0e4 Dy4e06msgwaelALwLMOUnMrkA4KhB1hC0Trc8r1Rdf2CKqR5c40GI4H8DI/i2bW5Mi5n02Ff1Md i6GHzjLaPw0ArigRfkmotHljVXuiW+6i5nKwHeAJljevMtyg7Lt0AAwPVuekgbTZTU9TnOVfenB ApHXko1xLw0rxbvkGNCzpzc+jRwe9CgpZuRFjs1BZVp1dd4zHgvfyUQViy7pMIUj3+mMqC2OPFp G3NyXAKvqPnczENF0CiEpdb+/mSVJ1CAbMA48jjpsOA5xO99z4TscL3/6TClpcPAdITNI6KHsqy n8f/aI4/uPcJmqtFotkmkWD4E X-Google-Smtp-Source: AGHT+IHVsZ8xYEbEizsgZIRrUswi5I9gaZlF8LH7SsKiLHMHKzkdmybyODeG5bKN3kGAyjZ7wypovA== X-Received: by 2002:a17:907:970d:b0:acb:66ea:5786 with SMTP id a640c23a62f3a-acedc6342a5mr263771366b.31.1746003792448; Wed, 30 Apr 2025 02:03:12 -0700 (PDT) Received: from puffmais.c.googlers.com (8.239.204.35.bc.googleusercontent.com. [35.204.239.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6e41bbb6sm889676766b.28.2025.04.30.02.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 02:03:12 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 30 Apr 2025 10:03:08 +0100 Subject: [PATCH v9 1/6] dt-bindings: gpio: add max77759 binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-max77759-mfd-v9-1-639763e23598@linaro.org> References: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> In-Reply-To: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Srinivas Kandagatla , Kees Cook , "Gustavo A. R. Silva" Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-hardening@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Bartosz Golaszewski X-Mailer: b4 0.14.2 The Maxim MAX77759 is a companion PMIC for USB Type-C applications and includes Battery Charger, Fuel Gauge, temperature sensors, USB Type-C Port Controller (TCPC), NVMEM, and a GPIO expander. This describes its GPIO module. Reviewed-by: Rob Herring (Arm) Acked-by: Bartosz Golaszewski Signed-off-by: Andr=C3=A9 Draszik --- v2: * drop 'interrupts' property and sort properties alphabetically --- .../bindings/gpio/maxim,max77759-gpio.yaml | 44 ++++++++++++++++++= ++++ MAINTAINERS | 6 +++ 2 files changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/maxim,max77759-gpio.yam= l b/Documentation/devicetree/bindings/gpio/maxim,max77759-gpio.yaml new file mode 100644 index 0000000000000000000000000000000000000000..55734190d5ebdbc351e1f91675d= ddd8a9db80cd7 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/maxim,max77759-gpio.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/maxim,max77759-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77759 GPIO + +maintainers: + - Andr=C3=A9 Draszik + +description: | + This module is part of the MAX77759 PMIC. For additional information, see + Documentation/devicetree/bindings/mfd/maxim,max77759.yaml. + + The MAX77759 is a PMIC integrating, amongst others, a GPIO controller + including interrupt support for 2 GPIO lines. + +properties: + compatible: + const: maxim,max77759-gpio + + "#gpio-cells": + const: 2 + + gpio-controller: true + + gpio-line-names: + minItems: 1 + maxItems: 2 + + "#interrupt-cells": + const: 2 + + interrupt-controller: true + +required: + - compatible + - "#gpio-cells" + - gpio-controller + - "#interrupt-cells" + - interrupt-controller + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index 906881b6c5cb6ff743e13b251873b89138c69a1c..0c7bf694468e9798946baecdfd0= 3d6eacdba2ce3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14663,6 +14663,12 @@ F: Documentation/devicetree/bindings/mfd/maxim,max= 77714.yaml F: drivers/mfd/max77714.c F: include/linux/mfd/max77714.h =20 +MAXIM MAX77759 PMIC MFD DRIVER +M: Andr=C3=A9 Draszik +L: linux-kernel@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/*/maxim,max77759*.yaml + MAXIM MAX77802 PMIC REGULATOR DEVICE DRIVER M: Javier Martinez Canillas L: linux-kernel@vger.kernel.org --=20 2.49.0.901.g37484f566f-goog From nobody Tue Feb 10 00:44:18 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B716621B9E0 for ; Wed, 30 Apr 2025 09:03:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003797; cv=none; b=nNdmx+43NRiRAbdW/zF4szS0fHU9CxFabHhg7jzGR1RzXYVt2CrSVYfWCyapvPQTYqh9uypyRgTRSPb4DxXxQ51t7KmTsX25bm0XPSwmF0cmY4ut73sjo1JRRhYSzhERvTCNrz/DlfW8mQv/GCFMvOc/EtNunsEQBFSY3WaQR/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003797; c=relaxed/simple; bh=Cc1Ucs7d+DoVlcf66E1KPy7NQ5fP8mutIpm2TD0VDuE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Wj8dIPmDJPPtuv10cCOXq/BqIYSxX4vV07ub7JRTmHileO4agqkIUWssxEmGsVmUDlE/VBLbqZ1UmUJpWT3x78DbDvP8eMnYLObKTL2zKzu6sBlPY3bjBRIcMVS4UgpbxQiJSo0zk74T9S3KwRb+JHdvvrtjXF2vYLFNP6x7aPI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=wdu5M2BO; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="wdu5M2BO" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-ace3b03c043so1110465066b.2 for ; Wed, 30 Apr 2025 02:03:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746003793; x=1746608593; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Rgc6ivQ4v0OBxVxiMV//REmkxOVzSIsF9RwMWgdL0S4=; b=wdu5M2BOvCYtLP31c+R4majTHgHEizvwMZ8fa7CnScROmmjq83XOx0ockoKXnhsj9M MifYakA9gftOFQo8n+lsZC9WLc2qBMSdRaVZdS7xXNMKD6YJhW4KLutHkOGCj61X1u6U IPercFCxtknFeXqvVnoJmzPmVhTgU2IGhYkjedetnAv+S103MpSLCsJL4LE+HqVbWj02 bps+A8OHH6CiabIehAsMP0IVupMTGwzx+DRcLZF1IG4oVsRYbqnUfjcx8JigRxCfdMtO v3+gnDNgZzfHtmFg99pdDT1vsxRy0YeJpxntlJ85SEERSeyqz2aZ37NPnA8ICot0PUXE sa3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746003793; x=1746608593; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rgc6ivQ4v0OBxVxiMV//REmkxOVzSIsF9RwMWgdL0S4=; b=pgWphwr/ooFYWB8j1SLD1sHOikj0IPycmjC6TJN3RgZzVVRiB+sLX6TVtJgVH1Ghf2 LqhKFaUzSdUGuQ9u597pyXtUlyWGbJE7qBgpbyZKt389EwDEHdxKwZpAIIXLFHddlOHM u7bODIvtMgiYez2tnuVa9me9OKrX/9rtdacKxEKYuzIj5z0AMAYeLzpGHVgWzFtkVd/K WoTUcw7VFc/t/8wnb6h6eW+HtqOR0AQmpz+Q11uoZzQjFkYRns8dIowWgg4l8avbPEYY hksBkq1dE1J+2jGMJf40k/7fLzzYNPg+OcvyE8SQ4rcvpdD+TkbIRcjhoR1xrT2Ptxbc P7Fg== X-Forwarded-Encrypted: i=1; AJvYcCW4hwBOXrCuxy6WTrpu9hPbYVPlomYALSm6rSIUCXqEdGGxX38iaVajJocxzNJo/oaoVNe7qJTR7uhVcog=@vger.kernel.org X-Gm-Message-State: AOJu0Yx1t03NYrbEaGp781n5mVtZg2YHqJHn8rDvtaou9VWW+bP6oEBO CRsy/l3QHjy3gxW1ZI+5KRq/QPxpWGpDuH2rZFMX1Ar7uPyLik9LeZ8wY/SQLh0= X-Gm-Gg: ASbGnct8CvDGH/wzEp9o6tp5Z8JVxfubGPDG5YPibg6E9vT+1Yq4QuZE6OoPO3Ya+b0 iBNDUZUTD976udnQPXPDzW2cRyn1nwyP6mrqX6UMl2pAk0yLOXavlk9CGhlygR+77qX3jO+uCxG N7aBIQJIVBRY+QjC8Dgscwa+Wwy6fkmTBMk0+Vx8SdxVh2eGvWMzikxwgvq+pBjSFty2B0BoibT 8TFJCqgnzeiuAgI/mcnDyUaM7plk1g5iDh8bzpAxylko93Rbjq8u5okqudOPE4re8ulRUB/e7bF f3hieo12O4SPIBULNCRRm/jzKiQu7035bJdPchcyg9CT2kjFfZbwjFnZLkFCSVDaBCVBrKt+eR8 T1xkjYpUbM65zwk89EMXq9NEW X-Google-Smtp-Source: AGHT+IHh/frVfvYlJV1tmXFwo00h3A1apTHUNVvYyWOBXRDPAdhfFrheDXV2GwC9doZTSaZcj+ITqw== X-Received: by 2002:a17:907:2d8a:b0:ab7:cfe7:116f with SMTP id a640c23a62f3a-acedc709fe8mr247900966b.46.1746003793118; Wed, 30 Apr 2025 02:03:13 -0700 (PDT) Received: from puffmais.c.googlers.com (8.239.204.35.bc.googleusercontent.com. [35.204.239.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6e41bbb6sm889676766b.28.2025.04.30.02.03.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 02:03:12 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 30 Apr 2025 10:03:09 +0100 Subject: [PATCH v9 2/6] dt-bindings: nvmem: add max77759 binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-max77759-mfd-v9-2-639763e23598@linaro.org> References: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> In-Reply-To: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Srinivas Kandagatla , Kees Cook , "Gustavo A. R. Silva" Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-hardening@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The Maxim MAX77759 is a companion PMIC for USB Type-C applications and includes Battery Charger, Fuel Gauge, temperature sensors, USB Type-C Port Controller (TCPC), NVMEM, and a GPIO expander. This describes its storage module (NVMEM). Reviewed-by: Rob Herring (Arm) Signed-off-by: Andr=C3=A9 Draszik --- v2: * drop example as the MFD binding has a complete one (Rob) Note: MAINTAINERS doesn't need updating, the binding update for the first leaf device (gpio) adds a wildcard matching all max77759 bindings --- .../bindings/nvmem/maxim,max77759-nvmem.yaml | 32 ++++++++++++++++++= ++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/maxim,max77759-nvmem.y= aml b/Documentation/devicetree/bindings/nvmem/maxim,max77759-nvmem.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1e3bd4433007341a11040f513bf= 444866b9e38a8 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/maxim,max77759-nvmem.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/maxim,max77759-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77759 Non Volatile Memory + +maintainers: + - Andr=C3=A9 Draszik + +description: | + This module is part of the MAX77759 PMIC. For additional information, see + Documentation/devicetree/bindings/mfd/maxim,max77759.yaml. + + The MAX77759 is a PMIC integrating, amongst others, Non Volatile Memory + (NVMEM) with 30 bytes of storage which can be used by software to store + information or communicate with a boot loader. + +properties: + compatible: + const: maxim,max77759-nvmem + + wp-gpios: false + +required: + - compatible + +allOf: + - $ref: nvmem.yaml# + +unevaluatedProperties: false --=20 2.49.0.901.g37484f566f-goog From nobody Tue Feb 10 00:44:18 2026 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A09F021B9FD for ; Wed, 30 Apr 2025 09:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003798; cv=none; b=oyzBjkWC0lAmAZmI3bRKsyqbFTFpeLFmRz5ZoKlqat8qgje2hJoJhr3SYaAOau8Iv+vwOjSznBZ5U/6JVVHbyhhFtRwT+4M2Ei3aLLGevrusvehLpPRSlIUosCiqu5GIJgFKBghWtkl3tdhZiAv0Ikapw/FRoJ9Lw7cbp4tA8Hk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003798; c=relaxed/simple; bh=bFksOeknh8d+JfpwdhA3LClj8Y8cCin0vyzLAmX/vl4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BFbvjn/oTuofUFOqOQq9X9SGgXbOUoNZ5iNkrf23cFunVL5hsR0xYkTOiNpeTALmhB4LTFaUJxLQH5N5OpsFUcyG2ZhSjaS3t5ETKMqYpNw95Zph3Mw5D+n09yQFJPfpgCgNKvjOiqKogOPYYTm1r2AOo2+jKlyxamyOa8O0ysU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=SpnR9hNl; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SpnR9hNl" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-ac2aeada833so148133566b.0 for ; Wed, 30 Apr 2025 02:03:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746003794; x=1746608594; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kyiytjDRdFd6s+6c7xd37xzCdnxjjI1OzqbZfUcJ7Kk=; b=SpnR9hNl9mWf+MlzGEOO3WnMpHiOBSGnU437elz744n2CDKB5ZyIS62qos4elyYpZO m2aQxpVcXAxbhg0eUcNDuYhjJ0yPxl5Km1SA47YQ6EG3fURKHyWChpBw+jpSTzstIsE1 KhL4KRQdgnc5bkNkubk3ixyYV/NVJcXwKG1dwNbvlu85t+ZXqsSSyzCe4XL73ccrA54l aOwRG8ByaUMAFGl3eVSKFgkLsWLBBeTaboTQcSM4seJiPhrjNnSv5ldBEx5+jaEc8a5B vVFkDvyHRUw5WXoL4blNNoZroeU3ZBVc8osHJs8gbIToUFuJoWwVM3FUZPqwXPI1Il/x WfVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746003794; x=1746608594; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kyiytjDRdFd6s+6c7xd37xzCdnxjjI1OzqbZfUcJ7Kk=; b=MdkitgGptoLedtfcOH58//mhpGNt2LyD6SpQm+nog2hNjPS+9/1Z9fCUlu8MddX0jz IngL3tvNd64u2LDCpBSM3RhomC2UMr2ThIRTPTzwVAnx50EukzBhH4Cyp+DA0YQuNjg7 gR/nPrsTWJVtPR9I4lggcBQM4sKkhh+d07pAQfn1uf7ag3trDbP+vXHNw3yrLqGeyPz8 AiO64H7+0p6reRSbRoszZcSSmFqwv0tEm3iqiKoC10PZKWBmJyHpp6ZSrYr3Z3YJsJGo wBDbSNWQreHPN3ZOffvlYpTLRktcDf57tszlbxQiaNbUe2WrAVI8hXA1+rjx/xRReirV C4kQ== X-Forwarded-Encrypted: i=1; AJvYcCWNEzorkmmjx273KV4VjBeOg+lucyDXoM4nX6UYes9AAn3IpU5zaNGNkgLFBFLh56GLrBwBSdymCtg5ijE=@vger.kernel.org X-Gm-Message-State: AOJu0Yy0i9dqW2NE6RwbCWqgfKRGcfYJDSZCJQ0s/Gp4CYoizwTVrRoS WvuK9xfXbHuVtj4FK/CXBBrqe/qpNzc5mBGFA04LlfvMYR/pl6TXf8GQN/6NFbo= X-Gm-Gg: ASbGncvKdJY8y2ATDnS0zsjBlK0t+GzNhvndVFB+Qm4v7/Lipex6WoDYSqitCwQi+z4 QpC5mT7O8nrkzNR2dn3digILyZ8dGcbjQzKgah8XvG4q3lMG+lFJT3H4A8HCB6fqsR/8xLe9eNI jYOxYrD0/9TtNY4+vPfy8Y7IMlFV7irkd/TCiY/JdNFxur5fIeAnpkfmNKa4ReyEGqWQEiWCmuT TY9n1NlC8i6Gbngm1ypXmCj7ZC9W2rbN679C/NeaVUCPtgA4BVI9I6NGV5uFP8Q+Y7qUe6729KF E94fK1k+EzNNY3Orn4nLHfNLTneEa34V1X9eoNBoHBHlxIoW8p00LT7uws0NoZrLIGfKvyNyM+I riYcVOwTOjreb0T9xgL3GfIlD X-Google-Smtp-Source: AGHT+IGcixekqMbiCwTt0euFgr8qyktPoka758m284mP8XwKbyfXBT71rs+QPFdZrVWILYzT2lipaw== X-Received: by 2002:a17:907:72ca:b0:acb:37ae:619c with SMTP id a640c23a62f3a-acedf6be04dmr180503466b.15.1746003793663; Wed, 30 Apr 2025 02:03:13 -0700 (PDT) Received: from puffmais.c.googlers.com (8.239.204.35.bc.googleusercontent.com. [35.204.239.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6e41bbb6sm889676766b.28.2025.04.30.02.03.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 02:03:13 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 30 Apr 2025 10:03:10 +0100 Subject: [PATCH v9 3/6] dt-bindings: mfd: add max77759 binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-max77759-mfd-v9-3-639763e23598@linaro.org> References: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> In-Reply-To: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Srinivas Kandagatla , Kees Cook , "Gustavo A. R. Silva" Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-hardening@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The Maxim MAX77759 is a companion PMIC for USB Type-C applications and includes Battery Charger, Fuel Gauge, temperature sensors, USB Type-C Port Controller (TCPC), NVMEM, and a GPIO expander. This describes the top-level device. Reviewed-by: Rob Herring (Arm) Signed-off-by: Andr=C3=A9 Draszik --- v3: * drop gpio-controller and gpio-cells, GPIO is provided by the child (Rob) v2: * rename expected nvmem subdev nodename to 'nvmem-0' I'd have preferred just 'nvmem', but that matches nvmem-consumer.yaml and fails validation. Note: MAINTAINERS doesn't need updating, the binding update for the first leaf device (gpio) adds a wildcard matching all max77759 bindings --- .../devicetree/bindings/mfd/maxim,max77759.yaml | 99 ++++++++++++++++++= ++++ 1 file changed, 99 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/maxim,max77759.yaml b/Do= cumentation/devicetree/bindings/mfd/maxim,max77759.yaml new file mode 100644 index 0000000000000000000000000000000000000000..525de9ab3c2b7b431e484973306= 40857540625b1 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/maxim,max77759.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/maxim,max77759.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77759 PMIC for USB Type-C applications + +maintainers: + - Andr=C3=A9 Draszik + +description: | + This is a part of device tree bindings for the MAX77759 companion Power + Management IC for USB Type-C applications. + + The MAX77759 includes Battery Charger, Fuel Gauge, temperature sensors, = USB + Type-C Port Controller (TCPC), NVMEM, and a GPIO expander. + +properties: + compatible: + const: maxim,max77759 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + reg: + maxItems: 1 + + gpio: + $ref: /schemas/gpio/maxim,max77759-gpio.yaml + + nvmem-0: + $ref: /schemas/nvmem/maxim,max77759-nvmem.yaml + +required: + - compatible + - interrupts + - reg + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmic@66 { + compatible =3D "maxim,max77759"; + reg =3D <0x66>; + interrupts-extended =3D <&gpa8 3 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio { + compatible =3D "maxim,max77759-gpio"; + + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + nvmem-0 { + compatible =3D "maxim,max77759-nvmem"; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reboot-mode@0 { + reg =3D <0x0 0x4>; + }; + + boot-reason@4 { + reg =3D <0x4 0x4>; + }; + + shutdown-user-flag@8 { + reg =3D <0x8 0x1>; + }; + + rsoc@10 { + reg =3D <0xa 0x2>; + }; + }; + }; + }; + }; --=20 2.49.0.901.g37484f566f-goog From nobody Tue Feb 10 00:44:18 2026 Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A9EE214232 for ; Wed, 30 Apr 2025 09:03:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003800; cv=none; b=rN/njKt5px73t1IkzXXiKkLk+ZVxHYd8yTpyJo7nJR4TAQkDv5+Ct1e3kMVE3nl1ag0wqz+n0TS0LritwFe6NBjsNY6VH7Un6ZyyYuWqW0PvW3WCXrfVGSURIaocqFcWdRUPqCFqkpnNDs0nhfnFGZFruvFVrF1vyrWU+v/xtzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003800; c=relaxed/simple; bh=ETC0/fQ2J0eodVufxbigax62gsNYjoMjRIRivyab6iI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YkcDqBfc8BztVZPbQxD82LDHPtHQbZCdEy1CTLxgGR9trAMGqRAvs6ZQm/B2HVdIVeBadLww3kuWmLs6lrfDWDWUea+ltoDvEb6N3qNE4TYabTovT0bLLDAD81ED9QfSr05Sis4LNx+g0RIbyIstiq182gWPA/7w0OEA55P009Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=zTECtDep; arc=none smtp.client-ip=209.85.208.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zTECtDep" Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-5e677f59438so10995668a12.2 for ; Wed, 30 Apr 2025 02:03:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746003795; x=1746608595; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RNMGX8xTAJV03xiy4EuyoYxFrFzL7vnGQ/tRNVy0Y60=; b=zTECtDep04c5sooiW8nCEHz4zinKPA5FymKF+D82eXd7CiWiXIgJ9s7qz0uN+p1qNS ULMIka4q4MK8VUp81oDaFXkbmZxb8wIzxTqZ/NZmdrxBC57LhuYIiUt3NbA4w65YPYYQ aLGp0S9t/Lz8ex/qdp1tbGg491jkQGgInJlMN/6uM3IUF9UIIteasA7yEg+0lS5nCOqF t6FXVchOHLEpqUYVvuX/v4UZSgZes5QJGowSRKp2et9Y+R5JnWjs65YypfMkea0w158G nVAnPjP0Bhhoj8QAa6DWO9KCSFq7i4mfpvMxfnXnlioVDZkMi2f1FchopZCK06NIhTAM OF8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746003795; x=1746608595; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RNMGX8xTAJV03xiy4EuyoYxFrFzL7vnGQ/tRNVy0Y60=; b=cqMiPpM9xsM3g+yiwXbj0imldHadAa4UusWQhr7JGzrSZAyfYfxQiUjnhWSvP8XGpW /8nWkOah1NY7nTmMIt/baK5bZ5NfMtumVAT0Uuc6IlK5PidNKvoDllYwzy+/VgGYS4yQ O55lztjd578HjCDZJiw/ClN7Vw3qzfbrEMxjKtnhiAiq7opgg0ogw+kARLX/1XgMRCih ymGWyFDN4kKkbEjeThSuikr+ZDRdCfd6QiGvHGEqhaXjnkgbe4pZObgfmY0B909K1jUx 2vfQqoCwpemADdkON76se8l7QxpSD2bkD8zN8kpwD4SeXNIcP5GuUkeurEAB7CRQyVwD jS6g== X-Forwarded-Encrypted: i=1; AJvYcCUVifNMqU0wMpxf4miOOq1NTeSiZv0Q7I6Swm4KHM0gLFjx24uwviUt9PcqoV5Eb2r8WQQLnfWcjnmMH7M=@vger.kernel.org X-Gm-Message-State: AOJu0YyfltvmRzkS/ePt2VCVzX373fqvHzdx4vP+jFyrjOOfA3aDYl2G VwG4/+1BFFc4HAp5iY1PIZ6OhAzqmVJiqDa1EzglLdd5O2rvUFlt65CXzWC7nkE= X-Gm-Gg: ASbGncs708OdIsYrCNfEqQu3uabUijfHhAefA6uHwybDHwQxg5UAPbcy+Vjf2oMcPLo zcqr8Rz2kZDABNpXudWWh5IzGYXxF9df00F8vqdAZDGlsdrTMDJctMW2X+uGBljbvKTfG5dsy3a 7lT0CQBMv6xQ6mZLWBtg4tsrlH78jQr/W6ZHCamOTpO7ROKiQWkkdG/JDuKSqsGNIiCVoqJ+xDZ aVj07xW1P2JVxvXYtIsLeuOTx7k7vcBGcCMV8AxjoNbacHa4jISW1Hz0kX/wyrmbYP6PBu1d9sn rL2+065SA62ldzvSlwvpEnwYuIFqehj+lpijVmDznHgDCps2x4WfojdG3rnHlsEitiw/HVsDuad 9T8y+6bvyt7PgUERdgYjQV1pD X-Google-Smtp-Source: AGHT+IFAKZJgrGytc8p4FJx6aqGbMB48BeNTMcYuI/vUNSt+ICPVaY4i5o4gaGYHt1kjsryp7gGWDQ== X-Received: by 2002:a17:907:728f:b0:aca:b45a:7c86 with SMTP id a640c23a62f3a-acedc579956mr228442066b.1.1746003794311; Wed, 30 Apr 2025 02:03:14 -0700 (PDT) Received: from puffmais.c.googlers.com (8.239.204.35.bc.googleusercontent.com. [35.204.239.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6e41bbb6sm889676766b.28.2025.04.30.02.03.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 02:03:13 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 30 Apr 2025 10:03:11 +0100 Subject: [PATCH v9 4/6] mfd: max77759: add Maxim MAX77759 core mfd driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-max77759-mfd-v9-4-639763e23598@linaro.org> References: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> In-Reply-To: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Srinivas Kandagatla , Kees Cook , "Gustavo A. R. Silva" Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-hardening@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The Maxim MAX77759 is a companion PMIC for USB Type-C applications and includes Battery Charger, Fuel Gauge, temperature sensors, USB Type-C Port Controller (TCPC), NVMEM, and a GPIO expander. Fuel Gauge and TCPC have separate and independent I2C addresses, register maps, and interrupt lines and are therefore excluded from the MFD core device driver here. The GPIO and NVMEM interfaces are accessed via specific commands to the built-in microprocessor. This driver implements an API that client drivers can use for accessing those. Signed-off-by: Andr=C3=A9 Draszik --- v6: really use postinc v5: * update all (I hope) of Lee's comments: * file header C comment (not C++) * drop references to 'MFD' * extra indent register bit definitions * make 'struct max77759' public * drop comments that were used for visual separation only * drop MAX77759_*_REG_LAST_REGISTER defines * add comments to regmap ranges * use longer lines * sort local variable in reverse christmas tree order * update comments in max77759_maxq_command() * drop BUILD_BUG_ON() * use dev_err() in max77759_maxq_command() * reflow max77759_create_i2c_subdev() slightly and update error messages * drop useless comment in max77759_add_chained_maxq() * reflow max77759_probe() * consistent upper-/lower-case in messages v4: * add missing build_bug.h include * update an irq chip comment * fix a whitespace in register definitions v2: * add kernel doc for max77759_maxq_command() and related structs * fix an msec / usec typo * add missing error handling of devm_mutex_init() (Christophe) * align sentinel in max77759_of_id[] with max77759_i2c_id[] (Christophe) * some tidy-ups in max77759_maxq_command() (Christophe) max77759 Lee's updates --- MAINTAINERS | 2 + drivers/mfd/Kconfig | 20 ++ drivers/mfd/Makefile | 1 + drivers/mfd/max77759.c | 690 +++++++++++++++++++++++++++++++++++++++= ++++ include/linux/mfd/max77759.h | 165 +++++++++++ 5 files changed, 878 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0c7bf694468e9798946baecdfd03d6eacdba2ce3..1259d09e700a21215e8ae2facef= 858df5304346e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14668,6 +14668,8 @@ M: Andr=C3=A9 Draszik L: linux-kernel@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/*/maxim,max77759*.yaml +F: drivers/mfd/max77759.c +F: include/linux/mfd/max77759.h =20 MAXIM MAX77802 PMIC REGULATOR DEVICE DRIVER M: Javier Martinez Canillas diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 22b93631003943c393d9fe704748bc23f1905397..96992af22565205716d72db0494= c7bf2567b045e 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -943,6 +943,26 @@ config MFD_MAX77714 drivers must be enabled in order to use each functionality of the device. =20 +config MFD_MAX77759 + tristate "Maxim Integrated MAX77759 PMIC" + depends on I2C + depends on OF + select IRQ_DOMAIN + select MFD_CORE + select REGMAP_I2C + select REGMAP_IRQ + help + Say yes here to add support for Maxim Integrated MAX77759. + This is a companion Power Management IC for USB Type-C applications + with Battery Charger, Fuel Gauge, temperature sensors, USB Type-C + Port Controller (TCPC), NVMEM, and additional GPIO interfaces. + This driver provides common support for accessing the device; + additional drivers must be enabled in order to use the functionality + of the device. + + To compile this driver as a module, choose M here: the module will be + called max77759. + config MFD_MAX77843 bool "Maxim Semiconductor MAX77843 PMIC Support" depends on I2C=3Dy diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 948cbdf42a18b22a826f0b17fb8d5796a7ec8ba6..5e5cc279af6036a6b3ea1f1f0fe= eddf45b85f15c 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -169,6 +169,7 @@ obj-$(CONFIG_MFD_MAX77686) +=3D max77686.o obj-$(CONFIG_MFD_MAX77693) +=3D max77693.o obj-$(CONFIG_MFD_MAX77705) +=3D max77705.o obj-$(CONFIG_MFD_MAX77714) +=3D max77714.o +obj-$(CONFIG_MFD_MAX77759) +=3D max77759.o obj-$(CONFIG_MFD_MAX77843) +=3D max77843.o obj-$(CONFIG_MFD_MAX8907) +=3D max8907.o max8925-objs :=3D max8925-core.o max8925-i2c.o diff --git a/drivers/mfd/max77759.c b/drivers/mfd/max77759.c new file mode 100644 index 0000000000000000000000000000000000000000..15723ac3ef49771eafd5c2e9984= abc550eec7aa1 --- /dev/null +++ b/drivers/mfd/max77759.c @@ -0,0 +1,690 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google Inc + * Copyright 2025 Linaro Ltd. + * + * Core driver for Maxim MAX77759 companion PMIC for USB Type-C + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Chip ID as per MAX77759_PMIC_REG_PMIC_ID */ +enum { + MAX77759_CHIP_ID =3D 59, +}; + +enum max77759_i2c_subdev_id { + /* + * These are arbitrary and simply used to match struct + * max77759_i2c_subdev entries to the regmap pointers in struct + * max77759 during probe(). + */ + MAX77759_I2C_SUBDEV_ID_MAXQ, + MAX77759_I2C_SUBDEV_ID_CHARGER, +}; + +struct max77759_i2c_subdev { + enum max77759_i2c_subdev_id id; + const struct regmap_config *cfg; + u16 i2c_address; +}; + +static const struct regmap_range max77759_top_registers[] =3D { + regmap_reg_range(0x00, 0x02), /* PMIC_ID / PMIC_REVISION / OTP_REVISION */ + regmap_reg_range(0x22, 0x24), /* INTSRC / INTSRCMASK / TOPSYS_INT */ + regmap_reg_range(0x26, 0x26), /* TOPSYS_INT_MASK */ + regmap_reg_range(0x40, 0x40), /* I2C_CNFG */ + regmap_reg_range(0x50, 0x51), /* SWRESET / CONTROL_FG */ +}; + +static const struct regmap_range max77759_top_ro_registers[] =3D { + regmap_reg_range(0x00, 0x02), + regmap_reg_range(0x22, 0x22), +}; + +static const struct regmap_range max77759_top_volatile_registers[] =3D { + regmap_reg_range(0x22, 0x22), + regmap_reg_range(0x24, 0x24), +}; + +static const struct regmap_access_table max77759_top_wr_table =3D { + .yes_ranges =3D max77759_top_registers, + .n_yes_ranges =3D ARRAY_SIZE(max77759_top_registers), + .no_ranges =3D max77759_top_ro_registers, + .n_no_ranges =3D ARRAY_SIZE(max77759_top_ro_registers), +}; + +static const struct regmap_access_table max77759_top_rd_table =3D { + .yes_ranges =3D max77759_top_registers, + .n_yes_ranges =3D ARRAY_SIZE(max77759_top_registers), +}; + +static const struct regmap_access_table max77759_top_volatile_table =3D { + .yes_ranges =3D max77759_top_volatile_registers, + .n_yes_ranges =3D ARRAY_SIZE(max77759_top_volatile_registers), +}; + +static const struct regmap_config max77759_regmap_config_top =3D { + .name =3D "top", + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D MAX77759_PMIC_REG_CONTROL_FG, + .wr_table =3D &max77759_top_wr_table, + .rd_table =3D &max77759_top_rd_table, + .volatile_table =3D &max77759_top_volatile_table, + .num_reg_defaults_raw =3D MAX77759_PMIC_REG_CONTROL_FG + 1, + .cache_type =3D REGCACHE_FLAT, +}; + +static const struct regmap_range max77759_maxq_registers[] =3D { + regmap_reg_range(0x60, 0x73), /* Device ID, Rev, INTx, STATUSx, MASKx */ + regmap_reg_range(0x81, 0xa1), /* AP_DATAOUTx */ + regmap_reg_range(0xb1, 0xd1), /* AP_DATAINx */ + regmap_reg_range(0xe0, 0xe0), /* UIC_SWRST */ +}; + +static const struct regmap_range max77759_maxq_ro_registers[] =3D { + regmap_reg_range(0x60, 0x63), /* Device ID, Rev */ + regmap_reg_range(0x68, 0x6f), /* STATUSx */ + regmap_reg_range(0xb1, 0xd1), +}; + +static const struct regmap_range max77759_maxq_volatile_registers[] =3D { + regmap_reg_range(0x64, 0x6f), /* INTx, STATUSx */ + regmap_reg_range(0xb1, 0xd1), + regmap_reg_range(0xe0, 0xe0), +}; + +static const struct regmap_access_table max77759_maxq_wr_table =3D { + .yes_ranges =3D max77759_maxq_registers, + .n_yes_ranges =3D ARRAY_SIZE(max77759_maxq_registers), + .no_ranges =3D max77759_maxq_ro_registers, + .n_no_ranges =3D ARRAY_SIZE(max77759_maxq_ro_registers), +}; + +static const struct regmap_access_table max77759_maxq_rd_table =3D { + .yes_ranges =3D max77759_maxq_registers, + .n_yes_ranges =3D ARRAY_SIZE(max77759_maxq_registers), +}; + +static const struct regmap_access_table max77759_maxq_volatile_table =3D { + .yes_ranges =3D max77759_maxq_volatile_registers, + .n_yes_ranges =3D ARRAY_SIZE(max77759_maxq_volatile_registers), +}; + +static const struct regmap_config max77759_regmap_config_maxq =3D { + .name =3D "maxq", + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D MAX77759_MAXQ_REG_UIC_SWRST, + .wr_table =3D &max77759_maxq_wr_table, + .rd_table =3D &max77759_maxq_rd_table, + .volatile_table =3D &max77759_maxq_volatile_table, + .num_reg_defaults_raw =3D MAX77759_MAXQ_REG_UIC_SWRST + 1, + .cache_type =3D REGCACHE_FLAT, +}; + +static const struct regmap_range max77759_charger_registers[] =3D { + regmap_reg_range(0xb0, 0xcc), +}; + +static const struct regmap_range max77759_charger_ro_registers[] =3D { + regmap_reg_range(0xb4, 0xb8), /* INT_OK, DETAILS_0x */ +}; + +static const struct regmap_range max77759_charger_volatile_registers[] =3D= { + regmap_reg_range(0xb0, 0xb1), /* INTx */ + regmap_reg_range(0xb4, 0xb8), +}; + +static const struct regmap_access_table max77759_charger_wr_table =3D { + .yes_ranges =3D max77759_charger_registers, + .n_yes_ranges =3D ARRAY_SIZE(max77759_charger_registers), + .no_ranges =3D max77759_charger_ro_registers, + .n_no_ranges =3D ARRAY_SIZE(max77759_charger_ro_registers), +}; + +static const struct regmap_access_table max77759_charger_rd_table =3D { + .yes_ranges =3D max77759_charger_registers, + .n_yes_ranges =3D ARRAY_SIZE(max77759_charger_registers), +}; + +static const struct regmap_access_table max77759_charger_volatile_table = =3D { + .yes_ranges =3D max77759_charger_volatile_registers, + .n_yes_ranges =3D ARRAY_SIZE(max77759_charger_volatile_registers), +}; + +static const struct regmap_config max77759_regmap_config_charger =3D { + .name =3D "charger", + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D MAX77759_CHGR_REG_CHG_CNFG_19, + .wr_table =3D &max77759_charger_wr_table, + .rd_table =3D &max77759_charger_rd_table, + .volatile_table =3D &max77759_charger_volatile_table, + .num_reg_defaults_raw =3D MAX77759_CHGR_REG_CHG_CNFG_19 + 1, + .cache_type =3D REGCACHE_FLAT, +}; + +/* + * Interrupts - with the following interrupt hierarchy: + * pmic IRQs (INTSRC) + * - MAXQ_INT: MaxQ IRQs + * - UIC_INT1 + * - APCmdResI + * - SysMsgI + * - GPIOxI + * - TOPSYS_INT: topsys + * - TOPSYS_INT + * - TSHDN_INT + * - SYSOVLO_INT + * - SYSUVLO_INT + * - FSHIP_NOT_RD + * - CHGR_INT: charger + * - CHG_INT + * - CHG_INT2 + */ +enum { + MAX77759_INT_MAXQ, + MAX77759_INT_TOPSYS, + MAX77759_INT_CHGR, +}; + +enum { + MAX77759_TOPSYS_INT_TSHDN, + MAX77759_TOPSYS_INT_SYSOVLO, + MAX77759_TOPSYS_INT_SYSUVLO, + MAX77759_TOPSYS_INT_FSHIP_NOT_RD, +}; + +enum { + MAX77759_MAXQ_INT_APCMDRESI, + MAX77759_MAXQ_INT_SYSMSGI, + MAX77759_MAXQ_INT_GPIO, + MAX77759_MAXQ_INT_UIC1, + MAX77759_MAXQ_INT_UIC2, + MAX77759_MAXQ_INT_UIC3, + MAX77759_MAXQ_INT_UIC4, +}; + +enum { + MAX77759_CHARGER_INT_1, + MAX77759_CHARGER_INT_2, +}; + +static const struct regmap_irq max77759_pmic_irqs[] =3D { + REGMAP_IRQ_REG(MAX77759_INT_MAXQ, 0, MAX77759_PMIC_REG_INTSRC_MAXQ), + REGMAP_IRQ_REG(MAX77759_INT_TOPSYS, 0, MAX77759_PMIC_REG_INTSRC_TOPSYS), + REGMAP_IRQ_REG(MAX77759_INT_CHGR, 0, MAX77759_PMIC_REG_INTSRC_CHGR), +}; + +static const struct regmap_irq max77759_maxq_irqs[] =3D { + REGMAP_IRQ_REG(MAX77759_MAXQ_INT_APCMDRESI, 0, MAX77759_MAXQ_REG_UIC_INT1= _APCMDRESI), + REGMAP_IRQ_REG(MAX77759_MAXQ_INT_SYSMSGI, 0, MAX77759_MAXQ_REG_UIC_INT1_S= YSMSGI), + REGMAP_IRQ_REG(MAX77759_MAXQ_INT_GPIO, 0, GENMASK(1, 0)), + REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC1, 0, GENMASK(5, 2)), + REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC2, 1, GENMASK(7, 0)), + REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC3, 2, GENMASK(7, 0)), + REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC4, 3, GENMASK(7, 0)), +}; + +static const struct regmap_irq max77759_topsys_irqs[] =3D { + REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_TSHDN, 0, MAX77759_PMIC_REG_TOPSYS_INT= _TSHDN), + REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_SYSOVLO, 0, MAX77759_PMIC_REG_TOPSYS_I= NT_SYSOVLO), + REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_SYSUVLO, 0, MAX77759_PMIC_REG_TOPSYS_I= NT_SYSUVLO), + REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_FSHIP_NOT_RD, 0, MAX77759_PMIC_REG_TOP= SYS_INT_FSHIP), +}; + +static const struct regmap_irq max77759_chgr_irqs[] =3D { + REGMAP_IRQ_REG(MAX77759_CHARGER_INT_1, 0, GENMASK(7, 0)), + REGMAP_IRQ_REG(MAX77759_CHARGER_INT_2, 1, GENMASK(7, 0)), +}; + +static const struct regmap_irq_chip max77759_pmic_irq_chip =3D { + .name =3D "max77759-pmic", + /* INTSRC is read-only and doesn't require clearing */ + .status_base =3D MAX77759_PMIC_REG_INTSRC, + .mask_base =3D MAX77759_PMIC_REG_INTSRCMASK, + .num_regs =3D 1, + .irqs =3D max77759_pmic_irqs, + .num_irqs =3D ARRAY_SIZE(max77759_pmic_irqs), +}; + +/* + * We can let regmap-irq auto-ack the topsys interrupt bits as required, b= ut + * for all others the individual drivers need to know which interrupt bit + * exactly is set inside their interrupt handlers, and therefore we can no= t set + * .ack_base for those. + */ +static const struct regmap_irq_chip max77759_maxq_irq_chip =3D { + .name =3D "max77759-maxq", + .domain_suffix =3D "MAXQ", + .status_base =3D MAX77759_MAXQ_REG_UIC_INT1, + .mask_base =3D MAX77759_MAXQ_REG_UIC_INT1_M, + .num_regs =3D 4, + .irqs =3D max77759_maxq_irqs, + .num_irqs =3D ARRAY_SIZE(max77759_maxq_irqs), +}; + +static const struct regmap_irq_chip max77759_topsys_irq_chip =3D { + .name =3D "max77759-topsys", + .domain_suffix =3D "TOPSYS", + .status_base =3D MAX77759_PMIC_REG_TOPSYS_INT, + .mask_base =3D MAX77759_PMIC_REG_TOPSYS_INT_MASK, + .ack_base =3D MAX77759_PMIC_REG_TOPSYS_INT, + .num_regs =3D 1, + .irqs =3D max77759_topsys_irqs, + .num_irqs =3D ARRAY_SIZE(max77759_topsys_irqs), +}; + +static const struct regmap_irq_chip max77759_chrg_irq_chip =3D { + .name =3D "max77759-chgr", + .domain_suffix =3D "CHGR", + .status_base =3D MAX77759_CHGR_REG_CHG_INT, + .mask_base =3D MAX77759_CHGR_REG_CHG_INT_MASK, + .num_regs =3D 2, + .irqs =3D max77759_chgr_irqs, + .num_irqs =3D ARRAY_SIZE(max77759_chgr_irqs), +}; + +static const struct max77759_i2c_subdev max77759_i2c_subdevs[] =3D { + { + .id =3D MAX77759_I2C_SUBDEV_ID_MAXQ, + .cfg =3D &max77759_regmap_config_maxq, + /* I2C address is same as for sub-block 'top' */ + }, + { + .id =3D MAX77759_I2C_SUBDEV_ID_CHARGER, + .cfg =3D &max77759_regmap_config_charger, + .i2c_address =3D 0x69, + }, +}; + +static const struct resource max77759_gpio_resources[] =3D { + DEFINE_RES_IRQ_NAMED(MAX77759_MAXQ_INT_GPIO, "GPI"), +}; + +static const struct resource max77759_charger_resources[] =3D { + DEFINE_RES_IRQ_NAMED(MAX77759_CHARGER_INT_1, "INT1"), + DEFINE_RES_IRQ_NAMED(MAX77759_CHARGER_INT_2, "INT2"), +}; + +static const struct mfd_cell max77759_cells[] =3D { + MFD_CELL_OF("max77759-nvmem", NULL, NULL, 0, 0, + "maxim,max77759-nvmem"), +}; + +static const struct mfd_cell max77759_maxq_cells[] =3D { + MFD_CELL_OF("max77759-gpio", max77759_gpio_resources, NULL, 0, 0, + "maxim,max77759-gpio"), +}; + +static const struct mfd_cell max77759_charger_cells[] =3D { + MFD_CELL_RES("max77759-charger", max77759_charger_resources), +}; + +int max77759_maxq_command(struct max77759 *max77759, + const struct max77759_maxq_command *cmd, + struct max77759_maxq_response *rsp) +{ + DEFINE_FLEX(struct max77759_maxq_response, _rsp, rsp, length, 1); + struct device *dev =3D regmap_get_device(max77759->regmap_maxq); + static const unsigned int timeout_ms =3D 200; + int ret; + + if (cmd->length > MAX77759_MAXQ_OPCODE_MAXLENGTH) + return -EINVAL; + + /* + * As a convenience for API users when issuing simple commands, rsp is + * allowed to be NULL. In that case we need a temporary here to write + * the response to, as we need to verify that the command was indeed + * completed correctly. + */ + if (!rsp) + rsp =3D _rsp; + + if (!rsp->length || rsp->length > MAX77759_MAXQ_OPCODE_MAXLENGTH) + return -EINVAL; + + guard(mutex)(&max77759->maxq_lock); + + reinit_completion(&max77759->cmd_done); + + /* + * MaxQ latches the message when the DATAOUT32 register is written. If + * cmd->length is shorter we still need to write 0 to it. + */ + ret =3D regmap_bulk_write(max77759->regmap_maxq, + MAX77759_MAXQ_REG_AP_DATAOUT0, cmd->cmd, + cmd->length); + if (!ret && cmd->length < MAX77759_MAXQ_OPCODE_MAXLENGTH) + ret =3D regmap_write(max77759->regmap_maxq, + MAX77759_MAXQ_REG_AP_DATAOUT32, 0); + if (ret) { + dev_err(dev, "writing command failed: %d\n", ret); + return ret; + } + + /* wait for response from MaxQ */ + if (!wait_for_completion_timeout(&max77759->cmd_done, + msecs_to_jiffies(timeout_ms))) { + dev_err(dev, "timed out waiting for response\n"); + return -ETIMEDOUT; + } + + ret =3D regmap_bulk_read(max77759->regmap_maxq, + MAX77759_MAXQ_REG_AP_DATAIN0, + rsp->rsp, rsp->length); + if (ret) { + dev_err(dev, "reading response failed: %d\n", ret); + return ret; + } + + /* + * As per the protocol, the first byte of the reply will match the + * request. + */ + if (cmd->cmd[0] !=3D rsp->rsp[0]) { + dev_err(dev, "unexpected opcode response for %#.2x: %*ph\n", + cmd->cmd[0], (int)rsp->length, rsp->rsp); + return -EIO; + } + + return 0; +} +EXPORT_SYMBOL_GPL(max77759_maxq_command); + +static irqreturn_t apcmdres_irq_handler(int irq, void *irq_data) +{ + struct max77759 *max77759 =3D irq_data; + + regmap_write(max77759->regmap_maxq, MAX77759_MAXQ_REG_UIC_INT1, + MAX77759_MAXQ_REG_UIC_INT1_APCMDRESI); + + complete(&max77759->cmd_done); + + return IRQ_HANDLED; +} + +static int max77759_create_i2c_subdev(struct i2c_client *client, + struct max77759 *max77759, + const struct max77759_i2c_subdev *sd) +{ + struct i2c_client *sub; + struct regmap *regmap; + int ret; + + /* + * If 'sd' has an I2C address, 'sub' will be assigned a new 'dummy' + * device, otherwise use it as-is. + */ + sub =3D client; + if (sd->i2c_address) { + sub =3D devm_i2c_new_dummy_device(&client->dev, + client->adapter, + sd->i2c_address); + + if (IS_ERR(sub)) + return dev_err_probe(&client->dev, PTR_ERR(sub), + "failed to claim I2C device %s\n", + sd->cfg->name); + } + + regmap =3D devm_regmap_init_i2c(sub, sd->cfg); + if (IS_ERR(regmap)) + return dev_err_probe(&sub->dev, PTR_ERR(regmap), + "regmap init for '%s' failed\n", + sd->cfg->name); + + ret =3D regmap_attach_dev(&client->dev, regmap, sd->cfg); + if (ret) + return dev_err_probe(&client->dev, ret, + "regmap attach of '%s' failed\n", + sd->cfg->name); + + if (sd->id =3D=3D MAX77759_I2C_SUBDEV_ID_MAXQ) + max77759->regmap_maxq =3D regmap; + else if (sd->id =3D=3D MAX77759_I2C_SUBDEV_ID_CHARGER) + max77759->regmap_charger =3D regmap; + + return 0; +} + +static int max77759_add_chained_irq_chip(struct device *dev, + struct regmap *regmap, + int pirq, + struct regmap_irq_chip_data *parent, + const struct regmap_irq_chip *chip, + struct regmap_irq_chip_data **data) +{ + int irq, ret; + + irq =3D regmap_irq_get_virq(parent, pirq); + if (irq < 0) + return dev_err_probe(dev, irq, + "failed to get parent vIRQ(%d) for chip %s\n", + pirq, chip->name); + + ret =3D devm_regmap_add_irq_chip(dev, regmap, irq, + IRQF_ONESHOT | IRQF_SHARED, 0, chip, + data); + if (ret) + return dev_err_probe(dev, ret, "failed to add %s IRQ chip\n", + chip->name); + + return 0; +} + +static int max77759_add_chained_maxq(struct i2c_client *client, + struct max77759 *max77759, + struct regmap_irq_chip_data *parent) +{ + struct regmap_irq_chip_data *irq_chip_data; + int apcmdres_irq; + int ret; + + ret =3D max77759_add_chained_irq_chip(&client->dev, + max77759->regmap_maxq, + MAX77759_INT_MAXQ, + parent, + &max77759_maxq_irq_chip, + &irq_chip_data); + if (ret) + return ret; + + init_completion(&max77759->cmd_done); + apcmdres_irq =3D regmap_irq_get_virq(irq_chip_data, + MAX77759_MAXQ_INT_APCMDRESI); + + ret =3D devm_request_threaded_irq(&client->dev, apcmdres_irq, + NULL, apcmdres_irq_handler, + IRQF_ONESHOT | IRQF_SHARED, + dev_name(&client->dev), max77759); + if (ret) + return dev_err_probe(&client->dev, ret, + "MAX77759_MAXQ_INT_APCMDRESI failed\n"); + + ret =3D devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, + max77759_maxq_cells, + ARRAY_SIZE(max77759_maxq_cells), + NULL, 0, + regmap_irq_get_domain(irq_chip_data)); + if (ret) + return dev_err_probe(&client->dev, ret, + "failed to add child devices (MaxQ)\n"); + + return 0; +} + +static int max77759_add_chained_topsys(struct i2c_client *client, + struct max77759 *max77759, + struct regmap_irq_chip_data *parent) +{ + struct regmap_irq_chip_data *irq_chip_data; + int ret; + + ret =3D max77759_add_chained_irq_chip(&client->dev, + max77759->regmap_top, + MAX77759_INT_TOPSYS, + parent, + &max77759_topsys_irq_chip, + &irq_chip_data); + if (ret) + return ret; + + return 0; +} + +static int max77759_add_chained_charger(struct i2c_client *client, + struct max77759 *max77759, + struct regmap_irq_chip_data *parent) +{ + struct regmap_irq_chip_data *irq_chip_data; + int ret; + + ret =3D max77759_add_chained_irq_chip(&client->dev, + max77759->regmap_charger, + MAX77759_INT_CHGR, + parent, + &max77759_chrg_irq_chip, + &irq_chip_data); + if (ret) + return ret; + + ret =3D devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, + max77759_charger_cells, + ARRAY_SIZE(max77759_charger_cells), + NULL, 0, + regmap_irq_get_domain(irq_chip_data)); + if (ret) + return dev_err_probe(&client->dev, ret, + "failed to add child devices (charger)\n"); + + return 0; +} + +static int max77759_probe(struct i2c_client *client) +{ + struct regmap_irq_chip_data *irq_chip_data_pmic; + struct irq_data *irq_data; + struct max77759 *max77759; + unsigned long irq_flags; + unsigned int pmic_id; + int ret; + + max77759 =3D devm_kzalloc(&client->dev, sizeof(*max77759), GFP_KERNEL); + if (!max77759) + return -ENOMEM; + + i2c_set_clientdata(client, max77759); + + max77759->regmap_top =3D devm_regmap_init_i2c(client, + &max77759_regmap_config_top); + if (IS_ERR(max77759->regmap_top)) + return dev_err_probe(&client->dev, PTR_ERR(max77759->regmap_top), + "regmap init for '%s' failed\n", + max77759_regmap_config_top.name); + + ret =3D regmap_read(max77759->regmap_top, + MAX77759_PMIC_REG_PMIC_ID, &pmic_id); + if (ret) + return dev_err_probe(&client->dev, ret, + "unable to read device ID\n"); + + if (pmic_id !=3D MAX77759_CHIP_ID) + return dev_err_probe(&client->dev, -ENODEV, + "unsupported device ID %#.2x (%d)\n", + pmic_id, pmic_id); + + ret =3D devm_mutex_init(&client->dev, &max77759->maxq_lock); + if (ret) + return ret; + + for (int i =3D 0; i < ARRAY_SIZE(max77759_i2c_subdevs); i++) { + ret =3D max77759_create_i2c_subdev(client, max77759, + &max77759_i2c_subdevs[i]); + if (ret) + return ret; + } + + irq_data =3D irq_get_irq_data(client->irq); + if (!irq_data) + return dev_err_probe(&client->dev, -EINVAL, + "invalid IRQ: %d\n", client->irq); + + irq_flags =3D IRQF_ONESHOT | IRQF_SHARED; + irq_flags |=3D irqd_get_trigger_type(irq_data); + + ret =3D devm_regmap_add_irq_chip(&client->dev, max77759->regmap_top, + client->irq, irq_flags, 0, + &max77759_pmic_irq_chip, + &irq_chip_data_pmic); + if (ret) + return dev_err_probe(&client->dev, ret, + "failed to add IRQ chip '%s'\n", + max77759_pmic_irq_chip.name); + + ret =3D max77759_add_chained_maxq(client, max77759, irq_chip_data_pmic); + if (ret) + return ret; + + ret =3D max77759_add_chained_topsys(client, max77759, irq_chip_data_pmic); + if (ret) + return ret; + + ret =3D max77759_add_chained_charger(client, max77759, irq_chip_data_pmic= ); + if (ret) + return ret; + + return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, + max77759_cells, ARRAY_SIZE(max77759_cells), + NULL, 0, + regmap_irq_get_domain(irq_chip_data_pmic)); +} + +static const struct i2c_device_id max77759_i2c_id[] =3D { + { "max77759" }, + { } +}; +MODULE_DEVICE_TABLE(i2c, max77759_i2c_id); + +static const struct of_device_id max77759_of_id[] =3D { + { .compatible =3D "maxim,max77759", }, + { } +}; +MODULE_DEVICE_TABLE(of, max77759_of_id); + +static struct i2c_driver max77759_i2c_driver =3D { + .driver =3D { + .name =3D "max77759", + .of_match_table =3D max77759_of_id, + }, + .probe =3D max77759_probe, + .id_table =3D max77759_i2c_id, +}; +module_i2c_driver(max77759_i2c_driver); + +MODULE_AUTHOR("Andr=C3=A9 Draszik "); +MODULE_DESCRIPTION("Maxim MAX77759 core driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/max77759.h b/include/linux/mfd/max77759.h new file mode 100644 index 0000000000000000000000000000000000000000..c6face34e38555cbc09db413192= 5b6ed781af511 --- /dev/null +++ b/include/linux/mfd/max77759.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Google Inc. + * Copyright 2025 Linaro Ltd. + * + * Maxim MAX77759 core driver + */ + +#ifndef __LINUX_MFD_MAX77759_H +#define __LINUX_MFD_MAX77759_H + +#include +#include +#include + +#define MAX77759_PMIC_REG_PMIC_ID 0x00 +#define MAX77759_PMIC_REG_PMIC_REVISION 0x01 +#define MAX77759_PMIC_REG_OTP_REVISION 0x02 +#define MAX77759_PMIC_REG_INTSRC 0x22 +#define MAX77759_PMIC_REG_INTSRCMASK 0x23 +#define MAX77759_PMIC_REG_INTSRC_MAXQ BIT(3) +#define MAX77759_PMIC_REG_INTSRC_TOPSYS BIT(1) +#define MAX77759_PMIC_REG_INTSRC_CHGR BIT(0) +#define MAX77759_PMIC_REG_TOPSYS_INT 0x24 +#define MAX77759_PMIC_REG_TOPSYS_INT_MASK 0x26 +#define MAX77759_PMIC_REG_TOPSYS_INT_TSHDN BIT(6) +#define MAX77759_PMIC_REG_TOPSYS_INT_SYSOVLO BIT(5) +#define MAX77759_PMIC_REG_TOPSYS_INT_SYSUVLO BIT(4) +#define MAX77759_PMIC_REG_TOPSYS_INT_FSHIP BIT(0) +#define MAX77759_PMIC_REG_I2C_CNFG 0x40 +#define MAX77759_PMIC_REG_SWRESET 0x50 +#define MAX77759_PMIC_REG_CONTROL_FG 0x51 + +#define MAX77759_MAXQ_REG_UIC_INT1 0x64 +#define MAX77759_MAXQ_REG_UIC_INT1_APCMDRESI BIT(7) +#define MAX77759_MAXQ_REG_UIC_INT1_SYSMSGI BIT(6) +#define MAX77759_MAXQ_REG_UIC_INT1_GPIO6I BIT(1) +#define MAX77759_MAXQ_REG_UIC_INT1_GPIO5I BIT(0) +#define MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(offs, en) (((en) & 1) << (off= s)) +#define MAX77759_MAXQ_REG_UIC_INT1_GPIOxI_MASK(offs) \ + MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(offs, ~0) +#define MAX77759_MAXQ_REG_UIC_INT2 0x65 +#define MAX77759_MAXQ_REG_UIC_INT3 0x66 +#define MAX77759_MAXQ_REG_UIC_INT4 0x67 +#define MAX77759_MAXQ_REG_UIC_UIC_STATUS1 0x68 +#define MAX77759_MAXQ_REG_UIC_UIC_STATUS2 0x69 +#define MAX77759_MAXQ_REG_UIC_UIC_STATUS3 0x6a +#define MAX77759_MAXQ_REG_UIC_UIC_STATUS4 0x6b +#define MAX77759_MAXQ_REG_UIC_UIC_STATUS5 0x6c +#define MAX77759_MAXQ_REG_UIC_UIC_STATUS6 0x6d +#define MAX77759_MAXQ_REG_UIC_UIC_STATUS7 0x6f +#define MAX77759_MAXQ_REG_UIC_UIC_STATUS8 0x6f +#define MAX77759_MAXQ_REG_UIC_INT1_M 0x70 +#define MAX77759_MAXQ_REG_UIC_INT2_M 0x71 +#define MAX77759_MAXQ_REG_UIC_INT3_M 0x72 +#define MAX77759_MAXQ_REG_UIC_INT4_M 0x73 +#define MAX77759_MAXQ_REG_AP_DATAOUT0 0x81 +#define MAX77759_MAXQ_REG_AP_DATAOUT32 0xa1 +#define MAX77759_MAXQ_REG_AP_DATAIN0 0xb1 +#define MAX77759_MAXQ_REG_UIC_SWRST 0xe0 + +#define MAX77759_CHGR_REG_CHG_INT 0xb0 +#define MAX77759_CHGR_REG_CHG_INT2 0xb1 +#define MAX77759_CHGR_REG_CHG_INT_MASK 0xb2 +#define MAX77759_CHGR_REG_CHG_INT2_MASK 0xb3 +#define MAX77759_CHGR_REG_CHG_INT_OK 0xb4 +#define MAX77759_CHGR_REG_CHG_DETAILS_00 0xb5 +#define MAX77759_CHGR_REG_CHG_DETAILS_01 0xb6 +#define MAX77759_CHGR_REG_CHG_DETAILS_02 0xb7 +#define MAX77759_CHGR_REG_CHG_DETAILS_03 0xb8 +#define MAX77759_CHGR_REG_CHG_CNFG_00 0xb9 +#define MAX77759_CHGR_REG_CHG_CNFG_01 0xba +#define MAX77759_CHGR_REG_CHG_CNFG_02 0xbb +#define MAX77759_CHGR_REG_CHG_CNFG_03 0xbc +#define MAX77759_CHGR_REG_CHG_CNFG_04 0xbd +#define MAX77759_CHGR_REG_CHG_CNFG_05 0xbe +#define MAX77759_CHGR_REG_CHG_CNFG_06 0xbf +#define MAX77759_CHGR_REG_CHG_CNFG_07 0xc0 +#define MAX77759_CHGR_REG_CHG_CNFG_08 0xc1 +#define MAX77759_CHGR_REG_CHG_CNFG_09 0xc2 +#define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3 +#define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4 +#define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5 +#define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6 +#define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7 +#define MAX77759_CHGR_REG_CHG_CNFG_15 0xc8 +#define MAX77759_CHGR_REG_CHG_CNFG_16 0xc9 +#define MAX77759_CHGR_REG_CHG_CNFG_17 0xca +#define MAX77759_CHGR_REG_CHG_CNFG_18 0xcb +#define MAX77759_CHGR_REG_CHG_CNFG_19 0xcc + +/* MaxQ opcodes for max77759_maxq_command() */ +#define MAX77759_MAXQ_OPCODE_MAXLENGTH (MAX77759_MAXQ_REG_AP_DATAOUT32 - \ + MAX77759_MAXQ_REG_AP_DATAOUT0 + \ + 1) + +#define MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_READ 0x21 +#define MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_WRITE 0x22 +#define MAX77759_MAXQ_OPCODE_GPIO_CONTROL_READ 0x23 +#define MAX77759_MAXQ_OPCODE_GPIO_CONTROL_WRITE 0x24 +#define MAX77759_MAXQ_OPCODE_USER_SPACE_READ 0x81 +#define MAX77759_MAXQ_OPCODE_USER_SPACE_WRITE 0x82 + +/** + * struct max77759 - core max77759 internal data structure + * + * @regmap_top: Regmap for accessing TOP registers + * @maxq_lock: Lock for serializing access to MaxQ + * @regmap_maxq: Regmap for accessing MaxQ registers + * @cmd_done: Used to signal completion of a MaxQ command + * @regmap_charger: Regmap for accessing charger registers + * + * The MAX77759 comprises several sub-blocks, namely TOP, MaxQ, Charger, + * Fuel Gauge, and TCPCI. + */ +struct max77759 { + struct regmap *regmap_top; + + /* This protects MaxQ commands - only one can be active */ + struct mutex maxq_lock; + struct regmap *regmap_maxq; + struct completion cmd_done; + + struct regmap *regmap_charger; +}; + +/** + * struct max77759_maxq_command - structure containing the MaxQ command to + * send + * + * @length: The number of bytes to send. + * @cmd: The data to send. + */ +struct max77759_maxq_command { + u8 length; + u8 cmd[] __counted_by(length); +}; + +/** + * struct max77759_maxq_response - structure containing the MaxQ response + * + * @length: The number of bytes to receive. + * @rsp: The data received. Must have at least @length bytes space. + */ +struct max77759_maxq_response { + u8 length; + u8 rsp[] __counted_by(length); +}; + +/** + * max77759_maxq_command() - issue a MaxQ command and wait for the response + * and associated data + * + * @max77759: The core max77759 device handle. + * @cmd: The command to be sent. + * @rsp: Any response data associated with the command will be copied here; + * can be %NULL if the command has no response (other than ACK). + * + * Return: 0 on success, a negative error number otherwise. + */ +int max77759_maxq_command(struct max77759 *max77759, + const struct max77759_maxq_command *cmd, + struct max77759_maxq_response *rsp); + +#endif /* __LINUX_MFD_MAX77759_H */ --=20 2.49.0.901.g37484f566f-goog From nobody Tue Feb 10 00:44:18 2026 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F30521CA0F for ; Wed, 30 Apr 2025 09:03:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003801; cv=none; b=ckucmZ1PFYm9TG73VrcvwBVXrVGY5eX6dCiqdp93gUsqCdVSRsaRWB5DOUkIS/ooOTGnQlmBRiEBTtq1yUSoKv20RuddMAN/q7GmWa8I3vwtR8OB+tWDgjBSxQ8hK9jNEw+2d9ksLgv7TFBan8vo7WNVEbZIMuoppxtKiRsHCmU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003801; c=relaxed/simple; bh=XqoIewFhHfNmVYOpePvM3e9Sq5HQyuI/EA+aQi/NHYc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KyJY3oJofFy5SvoEHXeENmURNfA91z5idoHse7galClSAbihIBIZtdc9azTvnjg2MKo0WauhXeWkFJeM1qQe8GUd+f+tEUOak9coeRmoM8Zvmd4M+PkrSDoaK1Mnz/Ok9ilv1Yc0yyiy8uSfCwXIwGsoG1qEl0pMR2HgFpiC/DA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ysRjeioy; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ysRjeioy" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-5edc07c777eso8801034a12.3 for ; Wed, 30 Apr 2025 02:03:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746003795; x=1746608595; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=51WfKLwzr7VTpMyREiuoFgn/xarlpLYCgMiyf4+NwUo=; b=ysRjeioypI0pg500Fe16vbUoa78LiB8Hy058FZsJHc8Q+uMSzSDLY1pKlSv24FigoO sqUsqqOp9FhPkN72h6ppw1AFxD9QjzT1h+kZTHUjqEYJcJAZBKFniCpi7sCBUWQ5517C 8tat7akAmgqvKmxzi69jGIafyhdDDSYzgYyMPzS0ZludCrUKQJ1vHAc96rSimFrT6iq1 NGkRrT7fh4/sxW4IUY0utPTBoa9wTUfPCemSn8R5W2ZAalSnWWM/Ojl6AJ3WwUHRCYVn Y5rbTbWsQc2gRmDZ+IikkXKdVP5M85UpFZaFM7mveKboDEkLRxTVBCy5bsKOLOHdUuA0 yFgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746003795; x=1746608595; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=51WfKLwzr7VTpMyREiuoFgn/xarlpLYCgMiyf4+NwUo=; b=l6zIeAGJHeN7DlBsh76M+f5DzsOQsdPplK9MTKJcGFSmb7FK0loU0Ot57DTXT7HILH tfxL3py8xj3E4NXp7VRFn0jK5aO6N645y/cadNS4uGLEhQeUftr+KD8M3yXpUIdLgFcg v1YpqQfdbo0qusqxaR/XTbKmfHy5aS/lfWQWdQZtSk05RiOR8y3BrTVvyqkr6SApF5kz X9GmSHJ/PwRxPXTSfL6xD614L0cplIEcMhOZ15No2wcqgjnoeHXiPhsOsnKtuR6suruE qi9duqcPwb79T9E6Vm9VBwHeKsY6zaajl+hNBgD+gkQCxWvrWA65H2RreoKBI4d1iGVN kVmw== X-Forwarded-Encrypted: i=1; AJvYcCVxCVkbXuwqWeErkjVDKXH19XgcEGwcyhmUVkuh+MqocMiM/6Qup69gBG+kXcAqCRHE9kwTDctpon62Ceo=@vger.kernel.org X-Gm-Message-State: AOJu0YzT4et2YdagKvcwgbmzydan2MFVi4Y3F0eVBfn0y/apPRmzK2gj idJpNZwHUiv0nfwTDt3a+URcBWmQKYrvDit67DWLYpaJ7Fk536xDem896Eb7B+I= X-Gm-Gg: ASbGnctN2Fjj5FNvIr2cWMNOfVBaUb3OzwaE2q1bSPnuHSwFAdJNuJnAHPRkvJM8um2 bhoDDtgwGtjdsj0eddHpSoGxPdwRHBcav3ycaQOpHO3Gt4RaBOeNmcGqKq+xHBEcsvIT9fWwYEo FgY7JSJ5fWkb5t0+/pViDJTbclVkpAyjPSyQblpGvTV4et4EieZMNJPWZ2MmiA/ehG4E6oLbM6M Jw3nNBQfok1yG1WvpJpbf+BBh4aS68P+p7brw9zHDsfwc+d95RuR+JYJ48cGnuJVfzdt0OLFfyG 2wYYP63fykjwCLSw2bbzZ+52ba7KfEXndXgXDaellhjHnBhTcSDApq8visT1x64lRcvsRIKfk5P cuYL7+lOuP+bIMEpyTQYFY+z2 X-Google-Smtp-Source: AGHT+IEzi5VezjW91w/fsxeBdw9eUtZwPcwXU11ZQMX0lMnSeiOSz5XWRXwqOY+cBo44nlRQ+nNexA== X-Received: by 2002:a17:907:3f98:b0:ac7:3323:cfd8 with SMTP id a640c23a62f3a-acedc5cf5ffmr258471566b.16.1746003794947; Wed, 30 Apr 2025 02:03:14 -0700 (PDT) Received: from puffmais.c.googlers.com (8.239.204.35.bc.googleusercontent.com. [35.204.239.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6e41bbb6sm889676766b.28.2025.04.30.02.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 02:03:14 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 30 Apr 2025 10:03:12 +0100 Subject: [PATCH v9 5/6] gpio: max77759: add Maxim MAX77759 gpio driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-max77759-mfd-v9-5-639763e23598@linaro.org> References: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> In-Reply-To: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Srinivas Kandagatla , Kees Cook , "Gustavo A. R. Silva" Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-hardening@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Bartosz Golaszewski X-Mailer: b4 0.14.2 The Maxim MAX77759 is a companion PMIC for USB Type-C applications and includes Battery Charger, Fuel Gauge, temperature sensors, USB Type-C Port Controller (TCPC), NVMEM, and a GPIO expander. This driver supports the GPIO functions using the platform device registered by the core MFD driver. Acked-by: Bartosz Golaszewski Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Linus Walleij --- v8: * switch to gpio_chip::set_rv() (Bartosz) * replace MODULE_ALIAS() with .id_table (Krzysztof) * drop previous tags v5: * follow API updates of max77759 core driver v3: * drop duplicate init of 'handled' variable in irq handler * use boolean with IRQ_RETVAL() (Linus) * drop 'virq' variable inside irq handler to avoid confusion (Linus) * drop assignment of struct gpio_chip::owner (Linus) v2: * fix max77759_gpio_direction_from_control() * add missing error handling of devm_mutex_init() (Christophe) * align sentinel in max77759_gpio_of_id[] with other max77759 drivers (Christophe) --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 13 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-max77759.c | 530 +++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 545 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1259d09e700a21215e8ae2facef858df5304346e..0db5e1fe64930e85265913e6a7d= d2669c645cf42 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14668,6 +14668,7 @@ M: Andr=C3=A9 Draszik L: linux-kernel@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/*/maxim,max77759*.yaml +F: drivers/gpio/gpio-max77759.c F: drivers/mfd/max77759.c F: include/linux/mfd/max77759.h =20 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 9ae806f45e19c1494d156b7f04b1882be68d3e3f..bbc71cdde9ed66b2fe69dcbc750= 8d51690d2cfa4 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1483,6 +1483,19 @@ config GPIO_MAX77650 GPIO driver for MAX77650/77651 PMIC from Maxim Semiconductor. These chips have a single pin that can be configured as GPIO. =20 +config GPIO_MAX77759 + tristate "Maxim Integrated MAX77759 GPIO support" + depends on MFD_MAX77759 + default MFD_MAX77759 + select GPIOLIB_IRQCHIP + help + GPIO driver for MAX77759 PMIC from Maxim Integrated. + There are two GPIOs available on these chips in total, both of + which can also generate interrupts. + + This driver can also be built as a module. If so, the module will be + called gpio-max77759. + config GPIO_PALMAS bool "TI PALMAS series PMICs GPIO" depends on MFD_PALMAS diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 9aabbb9cb4c61ea57833adf2edb265c204b42cdf..1abae4477ed76b88aff08e83f6d= 41e58d0b71ff5 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -106,6 +106,7 @@ obj-$(CONFIG_GPIO_MAX730X) +=3D gpio-max730x.o obj-$(CONFIG_GPIO_MAX732X) +=3D gpio-max732x.o obj-$(CONFIG_GPIO_MAX77620) +=3D gpio-max77620.o obj-$(CONFIG_GPIO_MAX77650) +=3D gpio-max77650.o +obj-$(CONFIG_GPIO_MAX77759) +=3D gpio-max77759.o obj-$(CONFIG_GPIO_MB86S7X) +=3D gpio-mb86s7x.o obj-$(CONFIG_GPIO_MC33880) +=3D gpio-mc33880.o obj-$(CONFIG_GPIO_MENZ127) +=3D gpio-menz127.o diff --git a/drivers/gpio/gpio-max77759.c b/drivers/gpio/gpio-max77759.c new file mode 100644 index 0000000000000000000000000000000000000000..7fe8e6f697d044ebf9c620f41e5= 9f150a6ae086a --- /dev/null +++ b/drivers/gpio/gpio-max77759.c @@ -0,0 +1,530 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright 2020 Google Inc +// Copyright 2025 Linaro Ltd. +// +// GPIO driver for Maxim MAX77759 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX77759_N_GPIOS ARRAY_SIZE(max77759_gpio_line_names) +static const char * const max77759_gpio_line_names[] =3D { "GPIO5", "GPIO6= " }; + +struct max77759_gpio_chip { + struct regmap *map; + struct max77759 *max77759; + struct gpio_chip gc; + struct mutex maxq_lock; /* protect MaxQ r/m/w operations */ + + struct mutex irq_lock; /* protect irq bus */ + int irq_mask; + int irq_mask_changed; + int irq_trig; + int irq_trig_changed; +}; + +#define MAX77759_GPIOx_TRIGGER(offs, val) (((val) & 1) << (offs)) +#define MAX77759_GPIOx_TRIGGER_MASK(offs) MAX77759_GPIOx_TRIGGER(offs, ~0) +enum max77759_trigger_gpio_type { + MAX77759_GPIO_TRIGGER_RISING =3D 0, + MAX77759_GPIO_TRIGGER_FALLING =3D 1 +}; + +#define MAX77759_GPIOx_DIR(offs, dir) (((dir) & 1) << (2 + (3 * (offs)))) +#define MAX77759_GPIOx_DIR_MASK(offs) MAX77759_GPIOx_DIR(offs, ~0) +enum max77759_control_gpio_dir { + MAX77759_GPIO_DIR_IN =3D 0, + MAX77759_GPIO_DIR_OUT =3D 1 +}; + +#define MAX77759_GPIOx_OUTVAL(offs, val) (((val) & 1) << (3 + (3 * (offs))= )) +#define MAX77759_GPIOx_OUTVAL_MASK(offs) MAX77759_GPIOx_OUTVAL(offs, ~0) + +#define MAX77759_GPIOx_INVAL_MASK(offs) (BIT(4) << (3 * (offs))) + +static int max77759_gpio_maxq_gpio_trigger_read(struct max77759_gpio_chip = *chip) +{ + DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 1); + DEFINE_FLEX(struct max77759_maxq_response, rsp, rsp, length, 2); + int ret; + + cmd->cmd[0] =3D MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_READ; + + ret =3D max77759_maxq_command(chip->max77759, cmd, rsp); + if (ret < 0) + return ret; + + return rsp->rsp[1]; +} + +static int max77759_gpio_maxq_gpio_trigger_write(struct max77759_gpio_chip= *chip, + u8 trigger) +{ + DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 2); + + cmd->cmd[0] =3D MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_WRITE; + cmd->cmd[1] =3D trigger; + + return max77759_maxq_command(chip->max77759, cmd, NULL); +} + +static int max77759_gpio_maxq_gpio_control_read(struct max77759_gpio_chip = *chip) +{ + DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 1); + DEFINE_FLEX(struct max77759_maxq_response, rsp, rsp, length, 2); + int ret; + + cmd->cmd[0] =3D MAX77759_MAXQ_OPCODE_GPIO_CONTROL_READ; + + ret =3D max77759_maxq_command(chip->max77759, cmd, rsp); + if (ret < 0) + return ret; + + return rsp->rsp[1]; +} + +static int max77759_gpio_maxq_gpio_control_write(struct max77759_gpio_chip= *chip, + u8 ctrl) +{ + DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 2); + + cmd->cmd[0] =3D MAX77759_MAXQ_OPCODE_GPIO_CONTROL_WRITE; + cmd->cmd[1] =3D ctrl; + + return max77759_maxq_command(chip->max77759, cmd, NULL); +} + +static int +max77759_gpio_direction_from_control(int ctrl, unsigned int offset) +{ + enum max77759_control_gpio_dir dir; + + dir =3D !!(ctrl & MAX77759_GPIOx_DIR_MASK(offset)); + return ((dir =3D=3D MAX77759_GPIO_DIR_OUT) + ? GPIO_LINE_DIRECTION_OUT + : GPIO_LINE_DIRECTION_IN); +} + +static int max77759_gpio_get_direction(struct gpio_chip *gc, + unsigned int offset) +{ + struct max77759_gpio_chip *chip =3D gpiochip_get_data(gc); + int ctrl; + + ctrl =3D max77759_gpio_maxq_gpio_control_read(chip); + if (ctrl < 0) + return ctrl; + + return max77759_gpio_direction_from_control(ctrl, offset); +} + +static int max77759_gpio_direction_helper(struct gpio_chip *gc, + unsigned int offset, + enum max77759_control_gpio_dir dir, + int value) +{ + struct max77759_gpio_chip *chip =3D gpiochip_get_data(gc); + int ctrl, new_ctrl; + + guard(mutex)(&chip->maxq_lock); + + ctrl =3D max77759_gpio_maxq_gpio_control_read(chip); + if (ctrl < 0) + return ctrl; + + new_ctrl =3D ctrl & ~MAX77759_GPIOx_DIR_MASK(offset); + new_ctrl |=3D MAX77759_GPIOx_DIR(offset, dir); + + if (dir =3D=3D MAX77759_GPIO_DIR_OUT) { + new_ctrl &=3D ~MAX77759_GPIOx_OUTVAL_MASK(offset); + new_ctrl |=3D MAX77759_GPIOx_OUTVAL(offset, value); + } + + if (new_ctrl =3D=3D ctrl) + return 0; + + return max77759_gpio_maxq_gpio_control_write(chip, new_ctrl); +} + +static int max77759_gpio_direction_input(struct gpio_chip *gc, + unsigned int offset) +{ + return max77759_gpio_direction_helper(gc, offset, + MAX77759_GPIO_DIR_IN, -1); +} + +static int max77759_gpio_direction_output(struct gpio_chip *gc, + unsigned int offset, int value) +{ + return max77759_gpio_direction_helper(gc, offset, + MAX77759_GPIO_DIR_OUT, value); +} + +static int max77759_gpio_get_value(struct gpio_chip *gc, unsigned int offs= et) +{ + struct max77759_gpio_chip *chip =3D gpiochip_get_data(gc); + int ctrl, mask; + + ctrl =3D max77759_gpio_maxq_gpio_control_read(chip); + if (ctrl < 0) + return ctrl; + + /* + * The input status bit doesn't reflect the pin state when the GPIO is + * configured as an output. Check the direction, and inspect the input + * or output bit accordingly. + */ + mask =3D ((max77759_gpio_direction_from_control(ctrl, offset) + =3D=3D GPIO_LINE_DIRECTION_IN) + ? MAX77759_GPIOx_INVAL_MASK(offset) + : MAX77759_GPIOx_OUTVAL_MASK(offset)); + + return !!(ctrl & mask); +} + +static int max77759_gpio_set_value(struct gpio_chip *gc, + unsigned int offset, int value) +{ + struct max77759_gpio_chip *chip =3D gpiochip_get_data(gc); + int ctrl, new_ctrl; + + guard(mutex)(&chip->maxq_lock); + + ctrl =3D max77759_gpio_maxq_gpio_control_read(chip); + if (ctrl < 0) + return ctrl; + + new_ctrl =3D ctrl & ~MAX77759_GPIOx_OUTVAL_MASK(offset); + new_ctrl |=3D MAX77759_GPIOx_OUTVAL(offset, value); + + if (new_ctrl =3D=3D ctrl) + return 0; + + return max77759_gpio_maxq_gpio_control_write(chip, new_ctrl); +} + +static void max77759_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct max77759_gpio_chip *chip =3D gpiochip_get_data(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + + chip->irq_mask &=3D ~MAX77759_MAXQ_REG_UIC_INT1_GPIOxI_MASK(hwirq); + chip->irq_mask |=3D MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 1); + chip->irq_mask_changed |=3D MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 1); + + gpiochip_disable_irq(gc, hwirq); +} + +static void max77759_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct max77759_gpio_chip *chip =3D gpiochip_get_data(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + + gpiochip_enable_irq(gc, hwirq); + + chip->irq_mask &=3D ~MAX77759_MAXQ_REG_UIC_INT1_GPIOxI_MASK(hwirq); + chip->irq_mask |=3D MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 0); + chip->irq_mask_changed |=3D MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 1); +} + +static int max77759_gpio_set_irq_type(struct irq_data *d, unsigned int typ= e) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct max77759_gpio_chip *chip =3D gpiochip_get_data(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + + chip->irq_trig &=3D ~MAX77759_GPIOx_TRIGGER_MASK(hwirq); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + chip->irq_trig |=3D MAX77759_GPIOx_TRIGGER(hwirq, + MAX77759_GPIO_TRIGGER_RISING); + break; + + case IRQ_TYPE_EDGE_FALLING: + chip->irq_trig |=3D MAX77759_GPIOx_TRIGGER(hwirq, + MAX77759_GPIO_TRIGGER_FALLING); + break; + + default: + return -EINVAL; + } + + chip->irq_trig_changed |=3D MAX77759_GPIOx_TRIGGER(hwirq, 1); + + return 0; +} + +static void max77759_gpio_bus_lock(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct max77759_gpio_chip *chip =3D gpiochip_get_data(gc); + + mutex_lock(&chip->irq_lock); +} + +static int max77759_gpio_bus_sync_unlock_helper(struct gpio_chip *gc, + struct max77759_gpio_chip *chip) + __must_hold(&chip->maxq_lock) +{ + int ctrl, trigger, new_trigger, new_ctrl; + unsigned long irq_trig_changed; + int offset; + int ret; + + lockdep_assert_held(&chip->maxq_lock); + + ctrl =3D max77759_gpio_maxq_gpio_control_read(chip); + trigger =3D max77759_gpio_maxq_gpio_trigger_read(chip); + if (ctrl < 0 || trigger < 0) { + dev_err(gc->parent, "failed to read current state: %d / %d\n", + ctrl, trigger); + return (ctrl < 0) ? ctrl : trigger; + } + + new_trigger =3D trigger & ~chip->irq_trig_changed; + new_trigger |=3D (chip->irq_trig & chip->irq_trig_changed); + + /* change GPIO direction if required */ + new_ctrl =3D ctrl; + irq_trig_changed =3D chip->irq_trig_changed; + for_each_set_bit(offset, &irq_trig_changed, MAX77759_N_GPIOS) { + new_ctrl &=3D ~MAX77759_GPIOx_DIR_MASK(offset); + new_ctrl |=3D MAX77759_GPIOx_DIR(offset, MAX77759_GPIO_DIR_IN); + } + + if (new_trigger !=3D trigger) { + ret =3D max77759_gpio_maxq_gpio_trigger_write(chip, new_trigger); + if (ret) { + dev_err(gc->parent, + "failed to write new trigger: %d\n", ret); + return ret; + } + } + + if (new_ctrl !=3D ctrl) { + ret =3D max77759_gpio_maxq_gpio_control_write(chip, new_ctrl); + if (ret) { + dev_err(gc->parent, + "failed to write new control: %d\n", ret); + return ret; + } + } + + chip->irq_trig_changed =3D 0; + + return 0; +} + +static void max77759_gpio_bus_sync_unlock(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct max77759_gpio_chip *chip =3D gpiochip_get_data(gc); + int ret; + + scoped_guard(mutex, &chip->maxq_lock) { + ret =3D max77759_gpio_bus_sync_unlock_helper(gc, chip); + if (ret) + goto out_unlock; + } + + ret =3D regmap_update_bits(chip->map, + MAX77759_MAXQ_REG_UIC_INT1_M, + chip->irq_mask_changed, chip->irq_mask); + if (ret) { + dev_err(gc->parent, + "failed to update UIC_INT1 irq mask: %d\n", ret); + goto out_unlock; + } + + chip->irq_mask_changed =3D 0; + +out_unlock: + mutex_unlock(&chip->irq_lock); +} + +static void max77759_gpio_irq_print_chip(struct irq_data *d, struct seq_fi= le *p) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + + seq_puts(p, dev_name(gc->parent)); +} + +static const struct irq_chip max77759_gpio_irq_chip =3D { + .irq_mask =3D max77759_gpio_irq_mask, + .irq_unmask =3D max77759_gpio_irq_unmask, + .irq_set_type =3D max77759_gpio_set_irq_type, + .irq_bus_lock =3D max77759_gpio_bus_lock, + .irq_bus_sync_unlock =3D max77759_gpio_bus_sync_unlock, + .irq_print_chip =3D max77759_gpio_irq_print_chip, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static irqreturn_t max77759_gpio_irqhandler(int irq, void *data) +{ + struct max77759_gpio_chip *chip =3D data; + struct gpio_chip *gc =3D &chip->gc; + bool handled =3D false; + + /* iterate until no interrupt is pending */ + while (true) { + unsigned int uic_int1; + int ret; + unsigned long pending; + int offset; + + ret =3D regmap_read(chip->map, MAX77759_MAXQ_REG_UIC_INT1, + &uic_int1); + if (ret < 0) { + dev_err_ratelimited(gc->parent, + "failed to read IRQ status: %d\n", + ret); + /* + * If !handled, we have looped not even once, which + * means we should return IRQ_NONE in that case (and + * of course IRQ_HANDLED otherwise). + */ + return IRQ_RETVAL(handled); + } + + pending =3D uic_int1; + pending &=3D (MAX77759_MAXQ_REG_UIC_INT1_GPIO6I + | MAX77759_MAXQ_REG_UIC_INT1_GPIO5I); + if (!pending) + break; + + for_each_set_bit(offset, &pending, MAX77759_N_GPIOS) { + /* + * ACK interrupt by writing 1 to bit 'offset', all + * others need to be written as 0. This needs to be + * done unconditionally hence regmap_set_bits() is + * inappropriate here. + */ + regmap_write(chip->map, MAX77759_MAXQ_REG_UIC_INT1, + BIT(offset)); + + handle_nested_irq(irq_find_mapping(gc->irq.domain, + offset)); + + handled =3D true; + } + } + + return IRQ_RETVAL(handled); +} + +static int max77759_gpio_probe(struct platform_device *pdev) +{ + struct max77759_gpio_chip *chip; + int irq; + struct gpio_irq_chip *girq; + int ret; + unsigned long irq_flags; + struct irq_data *irqd; + + chip =3D devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->map =3D dev_get_regmap(pdev->dev.parent, "maxq"); + if (!chip->map) + return dev_err_probe(&pdev->dev, -ENODEV, "Missing regmap\n"); + + irq =3D platform_get_irq_byname(pdev, "GPI"); + if (irq < 0) + return dev_err_probe(&pdev->dev, irq, "Failed to get IRQ\n"); + + chip->max77759 =3D dev_get_drvdata(pdev->dev.parent); + ret =3D devm_mutex_init(&pdev->dev, &chip->maxq_lock); + if (ret) + return ret; + ret =3D devm_mutex_init(&pdev->dev, &chip->irq_lock); + if (ret) + return ret; + + chip->gc.base =3D -1; + chip->gc.label =3D dev_name(&pdev->dev); + chip->gc.parent =3D &pdev->dev; + chip->gc.can_sleep =3D true; + + chip->gc.names =3D max77759_gpio_line_names; + chip->gc.ngpio =3D MAX77759_N_GPIOS; + chip->gc.get_direction =3D max77759_gpio_get_direction; + chip->gc.direction_input =3D max77759_gpio_direction_input; + chip->gc.direction_output =3D max77759_gpio_direction_output; + chip->gc.get =3D max77759_gpio_get_value; + chip->gc.set_rv =3D max77759_gpio_set_value; + + girq =3D &chip->gc.irq; + gpio_irq_chip_set_chip(girq, &max77759_gpio_irq_chip); + /* This will let us handle the parent IRQ in the driver */ + girq->parent_handler =3D NULL; + girq->num_parents =3D 0; + girq->parents =3D NULL; + girq->default_type =3D IRQ_TYPE_NONE; + girq->handler =3D handle_simple_irq; + girq->threaded =3D true; + + ret =3D devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to add GPIO chip\n"); + + irq_flags =3D IRQF_ONESHOT | IRQF_SHARED; + irqd =3D irq_get_irq_data(irq); + if (irqd) + irq_flags |=3D irqd_get_trigger_type(irqd); + + ret =3D devm_request_threaded_irq(&pdev->dev, irq, NULL, + max77759_gpio_irqhandler, irq_flags, + dev_name(&pdev->dev), chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to request IRQ\n"); + + return ret; +} + +static const struct of_device_id max77759_gpio_of_id[] =3D { + { .compatible =3D "maxim,max77759-gpio", }, + { } +}; +MODULE_DEVICE_TABLE(of, max77759_gpio_of_id); + +static const struct platform_device_id max77759_gpio_platform_id[] =3D { + { "max77759-gpio", }, + { } +}; +MODULE_DEVICE_TABLE(platform, max77759_gpio_platform_id); + +static struct platform_driver max77759_gpio_driver =3D { + .driver =3D { + .name =3D "max77759-gpio", + .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, + .of_match_table =3D max77759_gpio_of_id, + }, + .probe =3D max77759_gpio_probe, + .id_table =3D max77759_gpio_platform_id, +}; + +module_platform_driver(max77759_gpio_driver); + +MODULE_AUTHOR("Andr=C3=A9 Draszik "); +MODULE_DESCRIPTION("GPIO driver for Maxim MAX77759"); +MODULE_LICENSE("GPL"); --=20 2.49.0.901.g37484f566f-goog From nobody Tue Feb 10 00:44:18 2026 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83A2D220685 for ; Wed, 30 Apr 2025 09:03:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003801; cv=none; b=YNGSBj2mdGr3AlGo1YEDOLEfxW+2JtNngUiP7/1somLjzLIEfeOK1k0aUg/Q8DrHtqGczFkXzo9h4C9ekO0L1F7Co3RqcMPu5WWuuKd4FDZxwzboQsZ0jskBrirh03dJ/hKww6l6R9d/fEp5BJ1cqiHAXQjZkuJXGx8mSREGFAQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746003801; c=relaxed/simple; bh=o1Qsb3HDQ0y1fMYD5Z0n6QAiTpx3nP8QGVFUewn/r80=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lOAZYFkRuyO3IywIC3Jj0xVEC35c2rnf8DRT20Ubwu95gChkbIxZvYPflB0oaGvDA5wmf6d1ach3CUE6Cj4CN4PZUeUnzA6HUPFYphCZFZwZw5RTWqD83wlFxRhAb6nNbLbHVXMEgKuarT9albcRXsWWsMjVELM0mY8sWbwnD8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=RUgdbKRN; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RUgdbKRN" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-ac2ab99e16eso1526822166b.0 for ; Wed, 30 Apr 2025 02:03:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746003796; x=1746608596; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7zdeylOylYk/fCkkbzL6TPhsYQZ5wrS4PeyDnGbCM1E=; b=RUgdbKRNqBWrN6+AIZYfWxJ8P4HnZmG8AA44PicMbv8BNVyhxFWHWv4mns+mYK3Vt3 xxAL/TVwb4DxiPElle9ywDk5eQj/Ajmf2u75KnqBF6iocKoxk3YTNt4UO8wI7Qjh+SRL bv3904SsYOTtkXBUUbHHHNY2FZR0WeYbG/aiZwCIy9Sh0SDqJ1h8aJFuY/FYb4ak+BBU 4QsLwwupWiW7/7iXVwl6Wevx1GsfwHSItjMq+02KJuSVVUUeUKDX+kg6qmMs4206wBWX S6CMBdDV3f0b8IjCZtxKNebaIa698jsw4yYaXcIjD1fUDJeGxgsVaOsd9HOdY6EOotWP SotA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746003796; x=1746608596; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7zdeylOylYk/fCkkbzL6TPhsYQZ5wrS4PeyDnGbCM1E=; b=bYul3fRZn8UjCWbvxJlNha74WuBnLypsHG5LA61rVm4/MC4xqXKwBG1wMCRMLKcDBu LTn9Xun1i2ssEZfnbhatFGS3ndoC0VIyKKc8SyYUhRfHAuQK1kpF9NQDbcZe7DguVWJe wRQ3gNiNd0w40sR9/MIsIcm5VslYBwcJcE37cq0L2YpNjBM4wd9uOpKxIOwo5k09/yYS mdyS/B2mP67l3H5adFo3jszYkKI/048lP9hAEEgyGNRxxr64aupzzbvHc3LA6UG2e5eB apLO/FG6dRj14TdnmHxy6Ggvg74xN18ZrrpZKybEjTDJrJx23YtOaC3nvSkbG5+Q/Mn7 6w6g== X-Forwarded-Encrypted: i=1; AJvYcCX/tUiUVdD+qEYLRl7m+w2Awb6LLJF/y7sfKT3VqciSW3m6trZenYTb7XOFzcjTpt/vXvGsuRuF8Io/YrE=@vger.kernel.org X-Gm-Message-State: AOJu0YwjUGAdWfVNHEt8RvsKhR0oZZ4ii/6U+SD4sy9mpwHUlzAd4W3e Rde17YCzpDQv5rPEjQtlma7/P9fRTuMMdqkHFOW92Xe3TTtMkZDf4CA4ruAZtGg= X-Gm-Gg: ASbGnctvNb3v/4QNacfP04RyH1+HTeSSN9cO2O0XbO9OYIbvWcZd19AQoCRfzqyB+Eo Oo8OPA+ihKI2E/EYsfbEf8pT+fj2aQch3mor8sHSMNABIHFmY7kLLYiJR/XPSesaHPJWyGPaYNx ssitvHqFAOuWHzYCvDPWHNnF3ejkG+/aMwyUmxnvS264fLpoHoXu4LyUEJs7Nhx7a7VTmjxG6BG LsjqFXM4oD7tiRimR+0g4+uM80LXNCj/5bR+s1Q4zrSqmyPRLCuQwGqBOBs7HUowuTSqPGVo6v2 YJzr9b5OT4jTcJEIV0SpZ3101SiyFhCqXuDn/QFGEGSrKdjcNM7IRdRpVeaoSQbTjjzFPjRwFqz Poky+cTOgkerQDq6IsmEtRUqd X-Google-Smtp-Source: AGHT+IGRuZJzgfE7wlsVQE+YnNAFAyvNW5Es5waeCyPJcJDIWE808tuoEyrNnMHOCdChveQaY2Wd9A== X-Received: by 2002:a17:907:7f17:b0:ace:d957:d6d8 with SMTP id a640c23a62f3a-acedc66a629mr224380466b.34.1746003795647; Wed, 30 Apr 2025 02:03:15 -0700 (PDT) Received: from puffmais.c.googlers.com (8.239.204.35.bc.googleusercontent.com. [35.204.239.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6e41bbb6sm889676766b.28.2025.04.30.02.03.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 02:03:15 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 30 Apr 2025 10:03:13 +0100 Subject: [PATCH v9 6/6] nvmem: max77759: add Maxim MAX77759 NVMEM driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-max77759-mfd-v9-6-639763e23598@linaro.org> References: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> In-Reply-To: <20250430-max77759-mfd-v9-0-639763e23598@linaro.org> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Srinivas Kandagatla , Kees Cook , "Gustavo A. R. Silva" Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-hardening@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The Maxim MAX77759 is a companion PMIC for USB Type-C applications and includes Battery Charger, Fuel Gauge, temperature sensors, USB Type-C Port Controller (TCPC), NVMEM, and a GPIO expander. This driver exposes the non volatile memory using the platform device registered by the core MFD driver. Signed-off-by: Andr=C3=A9 Draszik Acked-by: Srinivas Kandagatla --- v9: * drop superfluous max77759_nvmem_is_valid() (Srini) v8: * replace MODULE_ALIAS() with .id_table (Krzysztof) * drop previous tags v5: * follow API updates of max77759 core driver v2: * align sentinel in max77759_nvmem_of_id[] with other max77759 drivers (Christophe) --- MAINTAINERS | 1 + drivers/nvmem/Kconfig | 12 ++++ drivers/nvmem/Makefile | 2 + drivers/nvmem/max77759-nvmem.c | 145 +++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 160 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0db5e1fe64930e85265913e6a7dd2669c645cf42..b821502afc48f95d48fb8c6ac69= 41d1dd8e63582 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14670,6 +14670,7 @@ S: Maintained F: Documentation/devicetree/bindings/*/maxim,max77759*.yaml F: drivers/gpio/gpio-max77759.c F: drivers/mfd/max77759.c +F: drivers/nvmem/max77759-nvmem.c F: include/linux/mfd/max77759.h =20 MAXIM MAX77802 PMIC REGULATOR DEVICE DRIVER diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 8671b7c974b933e147154bb40b5d41b5730518d2..3de07ef524906ad24a89e58abdf= e93529a83c80f 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -154,6 +154,18 @@ config NVMEM_LPC18XX_OTP To compile this driver as a module, choose M here: the module will be called nvmem_lpc18xx_otp. =20 +config NVMEM_MAX77759 + tristate "Maxim Integrated MAX77759 NVMEM Support" + depends on MFD_MAX77759 + default MFD_MAX77759 + help + Say Y here to include support for the user-accessible storage found + in Maxim Integrated MAX77759 PMICs. This IC provides space for 30 + bytes of storage. + + This driver can also be built as a module. If so, the module + will be called nvmem-max77759. + config NVMEM_MESON_EFUSE tristate "Amlogic Meson GX eFuse Support" depends on (ARCH_MESON || COMPILE_TEST) && MESON_SM diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 5b77bbb6488bf89bfb305750a1cbf4a6731a0a58..a9d03cfbbd27e68d40f8c330e72= e20378b12a481 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -34,6 +34,8 @@ obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) +=3D nvmem_lpc18xx_eep= rom.o nvmem_lpc18xx_eeprom-y :=3D lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) +=3D nvmem_lpc18xx_otp.o nvmem_lpc18xx_otp-y :=3D lpc18xx_otp.o +obj-$(CONFIG_NVMEM_MAX77759) +=3D nvmem-max77759.o +nvmem-max77759-y :=3D max77759-nvmem.o obj-$(CONFIG_NVMEM_MESON_EFUSE) +=3D nvmem_meson_efuse.o nvmem_meson_efuse-y :=3D meson-efuse.o obj-$(CONFIG_NVMEM_MESON_MX_EFUSE) +=3D nvmem_meson_mx_efuse.o diff --git a/drivers/nvmem/max77759-nvmem.c b/drivers/nvmem/max77759-nvmem.c new file mode 100644 index 0000000000000000000000000000000000000000..c9961ad0e232e152e924b5b06d7= d93172760ac3a --- /dev/null +++ b/drivers/nvmem/max77759-nvmem.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright 2020 Google Inc +// Copyright 2025 Linaro Ltd. +// +// NVMEM driver for Maxim MAX77759 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX77759_NVMEM_OPCODE_HEADER_LEN 3 +/* + * NVMEM commands have a three byte header (which becomes part of the comm= and), + * so we need to subtract that. + */ +#define MAX77759_NVMEM_SIZE (MAX77759_MAXQ_OPCODE_MAXLENGTH \ + - MAX77759_NVMEM_OPCODE_HEADER_LEN) + +struct max77759_nvmem { + struct device *dev; + struct max77759 *max77759; +}; + +static int max77759_nvmem_reg_read(void *priv, unsigned int offset, + void *val, size_t bytes) +{ + struct max77759_nvmem *nvmem =3D priv; + DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, + MAX77759_NVMEM_OPCODE_HEADER_LEN); + DEFINE_FLEX(struct max77759_maxq_response, rsp, rsp, length, + MAX77759_MAXQ_OPCODE_MAXLENGTH); + int ret; + + cmd->cmd[0] =3D MAX77759_MAXQ_OPCODE_USER_SPACE_READ; + cmd->cmd[1] =3D offset; + cmd->cmd[2] =3D bytes; + rsp->length =3D bytes + MAX77759_NVMEM_OPCODE_HEADER_LEN; + + ret =3D max77759_maxq_command(nvmem->max77759, cmd, rsp); + if (ret < 0) + return ret; + + if (memcmp(cmd->cmd, rsp->rsp, MAX77759_NVMEM_OPCODE_HEADER_LEN)) { + dev_warn(nvmem->dev, "protocol error (read)\n"); + return -EIO; + } + + memcpy(val, &rsp->rsp[MAX77759_NVMEM_OPCODE_HEADER_LEN], bytes); + + return 0; +} + +static int max77759_nvmem_reg_write(void *priv, unsigned int offset, + void *val, size_t bytes) +{ + struct max77759_nvmem *nvmem =3D priv; + DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, + MAX77759_MAXQ_OPCODE_MAXLENGTH); + DEFINE_FLEX(struct max77759_maxq_response, rsp, rsp, length, + MAX77759_MAXQ_OPCODE_MAXLENGTH); + int ret; + + cmd->cmd[0] =3D MAX77759_MAXQ_OPCODE_USER_SPACE_WRITE; + cmd->cmd[1] =3D offset; + cmd->cmd[2] =3D bytes; + memcpy(&cmd->cmd[MAX77759_NVMEM_OPCODE_HEADER_LEN], val, bytes); + cmd->length =3D bytes + MAX77759_NVMEM_OPCODE_HEADER_LEN; + rsp->length =3D cmd->length; + + ret =3D max77759_maxq_command(nvmem->max77759, cmd, rsp); + if (ret < 0) + return ret; + + if (memcmp(cmd->cmd, rsp->rsp, cmd->length)) { + dev_warn(nvmem->dev, "protocol error (write)\n"); + return -EIO; + } + + return 0; +} + +static int max77759_nvmem_probe(struct platform_device *pdev) +{ + struct nvmem_config config =3D { + .dev =3D &pdev->dev, + .name =3D dev_name(&pdev->dev), + .id =3D NVMEM_DEVID_NONE, + .type =3D NVMEM_TYPE_EEPROM, + .ignore_wp =3D true, + .size =3D MAX77759_NVMEM_SIZE, + .word_size =3D sizeof(u8), + .stride =3D sizeof(u8), + .reg_read =3D max77759_nvmem_reg_read, + .reg_write =3D max77759_nvmem_reg_write, + }; + struct max77759_nvmem *nvmem; + + nvmem =3D devm_kzalloc(&pdev->dev, sizeof(*nvmem), GFP_KERNEL); + if (!nvmem) + return -ENOMEM; + + nvmem->dev =3D &pdev->dev; + nvmem->max77759 =3D dev_get_drvdata(pdev->dev.parent); + + config.priv =3D nvmem; + + return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); +} + +static const struct of_device_id max77759_nvmem_of_id[] =3D { + { .compatible =3D "maxim,max77759-nvmem", }, + { } +}; +MODULE_DEVICE_TABLE(of, max77759_nvmem_of_id); + +static const struct platform_device_id max77759_nvmem_platform_id[] =3D { + { "max77759-nvmem", }, + { } +}; +MODULE_DEVICE_TABLE(platform, max77759_nvmem_platform_id); + +static struct platform_driver max77759_nvmem_driver =3D { + .driver =3D { + .name =3D "max77759-nvmem", + .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, + .of_match_table =3D max77759_nvmem_of_id, + }, + .probe =3D max77759_nvmem_probe, + .id_table =3D max77759_nvmem_platform_id, +}; + +module_platform_driver(max77759_nvmem_driver); + +MODULE_AUTHOR("Andr=C3=A9 Draszik "); +MODULE_DESCRIPTION("NVMEM driver for Maxim MAX77759"); +MODULE_LICENSE("GPL"); --=20 2.49.0.901.g37484f566f-goog