From nobody Thu Dec 18 02:26:45 2025 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCBC320F060 for ; Wed, 30 Apr 2025 08:16:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746000997; cv=none; b=q/A36BK+/fjNcmq+UKzHw7yFYmkBiMriuWS5n2wGfc4JZSBvciz1qXkJuc8JNS/BOzhisCVEooOp3hugsUPNySZe1331CNq0f3uebwEUJoxMUnKtFX5+no9UXnrZoPg0oY+/gbzT9l8NuYvWqxRvDZiFxXVzbqulGJ6a5/C60Ww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746000997; c=relaxed/simple; bh=vxtT9/3d3+RsfsN/8F9NhokA4ex2hx300P/B78SmG8M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hUEl/GjKn50k21nKX0/hZ5/Fp9IaSrHOOsLNrbFvWN74W8sa9QuNUC4MWUg61i2vcG3DAbuWibVIKeqtuPNBXmOymjIRblZjkr+1lrHOi07Hvp4pBzBXlJmp7oFHbcT+kIiCseiaCrgPGaz1jfLAaNqi+NZfkbmWA4AB/gMR1xw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=ZQoUu/bJ; arc=none smtp.client-ip=209.85.210.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="ZQoUu/bJ" Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-7396f13b750so7715502b3a.1 for ; Wed, 30 Apr 2025 01:16:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1746000995; x=1746605795; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GMR7LQ4EcuISRMn9uVkeFVkgbpXUkyH5s1ul4wVziJk=; b=ZQoUu/bJHr6YglVeveIm6EMM6K3sCqbuMpcdHjg6HqMhFdKoVi/7VRnP3LRlazBrLF lJWf5pc/3z820r0t1Nx04bKdhkPySBXo6M+A/BOxsMRQ1A3nrQ+RIAhLC8ISy7UT7SKD LR3d1AP8uvU3698aNDb9/2Y6Em8XjwCB/blEVHuKqdthF3arhqmhMtQTRVTOCDrFLz0y HiyziCR+NGNQL+EhRH+qIKnGgV03Sq9gFtgl1M/nnXsqAosWLxL/pfgPK0up3pa1oFve boFIElu6zBM32vwccaUNcajD4Ur1AfBFz0eTLWwY7yGxn23U+LBcXdCCP2VdTgLMHXd+ ZGfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746000995; x=1746605795; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GMR7LQ4EcuISRMn9uVkeFVkgbpXUkyH5s1ul4wVziJk=; b=vyT6Iwscm4qaVQSx2GDvUj4egEmO7VPs4B8DbwJgpJ7ie5zqBQ8BlmKz2TI91r9vw3 no9OD1X9pGxHx2jSMy/G5A7ywfpcAFQCu9mnHIbbB61p5GZSIMO+/7sh+HYRpo8DOhQB Mx2ujpoew95AAl/iToYTJrLCaVY/ZUS3fUeibi1m21ohf3nGa15+MnQzcpCAd3ZAwefd 4Z/or9ufuDlPg17iixXE1z0pJdkFf3xM7tkZWy0+gDwXA6f5M2EkgFDrPA4aiZz6+0Wf 508krIVBXsO/ekVBRQBz5RglzqQ6axtotE7oKjePLEL6qGmnH0E/xXzYqHcTMZ96fvP6 w/tg== X-Forwarded-Encrypted: i=1; AJvYcCWDuVzQ5bodN1Fb+/ytXjR46GOYYuvxGgU8SA+xihYH3A5LmNDM3xwxMBzJMg84GPTTO9baIjh2omqL4U8=@vger.kernel.org X-Gm-Message-State: AOJu0Yxx0BQgVFwZlmUGG+XaUdL4bDBqU7J3x8OUi5EeKf8A6kXXQPcM BwtR42aEokebM86Ji8z4aLekauVj9EMxCJBO6zZj/Ti+GRlnEoFXzLIJRrRXkDo= X-Gm-Gg: ASbGnctCsm54szrBwOR410DEXseZRmvBZsekzF+r80ntsdnGfQ8VZjXDUHlCMrbbA87 tjKldER6t/lUdhI327rKJxOb8ud4YrO1CWxXn6+lgIgSoqBqdjM4QfTWjjKKirnD/3hBVKqIhOv U2fNzWnPitRk+qR9a6Z312OEHkVv3cb+MeTrRfceNYJfdpTFkJdU3FqKu+1Pcbcubiz7gaCjviv fUg8BJv4El8KfQ63rzwZvOkexY4WPWKy+JoMic1q8wCmbhGuucumwZ8ZGXFc4yJW+5WI4lLprs4 4r5IPCtW4rvhhcU9oaTxnVRdKU08zg707gXniG/Nu1i3YTeCVP14yg== X-Google-Smtp-Source: AGHT+IEszTsV/BUeZBkL4ZpuZ0SkL3h2U9eOwaQLGRPB51BWwKG2aiOQfovURMFi8gr43T+5AaK3Cg== X-Received: by 2002:a05:6a00:139b:b0:736:bfc4:ef2c with SMTP id d2e1a72fcca58-74038793f8dmr3272406b3a.0.1746000995136; Wed, 30 Apr 2025 01:16:35 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74039a309edsm1073084b3a.91.2025.04.30.01.16.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 01:16:34 -0700 (PDT) From: Atish Patra Date: Wed, 30 Apr 2025 01:16:28 -0700 Subject: [PATCH v3 1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-kvm_selftest_improve-v3-1-eea270ff080b@rivosinc.com> References: <20250430-kvm_selftest_improve-v3-0-eea270ff080b@rivosinc.com> In-Reply-To: <20250430-kvm_selftest_improve-v3-0-eea270ff080b@rivosinc.com> To: Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Andrew Jones Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-42535 The current exeception register structure in selftests are missing few registers (e.g stval). Instead of adding it manually, change the ex_regs to align with pt_regs to make it future proof. Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- .../selftests/kvm/include/riscv/processor.h | 10 +- tools/testing/selftests/kvm/lib/riscv/handlers.S | 139 +++++++++++------= ---- tools/testing/selftests/kvm/lib/riscv/processor.c | 2 +- tools/testing/selftests/kvm/riscv/arch_timer.c | 2 +- tools/testing/selftests/kvm/riscv/ebreak_test.c | 2 +- tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 4 +- 6 files changed, 83 insertions(+), 76 deletions(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index 5f389166338c..1b5aef87de0f 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -60,7 +60,8 @@ static inline bool __vcpu_has_sbi_ext(struct kvm_vcpu *vc= pu, uint64_t sbi_ext) return __vcpu_has_ext(vcpu, RISCV_SBI_EXT_REG(sbi_ext)); } =20 -struct ex_regs { +struct pt_regs { + unsigned long epc; unsigned long ra; unsigned long sp; unsigned long gp; @@ -92,16 +93,19 @@ struct ex_regs { unsigned long t4; unsigned long t5; unsigned long t6; - unsigned long epc; + /* Supervisor/Machine CSRs */ unsigned long status; + unsigned long badaddr; unsigned long cause; + /* a0 value before the syscall */ + unsigned long orig_a0; }; =20 #define NR_VECTORS 2 #define NR_EXCEPTIONS 32 #define EC_MASK (NR_EXCEPTIONS - 1) =20 -typedef void(*exception_handler_fn)(struct ex_regs *); +typedef void(*exception_handler_fn)(struct pt_regs *); =20 void vm_init_vector_tables(struct kvm_vm *vm); void vcpu_init_vector_tables(struct kvm_vcpu *vcpu); diff --git a/tools/testing/selftests/kvm/lib/riscv/handlers.S b/tools/testi= ng/selftests/kvm/lib/riscv/handlers.S index aa0abd3f35bb..b787b982e922 100644 --- a/tools/testing/selftests/kvm/lib/riscv/handlers.S +++ b/tools/testing/selftests/kvm/lib/riscv/handlers.S @@ -10,85 +10,88 @@ #include =20 .macro save_context - addi sp, sp, (-8*34) - sd x1, 0(sp) - sd x2, 8(sp) - sd x3, 16(sp) - sd x4, 24(sp) - sd x5, 32(sp) - sd x6, 40(sp) - sd x7, 48(sp) - sd x8, 56(sp) - sd x9, 64(sp) - sd x10, 72(sp) - sd x11, 80(sp) - sd x12, 88(sp) - sd x13, 96(sp) - sd x14, 104(sp) - sd x15, 112(sp) - sd x16, 120(sp) - sd x17, 128(sp) - sd x18, 136(sp) - sd x19, 144(sp) - sd x20, 152(sp) - sd x21, 160(sp) - sd x22, 168(sp) - sd x23, 176(sp) - sd x24, 184(sp) - sd x25, 192(sp) - sd x26, 200(sp) - sd x27, 208(sp) - sd x28, 216(sp) - sd x29, 224(sp) - sd x30, 232(sp) - sd x31, 240(sp) + addi sp, sp, (-8*36) + sd x1, 8(sp) + sd x2, 16(sp) + sd x3, 24(sp) + sd x4, 32(sp) + sd x5, 40(sp) + sd x6, 48(sp) + sd x7, 56(sp) + sd x8, 64(sp) + sd x9, 72(sp) + sd x10, 80(sp) + sd x11, 88(sp) + sd x12, 96(sp) + sd x13, 104(sp) + sd x14, 112(sp) + sd x15, 120(sp) + sd x16, 128(sp) + sd x17, 136(sp) + sd x18, 144(sp) + sd x19, 152(sp) + sd x20, 160(sp) + sd x21, 168(sp) + sd x22, 176(sp) + sd x23, 184(sp) + sd x24, 192(sp) + sd x25, 200(sp) + sd x26, 208(sp) + sd x27, 216(sp) + sd x28, 224(sp) + sd x29, 232(sp) + sd x30, 240(sp) + sd x31, 248(sp) csrr s0, CSR_SEPC csrr s1, CSR_SSTATUS - csrr s2, CSR_SCAUSE - sd s0, 248(sp) + csrr s2, CSR_STVAL + csrr s3, CSR_SCAUSE + sd s0, 0(sp) sd s1, 256(sp) sd s2, 264(sp) + sd s3, 272(sp) .endm =20 .macro restore_context + ld s3, 272(sp) ld s2, 264(sp) ld s1, 256(sp) - ld s0, 248(sp) - csrw CSR_SCAUSE, s2 + ld s0, 0(sp) + csrw CSR_SCAUSE, s3 csrw CSR_SSTATUS, s1 csrw CSR_SEPC, s0 - ld x31, 240(sp) - ld x30, 232(sp) - ld x29, 224(sp) - ld x28, 216(sp) - ld x27, 208(sp) - ld x26, 200(sp) - ld x25, 192(sp) - ld x24, 184(sp) - ld x23, 176(sp) - ld x22, 168(sp) - ld x21, 160(sp) - ld x20, 152(sp) - ld x19, 144(sp) - ld x18, 136(sp) - ld x17, 128(sp) - ld x16, 120(sp) - ld x15, 112(sp) - ld x14, 104(sp) - ld x13, 96(sp) - ld x12, 88(sp) - ld x11, 80(sp) - ld x10, 72(sp) - ld x9, 64(sp) - ld x8, 56(sp) - ld x7, 48(sp) - ld x6, 40(sp) - ld x5, 32(sp) - ld x4, 24(sp) - ld x3, 16(sp) - ld x2, 8(sp) - ld x1, 0(sp) - addi sp, sp, (8*34) + ld x31, 248(sp) + ld x30, 240(sp) + ld x29, 232(sp) + ld x28, 224(sp) + ld x27, 216(sp) + ld x26, 208(sp) + ld x25, 200(sp) + ld x24, 192(sp) + ld x23, 184(sp) + ld x22, 176(sp) + ld x21, 168(sp) + ld x20, 160(sp) + ld x19, 152(sp) + ld x18, 144(sp) + ld x17, 136(sp) + ld x16, 128(sp) + ld x15, 120(sp) + ld x14, 112(sp) + ld x13, 104(sp) + ld x12, 96(sp) + ld x11, 88(sp) + ld x10, 80(sp) + ld x9, 72(sp) + ld x8, 64(sp) + ld x7, 56(sp) + ld x6, 48(sp) + ld x5, 40(sp) + ld x4, 32(sp) + ld x3, 24(sp) + ld x2, 16(sp) + ld x1, 8(sp) + addi sp, sp, (8*36) .endm =20 .balign 4 diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/test= ing/selftests/kvm/lib/riscv/processor.c index dd663bcf0cc0..2eac7d4b59e9 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -402,7 +402,7 @@ struct handlers { exception_handler_fn exception_handlers[NR_VECTORS][NR_EXCEPTIONS]; }; =20 -void route_exception(struct ex_regs *regs) +void route_exception(struct pt_regs *regs) { struct handlers *handlers =3D (struct handlers *)exception_handlers; int vector =3D 0, ec; diff --git a/tools/testing/selftests/kvm/riscv/arch_timer.c b/tools/testing= /selftests/kvm/riscv/arch_timer.c index 9e370800a6a2..f962fefc48fa 100644 --- a/tools/testing/selftests/kvm/riscv/arch_timer.c +++ b/tools/testing/selftests/kvm/riscv/arch_timer.c @@ -15,7 +15,7 @@ =20 static int timer_irq =3D IRQ_S_TIMER; =20 -static void guest_irq_handler(struct ex_regs *regs) +static void guest_irq_handler(struct pt_regs *regs) { uint64_t xcnt, xcnt_diff_us, cmp; unsigned int intid =3D regs->cause & ~CAUSE_IRQ_FLAG; diff --git a/tools/testing/selftests/kvm/riscv/ebreak_test.c b/tools/testin= g/selftests/kvm/riscv/ebreak_test.c index cfed6c727bfc..739d17befb5a 100644 --- a/tools/testing/selftests/kvm/riscv/ebreak_test.c +++ b/tools/testing/selftests/kvm/riscv/ebreak_test.c @@ -27,7 +27,7 @@ static void guest_code(void) GUEST_DONE(); } =20 -static void guest_breakpoint_handler(struct ex_regs *regs) +static void guest_breakpoint_handler(struct pt_regs *regs) { WRITE_ONCE(sw_bp_addr, regs->epc); regs->epc +=3D 4; diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testi= ng/selftests/kvm/riscv/sbi_pmu_test.c index 03406de4989d..6e66833e5941 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -128,7 +128,7 @@ static void stop_counter(unsigned long counter, unsigne= d long stop_flags) "Unable to stop counter %ld error %ld\n", counter, ret.error); } =20 -static void guest_illegal_exception_handler(struct ex_regs *regs) +static void guest_illegal_exception_handler(struct pt_regs *regs) { __GUEST_ASSERT(regs->cause =3D=3D EXC_INST_ILLEGAL, "Unexpected exception handler %lx\n", regs->cause); @@ -138,7 +138,7 @@ static void guest_illegal_exception_handler(struct ex_r= egs *regs) regs->epc +=3D 4; } =20 -static void guest_irq_handler(struct ex_regs *regs) +static void guest_irq_handler(struct pt_regs *regs) { unsigned int irq_num =3D regs->cause & ~CAUSE_IRQ_FLAG; struct riscv_pmu_snapshot_data *snapshot_data =3D snapshot_gva; --=20 2.43.0