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Wed, 30 Apr 2025 06:01:19 -0700 (PDT) From: Krzysztof Kozlowski Date: Wed, 30 Apr 2025 15:00:36 +0200 Subject: [PATCH v5 06/24] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-b4-sm8750-display-v5-6-8cab30c3e4df@linaro.org> References: <20250430-b4-sm8750-display-v5-0-8cab30c3e4df@linaro.org> In-Reply-To: <20250430-b4-sm8750-display-v5-0-8cab30c3e4df@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Rob Clark , Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Rob Clark , linux-clk@vger.kernel.org, Srinivas Kandagatla X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B On SM8750 the setting rate of pixel and byte clocks, while the parent DSI PHY PLL, fails with: disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration. DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in CMN_CTRL_0 asserted. Mark these clocks with CLK_OPS_PARENT_ENABLE to ensure the parent is enabled during rate changes. Signed-off-by: Krzysztof Kozlowski --- Patch is independent and can go via separate tree. Including here for complete picture of clock debugging issues. Changes in v5: 1. New patch --- drivers/clk/qcom/dispcc-sm8750.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8= 750.c index 877b40d50e6ff5501df16edcffb6cf3322c65977..d86f3def6dd06b6f6f7a25018a8= 56dcc86fc48eb 100644 --- a/drivers/clk/qcom/dispcc-sm8750.c +++ b/drivers/clk/qcom/dispcc-sm8750.c @@ -393,7 +393,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src =3D { .name =3D "disp_cc_mdss_byte0_clk_src", .parent_data =3D disp_cc_parent_data_1, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), - .flags =3D CLK_SET_RATE_PARENT, + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops =3D &clk_byte2_ops, }, }; @@ -712,7 +712,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { .name =3D "disp_cc_mdss_pclk0_clk_src", .parent_data =3D disp_cc_parent_data_1, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), - .flags =3D CLK_SET_RATE_PARENT, + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops =3D &clk_pixel_ops, }, }; --=20 2.45.2