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Wed, 30 Apr 2025 06:01:51 -0700 (PDT) From: Krzysztof Kozlowski Date: Wed, 30 Apr 2025 15:00:50 +0200 Subject: [PATCH v5 20/24] drm/msm/dpu: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250430-b4-sm8750-display-v5-20-8cab30c3e4df@linaro.org> References: <20250430-b4-sm8750-display-v5-0-8cab30c3e4df@linaro.org> In-Reply-To: <20250430-b4-sm8750-display-v5-0-8cab30c3e4df@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Rob Clark , Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Rob Clark , linux-clk@vger.kernel.org, Srinivas Kandagatla , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DPU version v12.0 support for the Qualcomm SM8750 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v2: 1. Add CDM --- .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 496 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 29 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 527 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h new file mode 100644 index 0000000000000000000000000000000000000000..1f883b9f8b8b29e3a8c2fe254b7= 8594a413dc2a1 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h @@ -0,0 +1,496 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Linaro Limited + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_12_0_SM8750_H +#define _DPU_12_0_SM8750_H + +static const struct dpu_caps sm8750_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 8192, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg sm8750_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +static const struct dpu_ctl_cfg sm8750_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x1000, + .has_split_display =3D 1, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x1000, + .has_split_display =3D 1, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm8750_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x6000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x8000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0xa000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_12", .id =3D SSPP_DMA4, + .base =3D 0x2c000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 14, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_13", .id =3D SSPP_DMA5, + .base =3D 0x2e000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 15, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg sm8750_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x48000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x49000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, { + .name =3D "lm_6", .id =3D LM_6, + .base =3D 0x4a000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_7, + .pingpong =3D PINGPONG_6, + }, { + .name =3D "lm_7", .id =3D LM_7, + .base =3D 0x4b000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_6, + .pingpong =3D PINGPONG_7, + }, +}; + +static const struct dpu_dspp_cfg sm8750_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x56000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x58000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x5a000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg sm8750_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x69000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x6a000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x6b000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x6d000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x6e000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x6f000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20), + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x70000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x66000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, + .base =3D 0x66400, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_2", .id =3D PINGPONG_CWB_2, + .base =3D 0x7e000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, { + .name =3D "pingpong_cwb_3", .id =3D PINGPONG_CWB_3, + .base =3D 0x7e400, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, +}; + +static const struct dpu_merge_3d_cfg sm8750_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x4e000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x4f000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x50000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x51000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_4", .id =3D MERGE_3D_4, + .base =3D 0x66700, .len =3D 0x1c, + }, { + .name =3D "merge_3d_5", .id =3D MERGE_3D_5, + .base =3D 0x7e700, .len =3D 0x1c, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg sm8750_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x80000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x81000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x81000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_2_0", .id =3D DSC_4, + .base =3D 0x82000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_2_1", .id =3D DSC_5, + .base =3D 0x82000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_3_0", .id =3D DSC_6, + .base =3D 0x83000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_3_1", .id =3D DSC_7, + .base =3D 0x83000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg sm8750_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x65000, .len =3D 0x2c8, + .features =3D WB_SDM845_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_cwb_cfg sm8750_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x66200, .len =3D 0x20, + }, + { + .name =3D "cwb_1", .id =3D CWB_1, + .base =3D 0x66600, .len =3D 0x20, + }, + { + .name =3D "cwb_2", .id =3D CWB_2, + .base =3D 0x7e200, .len =3D 0x20, + }, + { + .name =3D "cwb_3", .id =3D CWB_3, + .base =3D 0x7e600, .len =3D 0x20, + }, +}; + +static const struct dpu_intf_cfg sm8750_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x34000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x35000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x36000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x37000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg sm8750_perf_data =3D { + .max_bw_low =3D 18900000, + .max_bw_high =3D 28500000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version sm8750_mdss_ver =3D { + .core_major_ver =3D 12, + .core_minor_ver =3D 0, +}; + +const struct dpu_mdss_cfg dpu_sm8750_cfg =3D { + .mdss_ver =3D &sm8750_mdss_ver, + .caps =3D &sm8750_dpu_caps, + .mdp =3D &sm8750_mdp, + .cdm =3D &dpu_cdm_5_x, + .ctl_count =3D ARRAY_SIZE(sm8750_ctl), + .ctl =3D sm8750_ctl, + .sspp_count =3D ARRAY_SIZE(sm8750_sspp), + .sspp =3D sm8750_sspp, + .mixer_count =3D ARRAY_SIZE(sm8750_lm), + .mixer =3D sm8750_lm, + .dspp_count =3D ARRAY_SIZE(sm8750_dspp), + .dspp =3D sm8750_dspp, + .pingpong_count =3D ARRAY_SIZE(sm8750_pp), + .pingpong =3D sm8750_pp, + .dsc_count =3D ARRAY_SIZE(sm8750_dsc), + .dsc =3D sm8750_dsc, + .merge_3d_count =3D ARRAY_SIZE(sm8750_merge_3d), + .merge_3d =3D sm8750_merge_3d, + .wb_count =3D ARRAY_SIZE(sm8750_wb), + .wb =3D sm8750_wb, + .cwb_count =3D ARRAY_SIZE(sm8750_cwb), + .cwb =3D sm8650_cwb, + .intf_count =3D ARRAY_SIZE(sm8750_intf), + .intf =3D sm8750_intf, + .vbif_count =3D ARRAY_SIZE(sm8650_vbif), + .vbif =3D sm8650_vbif, + .perf =3D &sm8750_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index a310a5234e99ea4886e82ac2100c4099e6a1841e..1ccef3cdc5227ab785bd805b44c= ec132b2881e46 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -323,6 +323,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qsee= d3_3_2 =3D static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =3D _VIG_SBLK(SSPP_SCALER_VER(3, 3)); =20 +static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =3D + _VIG_SBLK(SSPP_SCALER_VER(3, 4)); + static const struct dpu_sspp_sub_blks dpu_rgb_sblk =3D _RGB_SBLK(); =20 static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D _DMA_SBLK(); @@ -357,6 +360,16 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk =3D= { }, }; =20 +static const struct dpu_lm_sub_blks sm8750_lm_sblk =3D { + .maxwidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .maxblendstages =3D 11, /* excluding base layer */ + .blendstage_base =3D { /* offsets relative to mixer base */ + /* 0x40 + n*0x30 */ + 0x40, 0x70, 0xa0, 0xd0, 0x100, 0x130, 0x160, 0x190, 0x1c0, + 0x1f0, 0x220 + }, +}; + static const struct dpu_lm_sub_blks qcm2290_lm_sblk =3D { .maxwidth =3D DEFAULT_DPU_LINE_WIDTH, .maxblendstages =3D 4, /* excluding base layer */ @@ -378,6 +391,11 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk= =3D { .len =3D 0x90, .version =3D 0x40000}, }; =20 +static const struct dpu_dspp_sub_blks sm8750_dspp_sblk =3D { + .pcc =3D {.name =3D "pcc", .base =3D 0x1700, + .len =3D 0x90, .version =3D 0x60000}, +}; + /************************************************************* * PINGPONG sub blocks config *************************************************************/ @@ -420,6 +438,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 =3D { .ctl =3D {.name =3D "ctl", .base =3D 0xF80, .len =3D 0x10}, }; =20 +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 =3D { + .enc =3D {.name =3D "enc", .base =3D 0x100, .len =3D 0x100}, + .ctl =3D {.name =3D "ctl", .base =3D 0xF00, .len =3D 0x24}, +}; + +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_1 =3D { + .enc =3D {.name =3D "enc", .base =3D 0x200, .len =3D 0x100}, + .ctl =3D {.name =3D "ctl", .base =3D 0xF80, .len =3D 0x24}, +}; + /************************************************************* * CDM block config *************************************************************/ @@ -710,3 +738,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_9_2_x1e80100.h" =20 #include "catalog/dpu_10_0_sm8650.h" +#include "catalog/dpu_12_0_sm8750.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index f5ce35cd966459f0edf2dbdd2dbc2693779fac73..de124b722340e98dc78999af1e0= ff50bd65a53c2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -749,6 +749,7 @@ extern const struct dpu_mdss_cfg dpu_sm8450_cfg; extern const struct dpu_mdss_cfg dpu_sa8775p_cfg; extern const struct dpu_mdss_cfg dpu_sm8550_cfg; extern const struct dpu_mdss_cfg dpu_sm8650_cfg; +extern const struct dpu_mdss_cfg dpu_sm8750_cfg; extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; =20 #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index d44461e7e1641b25c5181bf7c0c9bbedffcc869d..18d2237b291fd7acd37da8f74ea= 924c4f4f3d542 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1532,6 +1532,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sm8450-dpu", .data =3D &dpu_sm8450_cfg, }, { .compatible =3D "qcom,sm8550-dpu", .data =3D &dpu_sm8550_cfg, }, { .compatible =3D "qcom,sm8650-dpu", .data =3D &dpu_sm8650_cfg, }, + { .compatible =3D "qcom,sm8750-dpu", .data =3D &dpu_sm8750_cfg, }, { .compatible =3D "qcom,x1e80100-dpu", .data =3D &dpu_x1e80100_cfg, }, {} }; --=20 2.45.2