From nobody Sun Feb 8 23:35:19 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECE51244685; Tue, 29 Apr 2025 16:33:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745944425; cv=none; b=rmI8zJsuHH0pGU3ofCpQrxJl/JTprPWt3pyxsU9RlQmArOoIurW5p+9kdmOJRq4imNp7RGjSz5zUMwE9eEutiEt8BmaL6U7nSUFUJxVzKf7WFJnrJDlfeMtQ/z8JRtQhABNF88vj3AwBf/lSEnhGoUtJ1HB2kfOs1EGWiNPNMk0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745944425; c=relaxed/simple; bh=ITMZtQtSCuisMtzmkO5p3sYMeGrtIHcslnCAPyofEKA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KyvWmIyZGCAmwj52byFRPFv4z6MriqRl0qmz65IDGav0qxdFiAalEL5Y2A5EDhYLXWKUaCTGPQbWDxtKWNh1kZFK5N513Zk/GbrlLSYclIVQ0li2AC6wFjBIoMUS+jD/la0rGguU0niUrxcDAsTYgUyJi546J56jkclC2SBbQHI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=fYjs0bYu; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fYjs0bYu" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53TGXbOi3141150 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 29 Apr 2025 11:33:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1745944418; bh=5fX3jYJgv1EleTFgsZUPSUMZTMUNaUj98y/1xoV41i4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fYjs0bYuFHT7zL4SZzIgI8b/J56WClYfJ1W11ll8slcpdOOs6O7chpbXtJ885yL5x dyyWesZ5oS6CqApQzu8jmD+ikyKX8lMa/2VMrqaRc8kAHsc2kYTwJbGsPtZL8qmCM/ OQ1+pDrJkRa3Cy5EBVnXmoO6oiOElf7SNrbGTavM= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53TGXbBY108651 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 29 Apr 2025 11:33:37 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 29 Apr 2025 11:33:37 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 29 Apr 2025 11:33:37 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53TGXb2M093065; Tue, 29 Apr 2025 11:33:37 -0500 From: Judith Mendez To: Judith Mendez , Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Moteen Shah , Udit Kumar , Bryan Brattlof Subject: [PATCH v2 3/3] arm64: dts: ti: k3-am62p-j722s-common-main: Set eMMC clock parent to default Date: Tue, 29 Apr 2025 11:33:37 -0500 Message-ID: <20250429163337.15634-4-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429163337.15634-1-jm@ti.com> References: <20250429163337.15634-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez Acked-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/= arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 7b65538110e8..fa55c43ca28d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -573,8 +573,6 @@ sdhci0: mmc@fa10000 { power-domains =3D <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 57 1>, <&k3_clks 57 2>; clock-names =3D "clk_ahb", "clk_xin"; - assigned-clocks =3D <&k3_clks 57 2>; - assigned-clock-parents =3D <&k3_clks 57 4>; bus-width =3D <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; --=20 2.49.0