From nobody Mon Feb 9 09:10:22 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62FC024728A; Tue, 29 Apr 2025 16:33:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745944439; cv=none; b=c2500fWxii4QEQ2s8eeLfH7nA37cSagu/HvX39F5qxAuWEphuEvNcd1BlBW3wGpcINPgSq32/ML2s+qaU3GFvFOHiGDpPaGP75bMvCaXW5r7dr6Fd6mpazkFo/5Lm+3flPb1rnP9IWxK78PM7vge51sJWwGFPbo3eDfJoUz0SvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745944439; c=relaxed/simple; bh=HSlF9wREdTEExMvNF166ZItn22mfRPSrDHuwrxh3Peg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GsLhm5a/Bk9WwVRz1O6PhZdIPKeeCwpJOVilcjaFQ8K2eMWpd4lW6HIXs6Zd7Wy9Th5HDxnHkqES+53E02eJZKcHgEEIOzlLwxNyKcgsDzfxIOs5eofaVTOOetdQkHyHTaNkAYWMiPAY7hEbi1/K7fuDl1zEvMvUG9w1bEgQnVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=g2yLV4sx; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="g2yLV4sx" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53TGXqph3141163 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 29 Apr 2025 11:33:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1745944432; bh=F61ZVzuAFIP2lJsQq/L+1CpYNlspg6M2tU1Zq6+tqtY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=g2yLV4sxnWD3TqyCh/yt5wlGmecc39RThfBZcfxQocnBXLaCZYJ+wKswCC8kL4vdQ TPRVggITkm5UiRIjJ1d68pjxw9eA3wOFvLXl+yFwhvp4vaevKufjdsklR0rU09DiBA dcXLChthoThA1KvFAiycjQg5Ns0KOqU/8cB2tZ1M= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53TGXqx5081117 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 29 Apr 2025 11:33:52 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 29 Apr 2025 11:33:52 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 29 Apr 2025 11:33:52 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53TGXb2K093065; Tue, 29 Apr 2025 11:33:37 -0500 From: Judith Mendez To: Judith Mendez , Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Moteen Shah , Udit Kumar , Bryan Brattlof Subject: [PATCH v2 1/3] arm64: dts: ti: k3-am62-main: Set eMMC clock parent to default Date: Tue, 29 Apr 2025 11:33:35 -0500 Message-ID: <20250429163337.15634-2-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429163337.15634-1-jm@ti.com> References: <20250429163337.15634-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez Acked-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 7d355aa73ea2..0c286f600296 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -552,8 +552,6 @@ sdhci0: mmc@fa10000 { power-domains =3D <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 57 5>, <&k3_clks 57 6>; clock-names =3D "clk_ahb", "clk_xin"; - assigned-clocks =3D <&k3_clks 57 6>; - assigned-clock-parents =3D <&k3_clks 57 8>; bus-width =3D <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; --=20 2.49.0