From nobody Sun Dec 14 19:13:41 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 014462206A3; Tue, 29 Apr 2025 15:15:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745939706; cv=none; b=og98TPQgJgaZCOH9WnAIDW3itkFMDi8GmvEAVNvQjZAi/KGaSaOFJh+OPA2ZRJcQT8hTRTIunP9mKc6Oh3+UkWOwlVPXHGlUnl4Ph2sWfkfTeqe9ehz26YdjL12fRFFV4Gtl50a7f36GZhMn1lxKOpJhHiwok6lsfZjHO76aMRw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745939706; c=relaxed/simple; bh=hvHnenv2ZDp2sJ/1/a8LaT52dCUYDrrYq4/vk2JTXYQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=N20QaEBIGcchKE7pqIwz1F7Z9wKTU7FseTx0OCr+omDzfeT6xTJFjdNTqeHRU34FBJBFTgqfY7mI8GniOjoygGG76RnA18RzjHmrDyr4gWNhnnyFFWa1qvL4pLJC1el/B46hgKFabjt4y/UKjUpt3jgSxx+ZkQwWniCBGN5oXVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=H1aus5w7; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="H1aus5w7" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53TFEtfl3129343 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 29 Apr 2025 10:14:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1745939695; bh=RTPopdjSO1h71jQIO/CLJSG8oKyKFgjRgwR6FKTPCBA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=H1aus5w7EQwxsmxyr+dssTkHayACqmmen6YvdZMoynaPTvyLqeg1TOj5M0oTBbeZU oA5iTKK5zuBlURhg66wv6NqhI2Eszlj42l0AMdMBxhbgMHSKLsDKbfwe5Nb1Eejcia aa/6MEEiAQRNkX6L/kos7fTvVQI//l2hmQF8NxSA= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53TFEtNW032102 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 29 Apr 2025 10:14:55 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 29 Apr 2025 10:14:54 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 29 Apr 2025 10:14:54 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53TFEslv129369; Tue, 29 Apr 2025 10:14:54 -0500 From: Judith Mendez To: Judith Mendez , Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Moteen Shah , Udit Kumar Subject: [PATCH v3 1/3] arm64: dts: ti: k3-am6*: Add boot phase flag to support MMC boot Date: Tue, 29 Apr 2025 10:14:52 -0500 Message-ID: <20250429151454.4160506-2-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429151454.4160506-1-jm@ti.com> References: <20250429151454.4160506-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. For eMMC and SD boot modes, voltage regulator nodes, io-expander nodes, gpio nodes, and MMC nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot and eMMC boot. Signed-off-by: Judith Mendez Reviewed-by: Moteen Shah --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts= /ti/k3-am62-lp-sk.dts index 8e9fc00a6b3c..aafdb90c0eb7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -69,6 +69,7 @@ vddshv_sdio: regulator-4 { gpios =3D <&main_gpio0 31 GPIO_ACTIVE_HIGH>; states =3D <1800000 0x0>, <3300000 0x1>; + bootph-all; }; }; =20 @@ -77,12 +78,14 @@ vddshv_sdio_pins_default: vddshv-sdio-default-pins { pinctrl-single,pins =3D < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ >; + bootph-all; }; =20 main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { pinctrl-single,pins =3D < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ >; + bootph-all; }; =20 pmic_irq_pins_default: pmic-irq-default-pins { @@ -118,6 +121,7 @@ exp1: gpio@22 { =20 pinctrl-names =3D "default"; pinctrl-0 =3D <&main_gpio1_ioexp_intr_pins_default>; + bootph-all; }; =20 exp2: gpio@23 { @@ -229,6 +233,14 @@ &tlv320aic3106 { DVDD-supply =3D <&buck2_reg>; }; =20 +&main_gpio0 { + bootph-all; +}; + +&main_gpio1 { + bootph-all; +}; + &gpmc0 { ranges =3D <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = =3D 16MB */ }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index a9557ee73b83..22be41d46eb5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -313,6 +313,7 @@ AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_= DAT5 */ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ >; + bootph-all; }; =20 main_mmc1_pins_default: main-mmc1-default-pins { @@ -634,6 +635,7 @@ &sdhci0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc0_pins_default>; disable-wp; + bootph-all; }; =20 &sdhci1 { --=20 2.49.0