From nobody Mon Feb 9 00:25:43 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BC6A2192E3; Tue, 29 Apr 2025 14:37:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745937480; cv=none; b=Wu27l3aZ4b4GPDB+7OiAqqvlRzjsMgHC+Qi3mVnjtMxgmgkW4cHh0HJ1jjIXVgYMSAmASvKqfQZeS0ndTY5ths2WZJlqgGRiZhJMURBGMprzPMpQnvRB5XYzMgydt6cd0hRj54meBpPQD7niXHeuy/KZ80VLf6I8edRnnZoNTYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745937480; c=relaxed/simple; bh=4Gs21laQhcqWYudDUmToeI3J82M4LIM7c8fcMrnGics=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eiMQLkTyFdgkKBZbudDwZj9XN9HW0dGFnJeTmfnHdHZLb+Y4HmWQLlIso9JLNozCUvdxvZONzjt9SeJezj5j3OxvsJuTQjrPywM2zK078vk3edjUg14UDU1ibxWEzHu3M9+rBwAE58lKu7Mybp8J0m1pv8HOd90U9eq902QkDCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=HInyXyx0; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="HInyXyx0" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53TEbEui3118882 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 29 Apr 2025 09:37:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1745937434; bh=uBLnvq9tnNBll+b98jrKss/AplqJhmEOPSzRV87IXfU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HInyXyx0A+jDK9Yahourju5HZWcbifNe0kqH7qS7C0sMESH02G1c26Q44YRMbC3h1 oaD7C3yySyY4YJhHgiyAqTX2ukjrm5OTJCgpdOVyFTzMDk1R5t0wYwPYZP47ayTUXk cjPO6HqZTgR+FpRueB5MAeZJb1p8aJvrWczRc2W0= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53TEbEEh036133 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 29 Apr 2025 09:37:14 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 29 Apr 2025 09:37:14 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 29 Apr 2025 09:37:14 -0500 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53TEaw7X106235; Tue, 29 Apr 2025 09:36:59 -0500 From: Devarsh Thakkar To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v5 1/3] dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS Date: Tue, 29 Apr 2025 20:06:54 +0530 Message-ID: <20250429143656.3252877-2-devarsht@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250429143656.3252877-1-devarsht@ti.com> References: <20250429143656.3252877-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The DSS controller on TI's AM62L SoC is an update from that on TI's AM625/AM65x/AM62A7 SoC. The AM62L DSS [1] only supports a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling. The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC. [1]: Section 11.7 (Display Subsystem and Peripherals) Link : https://www.ti.com/lit/pdf/sprujb4 Reviewed-by: Krzysztof Kozlowski Reviewed-by: Jayesh Choudhary Reviewed-by: Tomi Valkeinen Signed-off-by: Devarsh Thakkar --- V5: - No change V4: - No change V3: - Remove AM62A references as suggested - Add Reviewed-by V2:=20 - Add Reviewed-by - s/ti,am62l,dss/ti,am62l-dss =20 .../bindings/display/ti/ti,am65x-dss.yaml | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 31c4ffcb599c..a5b13cb7bc73 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -12,18 +12,25 @@ maintainers: - Tomi Valkeinen =20 description: | - The AM625 and AM65x TI Keystone Display SubSystem with two output + The AM625 and AM65x TI Keystone Display SubSystem has two output ports and two video planes. In AM65x DSS, the first video port supports 1 OLDI TX and in AM625 DSS, the first video port output is internally routed to 2 OLDI TXes. The second video port supports DPI format. The first plane is full video plane with all features and the second is a "lite plane" without scaling support. + The AM62L display subsystem has a single output port which supports DPI + format but it only supports single video "lite plane" which does not sup= port + scaling. The output port is routed to SoC boundary via DPI interface and= same + DPI signals are also routed internally to DSI Tx controller present with= in the + SoC. Due to clocking limitations only one of the interface i.e. either D= SI or + DPI can be used at once. =20 properties: compatible: enum: - ti,am625-dss - ti,am62a7-dss + - ti,am62l-dss - ti,am65x-dss =20 reg: @@ -91,6 +98,8 @@ properties: For AM625 DSS, the internal DPI output port node from video port 1. For AM62A7 DSS, the port is tied off inside the SoC. + For AM62L DSS, the DSS DPI output port node from video port 1 + or DSI Tx controller node connected to video port 1. =20 port@1: $ref: /schemas/graph.yaml#/properties/port @@ -123,6 +132,16 @@ allOf: ports: properties: port@0: false + - if: + properties: + compatible: + contains: + const: ti,am62l-dss + then: + properties: + ports: + properties: + port@1: false =20 required: - compatible --=20 2.39.1