From nobody Wed Dec 17 19:04:12 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDCDB2C3768; Tue, 29 Apr 2025 12:55:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931302; cv=none; b=SJBzhfudPlW+EIrbxbR/dTj1SEejQc40+jxUEalhIi8R8z6U4z6YnvpFBaRO+hjv4AHSpbd6aIpud8flUBdl2G96s84SShNxjqiozgj4nqIqlbhbFVEX4doBgepcTLkiMxIlaTRgg6PgMhbadpQ5swofwla3BZXw/JvD0+UlLBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931302; c=relaxed/simple; bh=Jo1F+SpndTahZzn2NeV6YMgPnUybfbIKse3Y/YgP+5c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EW8zmylpw2HEprwzYydCYO/OyzXwwgTjePfJvc9TZoH2BNZ746gaLQFtmP9/lZktTwvAMQxyh5nqaxDvbLma8TOBX2fmY7eHihYe60K/0FwgmX1Yf+CwLQTKOmQFq5p/J45yCH5+Ro/RFhjWGvtej2oq2evA+ob6v+yvtCwDlSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=tkI3gnXl; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="tkI3gnXl" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53TBAPBl006984; Tue, 29 Apr 2025 14:54:49 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= NeK5d7dLB9+0vrbA7blChOQTxW3J9mnj7OUQ3K6i/f4=; b=tkI3gnXlF3mNSEWS 0cLrnrLi0rEDfTH3ajf3lZWAF82i24BV6MxjTmezcZr3tkyUNyn3SoT3FE2gEdiK c/qYZqxAmE6mponvGx6g9PVTDXqK59o9PVM1SyphXhipvYrQE3Fv1KKiJa2pg5pK L//ikgdW2GWxp0UkvFSqvwuS6pIvMw0hKswUyUDALsyEnXAZ4X522FQtre9xv1ST +Q9FlVO+GvgJ5sRFio4zAxZ/H2S4nItEcA/RziqSErGQ+sXi2AOOjB8quoaeKuTw Ujl93+8oav6qZH3Pb+19eZLAfQoUin29CaLVe4aho+PCJl5fm8p8xQXouo/uZF5H baViJg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 468pu7kd1y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Apr 2025 14:54:49 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 2C8DA40080; Tue, 29 Apr 2025 14:53:45 +0200 (CEST) Received: from Webmail-eu.st.com (eqndag1node4.st.com [10.75.129.133]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C57E0ABE2FB; Tue, 29 Apr 2025 14:51:46 +0200 (CEST) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE4.st.com (10.75.129.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 29 Apr 2025 14:51:46 +0200 Received: from localhost (10.252.5.160) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 29 Apr 2025 14:51:46 +0200 From: Fabrice Gasnier To: , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 1/7] dt-bindings: mfd: stm32-lptimer: add support for stm32mp25 Date: Tue, 29 Apr 2025 14:51:27 +0200 Message-ID: <20250429125133.1574167-2-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> References: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-29_04,2025-04-24_02,2025-02-21_01 Content-Type: text/plain; charset="utf-8" Add a new stm32mp25 compatible to stm32-lptimer dt-bindings, to support STM32MP25 SoC. Some features has been updated or added to the low-power timer: - new capture compare channels - up to two PWM channels - PWM input capture - peripheral interconnect in stm32mp25 has been updated (new triggers). - registers/bits has been added or revisited (IER access). So introduce a new compatible to handle this diversity. Reviewed-by: Rob Herring (Arm) Signed-off-by: Fabrice Gasnier --- Changes in V4: - Add Rob's Reviewed-by tag Changes in V3: - Fix yaml indentation issue found by Rob's bot Changes in V2: - Use fallback compatibles, along with stm32mp25 specific compatible - trigger identifier can be up to 4 (e.g. from LPTIM1..5) --- .../bindings/mfd/st,stm32-lptimer.yaml | 40 ++++++++++++++++--- 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/= Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index d41308856408..4eabafb8079d 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -21,7 +21,12 @@ maintainers: =20 properties: compatible: - const: st,stm32-lptimer + oneOf: + - items: + - const: st,stm32mp25-lptimer + - const: st,stm32-lptimer + - items: + - const: st,stm32-lptimer =20 reg: maxItems: 1 @@ -48,13 +53,21 @@ properties: minItems: 1 maxItems: 2 =20 + power-domains: + maxItems: 1 + pwm: type: object additionalProperties: false =20 properties: compatible: - const: st,stm32-pwm-lp + oneOf: + - items: + - const: st,stm32mp25-pwm-lp + - const: st,stm32-pwm-lp + - items: + - const: st,stm32-pwm-lp =20 "#pwm-cells": const: 3 @@ -69,7 +82,12 @@ properties: =20 properties: compatible: - const: st,stm32-lptimer-counter + oneOf: + - items: + - const: st,stm32mp25-lptimer-counter + - const: st,stm32-lptimer-counter + - items: + - const: st,stm32-lptimer-counter =20 required: - compatible @@ -80,7 +98,12 @@ properties: =20 properties: compatible: - const: st,stm32-lptimer-timer + oneOf: + - items: + - const: st,stm32mp25-lptimer-timer + - const: st,stm32-lptimer-timer + - items: + - const: st,stm32-lptimer-timer =20 required: - compatible @@ -92,13 +115,18 @@ patternProperties: =20 properties: compatible: - const: st,stm32-lptimer-trigger + oneOf: + - items: + - const: st,stm32mp25-lptimer-trigger + - const: st,stm32-lptimer-trigger + - items: + - const: st,stm32-lptimer-trigger =20 reg: description: Identify trigger hardware block. items: minimum: 0 - maximum: 2 + maximum: 4 =20 required: - compatible --=20 2.25.1 From nobody Wed Dec 17 19:04:12 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68A8D2D190E; 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Tue, 29 Apr 2025 14:54:48 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 29FAC40074; Tue, 29 Apr 2025 14:53:41 +0200 (CEST) Received: from Webmail-eu.st.com (eqndag1node6.st.com [10.75.129.135]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A7192ABE2F8; Tue, 29 Apr 2025 14:51:47 +0200 (CEST) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE6.st.com (10.75.129.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 29 Apr 2025 14:51:47 +0200 Received: from localhost (10.252.5.160) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 29 Apr 2025 14:51:47 +0200 From: Fabrice Gasnier To: , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 2/7] mfd: stm32-lptimer: add support for stm32mp25 Date: Tue, 29 Apr 2025 14:51:28 +0200 Message-ID: <20250429125133.1574167-3-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> References: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-29_04,2025-04-24_02,2025-02-21_01 Content-Type: text/plain; charset="utf-8" Add support for STM32MP25 SoC. A new hardware configuration register (HWCFGR2) has been added, to gather number of capture/compare channels, autonomous mode and input capture capability. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features. This can now be read from HWCFGR registers. Add new registers to the stm32-lptimer.h: CCMR1, CCR2, HWCFGR1/2 and VERR. Update the stm32_lptimer data struct so signal the number of capture/compare channels to the child devices. Also Remove some unused bit masks (CMPOK_ARROK / CMPOKCF_ARROKCF). Signed-off-by: Fabrice Gasnier --- Changes in V4: - Add DIEROK, ARROK status flags, and their clear flags. Changes in V2: - rely on fallback compatible as no specific .data is associated to the driver. Compatibility is added by reading hardware configuration registers. - read version register, to be used by clockevent child driver - rename register/bits definitions --- drivers/mfd/stm32-lptimer.c | 33 ++++++++++++++++++++++++++- include/linux/mfd/stm32-lptimer.h | 37 ++++++++++++++++++++++++++++--- 2 files changed, 66 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/stm32-lptimer.c b/drivers/mfd/stm32-lptimer.c index b2704a9809c7..09073dbc9c80 100644 --- a/drivers/mfd/stm32-lptimer.c +++ b/drivers/mfd/stm32-lptimer.c @@ -6,6 +6,7 @@ * Inspired by Benjamin Gaignard's stm32-timers driver */ =20 +#include #include #include #include @@ -49,6 +50,36 @@ static int stm32_lptimer_detect_encoder(struct stm32_lpt= imer *ddata) return 0; } =20 +static int stm32_lptimer_detect_hwcfgr(struct stm32_lptimer *ddata) +{ + u32 val; + int ret; + + ret =3D regmap_read(ddata->regmap, STM32_LPTIM_VERR, &ddata->version); + if (ret) + return ret; + + /* Try to guess parameters from HWCFGR: e.g. encoder mode (STM32MP15) */ + ret =3D regmap_read(ddata->regmap, STM32_LPTIM_HWCFGR1, &val); + if (ret) + return ret; + + /* Fallback to legacy init if HWCFGR isn't present */ + if (!val) + return stm32_lptimer_detect_encoder(ddata); + + ddata->has_encoder =3D FIELD_GET(STM32_LPTIM_HWCFGR1_ENCODER, val); + + ret =3D regmap_read(ddata->regmap, STM32_LPTIM_HWCFGR2, &val); + if (ret) + return ret; + + /* Number of capture/compare channels */ + ddata->num_cc_chans =3D FIELD_GET(STM32_LPTIM_HWCFGR2_CHAN_NUM, val); + + return 0; +} + static int stm32_lptimer_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -73,7 +104,7 @@ static int stm32_lptimer_probe(struct platform_device *p= dev) if (IS_ERR(ddata->clk)) return PTR_ERR(ddata->clk); =20 - ret =3D stm32_lptimer_detect_encoder(ddata); + ret =3D stm32_lptimer_detect_hwcfgr(ddata); if (ret) return ret; =20 diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lp= timer.h index 06d3f11dc3c9..a592c8dc716d 100644 --- a/include/linux/mfd/stm32-lptimer.h +++ b/include/linux/mfd/stm32-lptimer.h @@ -17,20 +17,30 @@ #define STM32_LPTIM_IER 0x08 /* Interrupt Enable Reg */ #define STM32_LPTIM_CFGR 0x0C /* Configuration Reg */ #define STM32_LPTIM_CR 0x10 /* Control Reg */ -#define STM32_LPTIM_CMP 0x14 /* Compare Reg */ +#define STM32_LPTIM_CMP 0x14 /* Compare Reg (MP25 CCR1) */ #define STM32_LPTIM_ARR 0x18 /* Autoreload Reg */ #define STM32_LPTIM_CNT 0x1C /* Counter Reg */ +#define STM32_LPTIM_CCMR1 0x2C /* Capture/Compare Mode MP25 */ +#define STM32_LPTIM_CCR2 0x34 /* Compare Reg2 MP25 */ + +#define STM32_LPTIM_HWCFGR2 0x3EC /* Hardware configuration register 2 - M= P25 */ +#define STM32_LPTIM_HWCFGR1 0x3F0 /* Hardware configuration register 1 - M= P15 */ +#define STM32_LPTIM_VERR 0x3F4 /* Version identification register - MP15 */ =20 /* STM32_LPTIM_ISR - bit fields */ +#define STM32_LPTIM_DIEROK_ARROK (BIT(24) | BIT(4)) /* MP25 */ +#define STM32_LPTIM_CMP2_ARROK (BIT(19) | BIT(4)) #define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3) #define STM32_LPTIM_ARROK BIT(4) #define STM32_LPTIM_CMPOK BIT(3) =20 /* STM32_LPTIM_ICR - bit fields */ -#define STM32_LPTIM_ARRMCF BIT(1) +#define STM32_LPTIM_DIEROKCF_ARROKCF (BIT(24) | BIT(4)) /* MP25 */ +#define STM32_LPTIM_CMP2OKCF_ARROKCF (BIT(19) | BIT(4)) #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) +#define STM32_LPTIM_ARRMCF BIT(1) =20 -/* STM32_LPTIM_IER - bit flieds */ +/* STM32_LPTIM_IER - bit fields */ #define STM32_LPTIM_ARRMIE BIT(1) =20 /* STM32_LPTIM_CR - bit fields */ @@ -53,16 +63,37 @@ /* STM32_LPTIM_ARR */ #define STM32_LPTIM_MAX_ARR 0xFFFF =20 +/* STM32_LPTIM_CCMR1 */ +#define STM32_LPTIM_CC2P GENMASK(19, 18) +#define STM32_LPTIM_CC2E BIT(17) +#define STM32_LPTIM_CC2SEL BIT(16) +#define STM32_LPTIM_CC1P GENMASK(3, 2) +#define STM32_LPTIM_CC1E BIT(1) +#define STM32_LPTIM_CC1SEL BIT(0) + +/* STM32_LPTIM_HWCFGR1 */ +#define STM32_LPTIM_HWCFGR1_ENCODER BIT(16) + +/* STM32_LPTIM_HWCFGR2 */ +#define STM32_LPTIM_HWCFGR2_CHAN_NUM GENMASK(3, 0) + +/* STM32_LPTIM_VERR */ +#define STM32_LPTIM_VERR_23 0x23 /* STM32MP25 */ + /** * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent de= vice * @clk: clock reference for this instance * @regmap: register map reference for this instance * @has_encoder: indicates this Low-Power Timer supports encoder mode + * @num_cc_chans: indicates the number of capture/compare channels + * @version: indicates the major and minor revision of the controller */ struct stm32_lptimer { struct clk *clk; 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charset="utf-8" On stm32mp25, DIER (former IER) must only be modified when the lptimer is enabled. On earlier SoCs, it must be only be modified when it is disabled. There's also a new DIEROK flag, to ensure register access has completed. Add a new "set_evt" routine to be used on stm32mp25, called depending on the version register, read by the MFD core (LPTIM_VERR). Signed-off-by: Patrick Delaunay Signed-off-by: Fabrice Gasnier Acked-by: Daniel Lezcano --- Changes in V6: - Fixed warning reported by kernel test robot in https://lore.kernel.org/oe-kbuild-all/202504261456.aCATBoYN-lkp@intel.com/ use FIELD_GET() macro Changes in V5: - Added a delay after timer enable, it needs two clock cycles. Changes in V4: - Daniel suggests to encapsulate IER write into a separate function that manages the enabling/disabling of the LP timer. In addition, DIEROK and ARROK flags checks have been added. So adopt a new routine to set the event into ARR register and enable the interrupt. Changes in V2: - rely on fallback compatible as no specific .data is associated to the driver. Use version data from MFD core. - Added interrupt enable register access update in (missed in V1) --- drivers/clocksource/timer-stm32-lp.c | 61 ++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-stm32-lp.c b/drivers/clocksource/tim= er-stm32-lp.c index 928da2f6de69..6e7944ffd7c0 100644 --- a/drivers/clocksource/timer-stm32-lp.c +++ b/drivers/clocksource/timer-stm32-lp.c @@ -5,6 +5,7 @@ * Pascal Paillet for STMicroelectronics. */ =20 +#include #include #include #include @@ -27,6 +28,7 @@ struct stm32_lp_private { u32 psc; struct device *dev; struct clk *clk; + u32 version; }; =20 static struct stm32_lp_private* @@ -47,12 +49,46 @@ static int stm32_clkevent_lp_shutdown(struct clock_even= t_device *clkevt) return 0; } =20 -static int stm32_clkevent_lp_set_timer(unsigned long evt, - struct clock_event_device *clkevt, - int is_periodic) +static int stm32mp25_clkevent_lp_set_evt(struct stm32_lp_private *priv, un= signed long evt) { - struct stm32_lp_private *priv =3D to_priv(clkevt); + int ret; + u32 val; + + regmap_read(priv->reg, STM32_LPTIM_CR, &val); + if (!FIELD_GET(STM32_LPTIM_ENABLE, val)) { + /* Enable LPTIMER to be able to write into IER and ARR registers */ + regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); + /* + * After setting the ENABLE bit, a delay of two counter clock cycles is = needed + * before the LPTIM is actually enabled. For 32KHz rate, this makes appr= oximately + * 62.5 micro-seconds, round it up. + */ + udelay(63); + } + /* set next event counter */ + regmap_write(priv->reg, STM32_LPTIM_ARR, evt); + /* enable ARR interrupt */ + regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE); + + /* Poll DIEROK and ARROK to ensure register access has completed */ + ret =3D regmap_read_poll_timeout_atomic(priv->reg, STM32_LPTIM_ISR, val, + (val & STM32_LPTIM_DIEROK_ARROK) =3D=3D + STM32_LPTIM_DIEROK_ARROK, + 10, 500); + if (ret) { + dev_err(priv->dev, "access to LPTIM timed out\n"); + /* Disable LPTIMER */ + regmap_write(priv->reg, STM32_LPTIM_CR, 0); + return ret; + } + /* Clear DIEROK and ARROK flags */ + regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_DIEROKCF_ARROKCF); =20 + return 0; +} + +static void stm32_clkevent_lp_set_evt(struct stm32_lp_private *priv, unsig= ned long evt) +{ /* disable LPTIMER to be able to write into IER register*/ regmap_write(priv->reg, STM32_LPTIM_CR, 0); /* enable ARR interrupt */ @@ -61,6 +97,22 @@ static int stm32_clkevent_lp_set_timer(unsigned long evt, regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); 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Tue, 29 Apr 2025 14:54:21 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 630454004D; Tue, 29 Apr 2025 14:53:12 +0200 (CEST) Received: from Webmail-eu.st.com (eqndag1node4.st.com [10.75.129.133]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 648E6A7751D; Tue, 29 Apr 2025 14:51:49 +0200 (CEST) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE4.st.com (10.75.129.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 29 Apr 2025 14:51:49 +0200 Received: from localhost (10.252.5.160) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 29 Apr 2025 14:51:48 +0200 From: Fabrice Gasnier To: , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 4/7] pwm: stm32-lp: add support for stm32mp25 Date: Tue, 29 Apr 2025 14:51:30 +0200 Message-ID: <20250429125133.1574167-5-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> References: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-29_04,2025-04-24_02,2025-02-21_01 Add support for STM32MP25 SoC. A new compatible has been added to the dt-bindings. It represents handle new features, registers and bits diversity. It isn't used currently in the driver, as matching is done by retrieving MFD parent data. New dedicated capture/compare channels has been added: e.g. a new compare register for channel 2. Some controls (polarity / cc channel enable) are handled in CCMR register on this new variant (instead of wavepol bit). So, Low-power timer can now have up to two PWM outputs. Use device data from the MFD parent to configure the number of PWM channels e.g. 'npwm'. Update current get_state() and apply() ops to support either: - one PWM channel (as on older revision, or LPTIM5 on STM32MP25) - two PWM channels (e.g. LPTIM1/2/3/4 on STM32MP25 that has the full feature set) Introduce new routines to manage common prescaler, reload register and global enable bit. Acked-by: Uwe Kleine-K=C3=B6nig Signed-off-by: Fabrice Gasnier --- Changes in V5: - Add Uwe's Acked-by Changes in V2: - rely on fallback compatible as no specific .data is associated to the driver. Matching is achieved by using MFD parent data. - renamed registers/bits defintions --- drivers/pwm/pwm-stm32-lp.c | 219 ++++++++++++++++++++++++++++++++----- 1 file changed, 193 insertions(+), 26 deletions(-) diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index 5832dce8ed9d..4789eafb8bac 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -20,6 +20,7 @@ struct stm32_pwm_lp { struct clk *clk; struct regmap *regmap; + unsigned int num_cc_chans; }; =20 static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip) @@ -30,13 +31,101 @@ static inline struct stm32_pwm_lp *to_stm32_pwm_lp(str= uct pwm_chip *chip) /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescale= r */ #define STM32_LPTIM_MAX_PRESCALER 128 =20 +static int stm32_pwm_lp_update_allowed(struct stm32_pwm_lp *priv, int chan= nel) +{ + int ret; + u32 ccmr1; + unsigned long ccmr; + + /* Only one PWM on this LPTIMER: enable, prescaler and reload value can b= e changed */ + if (!priv->num_cc_chans) + return true; + + ret =3D regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); + if (ret) + return ret; + ccmr =3D ccmr1 & (STM32_LPTIM_CC1E | STM32_LPTIM_CC2E); + + /* More than one channel enabled: enable, prescaler or ARR value can't be= changed */ + if (bitmap_weight(&ccmr, sizeof(u32) * BITS_PER_BYTE) > 1) + return false; + + /* + * Only one channel is enabled (or none): check status on the other chann= el, to + * report if enable, prescaler or ARR value can be changed. + */ + if (channel) + return !(ccmr1 & STM32_LPTIM_CC1E); + else + return !(ccmr1 & STM32_LPTIM_CC2E); +} + +static int stm32_pwm_lp_compare_channel_apply(struct stm32_pwm_lp *priv, i= nt channel, + bool enable, enum pwm_polarity polarity) +{ + u32 ccmr1, val, mask; + bool reenable; + int ret; + + /* No dedicated CC channel: nothing to do */ + if (!priv->num_cc_chans) + return 0; + + ret =3D regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); + if (ret) + return ret; + + if (channel) { + /* Must disable CC channel (CCxE) to modify polarity (CCxP), then re-ena= ble */ + reenable =3D (enable && FIELD_GET(STM32_LPTIM_CC2E, ccmr1)) && + (polarity !=3D FIELD_GET(STM32_LPTIM_CC2P, ccmr1)); + + mask =3D STM32_LPTIM_CC2SEL | STM32_LPTIM_CC2E | STM32_LPTIM_CC2P; + val =3D FIELD_PREP(STM32_LPTIM_CC2P, polarity); + val |=3D FIELD_PREP(STM32_LPTIM_CC2E, enable); + } else { + reenable =3D (enable && FIELD_GET(STM32_LPTIM_CC1E, ccmr1)) && + (polarity !=3D FIELD_GET(STM32_LPTIM_CC1P, ccmr1)); + + mask =3D STM32_LPTIM_CC1SEL | STM32_LPTIM_CC1E | STM32_LPTIM_CC1P; + val =3D FIELD_PREP(STM32_LPTIM_CC1P, polarity); + val |=3D FIELD_PREP(STM32_LPTIM_CC1E, enable); + } + + if (reenable) { + u32 cfgr, presc; + unsigned long rate; + unsigned int delay_us; + + ret =3D regmap_update_bits(priv->regmap, STM32_LPTIM_CCMR1, + channel ? STM32_LPTIM_CC2E : STM32_LPTIM_CC1E, 0); + if (ret) + return ret; + /* + * After a write to the LPTIM_CCMRx register, a new write operation can = only be + * performed after a delay of at least (PRESC =C3=97 3) clock cycles + */ + ret =3D regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); + if (ret) + return ret; + presc =3D FIELD_GET(STM32_LPTIM_PRESC, cfgr); + rate =3D clk_get_rate(priv->clk) >> presc; + if (!rate) + return -EINVAL; + delay_us =3D 3 * DIV_ROUND_UP(USEC_PER_SEC, rate); + usleep_range(delay_us, delay_us * 2); + } + + return regmap_update_bits(priv->regmap, STM32_LPTIM_CCMR1, mask, val); +} + static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pw= m, const struct pwm_state *state) { struct stm32_pwm_lp *priv =3D to_stm32_pwm_lp(chip); unsigned long long prd, div, dty; struct pwm_state cstate; - u32 val, mask, cfgr, presc =3D 0; + u32 arr, val, mask, cfgr, presc =3D 0; bool reenable; int ret; =20 @@ -45,10 +134,28 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, s= truct pwm_device *pwm, =20 if (!state->enabled) { if (cstate.enabled) { - /* Disable LP timer */ - ret =3D regmap_write(priv->regmap, STM32_LPTIM_CR, 0); + /* Disable CC channel if any */ + ret =3D stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, false, + state->polarity); if (ret) return ret; + ret =3D regmap_write(priv->regmap, pwm->hwpwm ? + STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, 0); + if (ret) + return ret; + + /* Check if the timer can be disabled */ + ret =3D stm32_pwm_lp_update_allowed(priv, pwm->hwpwm); + if (ret < 0) + return ret; + + if (ret) { + /* Disable LP timer */ + ret =3D regmap_write(priv->regmap, STM32_LPTIM_CR, 0); + if (ret) + return ret; + } + /* disable clock to PWM counter */ clk_disable(priv->clk); } @@ -79,6 +186,23 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, st= ruct pwm_device *pwm, dty =3D prd * state->duty_cycle; do_div(dty, state->period); =20 + ret =3D regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); + if (ret) + return ret; + + /* + * When there are several channels, they share the same prescaler and rel= oad value. + * Check if this can be changed, or the values are the same for all chann= els. + */ + if (!stm32_pwm_lp_update_allowed(priv, pwm->hwpwm)) { + ret =3D regmap_read(priv->regmap, STM32_LPTIM_ARR, &arr); + if (ret) + return ret; + + if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) !=3D presc) || (arr !=3D prd - 1= )) + return -EBUSY; + } + if (!cstate.enabled) { /* enable clock to drive PWM counter */ ret =3D clk_enable(priv->clk); @@ -86,15 +210,20 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, s= truct pwm_device *pwm, return ret; } =20 - ret =3D regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); - if (ret) - goto err; - if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) !=3D presc) || - (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) !=3D state->polarity)) { + ((FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) !=3D state->polarity) && !priv-= >num_cc_chans)) { val =3D FIELD_PREP(STM32_LPTIM_PRESC, presc); - val |=3D FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); - mask =3D STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL; + mask =3D STM32_LPTIM_PRESC; + + if (!priv->num_cc_chans) { + /* + * WAVPOL bit is only available when no capature compare channel is use= d, + * e.g. on LPTIMER instances that have only one output channel. CCMR1 is + * used otherwise. + */ + val |=3D FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); + mask |=3D STM32_LPTIM_WAVPOL; + } =20 /* Must disable LP timer to modify CFGR */ reenable =3D true; @@ -120,20 +249,27 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, = struct pwm_device *pwm, if (ret) goto err; =20 - ret =3D regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty)); + /* Write CMP/CCRx register and ensure it's been properly written */ + ret =3D regmap_write(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_= LPTIM_CMP, + prd - (1 + dty)); if (ret) goto err; =20 - /* ensure CMP & ARR registers are properly written */ - ret =3D regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, + /* ensure ARR and CMP/CCRx registers are properly written */ + ret =3D regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, pwm-= >hwpwm ? + (val & STM32_LPTIM_CMP2_ARROK) =3D=3D STM32_LPTIM_CMP2_ARROK : (val & STM32_LPTIM_CMPOK_ARROK) =3D=3D STM32_LPTIM_CMPOK_ARROK, 100, 1000); if (ret) { dev_err(pwmchip_parent(chip), "ARR/CMP registers write issue\n"); goto err; } - ret =3D regmap_write(priv->regmap, STM32_LPTIM_ICR, - STM32_LPTIM_CMPOKCF_ARROKCF); + ret =3D regmap_write(priv->regmap, STM32_LPTIM_ICR, pwm->hwpwm ? + STM32_LPTIM_CMP2OKCF_ARROKCF : STM32_LPTIM_CMPOKCF_ARROKCF); + if (ret) + goto err; + + ret =3D stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, true, state-= >polarity); if (ret) goto err; =20 @@ -161,11 +297,22 @@ static int stm32_pwm_lp_get_state(struct pwm_chip *ch= ip, { struct stm32_pwm_lp *priv =3D to_stm32_pwm_lp(chip); unsigned long rate =3D clk_get_rate(priv->clk); - u32 val, presc, prd; + u32 val, presc, prd, ccmr1; + bool enabled; u64 tmp; =20 regmap_read(priv->regmap, STM32_LPTIM_CR, &val); - state->enabled =3D !!FIELD_GET(STM32_LPTIM_ENABLE, val); + enabled =3D !!FIELD_GET(STM32_LPTIM_ENABLE, val); + if (priv->num_cc_chans) { + /* There's a CC chan, need to also check if it's enabled */ + regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); + if (pwm->hwpwm) + enabled &=3D !!FIELD_GET(STM32_LPTIM_CC2E, ccmr1); + else + enabled &=3D !!FIELD_GET(STM32_LPTIM_CC1E, ccmr1); + } + state->enabled =3D enabled; + /* Keep PWM counter clock refcount in sync with PWM initial state */ if (state->enabled) { int ret =3D clk_enable(priv->clk); @@ -176,14 +323,21 @@ static int stm32_pwm_lp_get_state(struct pwm_chip *ch= ip, =20 regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val); presc =3D FIELD_GET(STM32_LPTIM_PRESC, val); - state->polarity =3D FIELD_GET(STM32_LPTIM_WAVPOL, val); + if (priv->num_cc_chans) { + if (pwm->hwpwm) + state->polarity =3D FIELD_GET(STM32_LPTIM_CC2P, ccmr1); + else + state->polarity =3D FIELD_GET(STM32_LPTIM_CC1P, ccmr1); + } else { + state->polarity =3D FIELD_GET(STM32_LPTIM_WAVPOL, val); + } =20 regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd); tmp =3D prd + 1; tmp =3D (tmp << presc) * NSEC_PER_SEC; state->period =3D DIV_ROUND_CLOSEST_ULL(tmp, rate); =20 - regmap_read(priv->regmap, STM32_LPTIM_CMP, &val); + regmap_read(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_LPTIM_CMP= , &val); tmp =3D prd - val; tmp =3D (tmp << presc) * NSEC_PER_SEC; state->duty_cycle =3D DIV_ROUND_CLOSEST_ULL(tmp, rate); @@ -201,15 +355,25 @@ static int stm32_pwm_lp_probe(struct platform_device = *pdev) struct stm32_lptimer *ddata =3D dev_get_drvdata(pdev->dev.parent); struct stm32_pwm_lp *priv; struct pwm_chip *chip; + unsigned int npwm; int ret; =20 - chip =3D devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*priv)); + if (!ddata->num_cc_chans) { + /* No dedicated CC channel, so there's only one PWM channel */ + npwm =3D 1; + } else { + /* There are dedicated CC channels, each with one PWM output */ + npwm =3D ddata->num_cc_chans; + } + + chip =3D devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*priv)); if (IS_ERR(chip)) return PTR_ERR(chip); priv =3D to_stm32_pwm_lp(chip); =20 priv->regmap =3D ddata->regmap; priv->clk =3D ddata->clk; + priv->num_cc_chans =3D ddata->num_cc_chans; chip->ops =3D &stm32_pwm_lp_ops; =20 ret =3D devm_pwmchip_add(&pdev->dev, chip); @@ -225,12 +389,15 @@ static int stm32_pwm_lp_suspend(struct device *dev) { struct pwm_chip *chip =3D dev_get_drvdata(dev); struct pwm_state state; - - pwm_get_state(&chip->pwms[0], &state); - if (state.enabled) { - dev_err(dev, "The consumer didn't stop us (%s)\n", - chip->pwms[0].label); - return -EBUSY; + unsigned int i; + + for (i =3D 0; i < chip->npwm; i++) { + pwm_get_state(&chip->pwms[i], &state); + if (state.enabled) { + dev_err(dev, "The consumer didn't stop us (%s)\n", + chip->pwms[i].label); + return -EBUSY; + } } =20 return pinctrl_pm_select_sleep_state(dev); --=20 2.25.1 From nobody Wed Dec 17 19:04:12 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 548B88BEE; Tue, 29 Apr 2025 12:54:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; 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charset="utf-8" Enable the STM32 LP timer MFD core and clockevent drivers used on STM32MP257F-EV1 board, for PSCI OSI. Signed-off-by: Fabrice Gasnier --- Changes in v2: - dropped unused IIO trigger, PWM and counter driver unused on upstream board currently, as advised by Krzysztof --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5bb8f09422a2..d106cdac05fa 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -777,6 +777,7 @@ CONFIG_MFD_TI_LP873X=3Dm CONFIG_MFD_TPS65219=3Dy CONFIG_MFD_TPS6594_I2C=3Dm CONFIG_MFD_ROHM_BD718XX=3Dy +CONFIG_MFD_STM32_LPTIMER=3Dm CONFIG_MFD_WCD934X=3Dm CONFIG_MFD_KHADAS_MCU=3Dm CONFIG_REGULATOR_FIXED_VOLTAGE=3Dy @@ -1414,6 +1415,7 @@ CONFIG_CLK_RENESAS_VBATTB=3Dm CONFIG_HWSPINLOCK=3Dy CONFIG_HWSPINLOCK_QCOM=3Dy CONFIG_TEGRA186_TIMER=3Dy +CONFIG_CLKSRC_STM32_LP=3Dy CONFIG_RENESAS_OSTM=3Dy CONFIG_ARM_MHU=3Dy CONFIG_IMX_MBOX=3Dy --=20 2.25.1 From nobody Wed Dec 17 19:04:12 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B40EC2C2ABF; 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charset="utf-8" Add low-power timer (LPTimer) support on STM32MP25 SoC. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features (no capture/compare) channel. Still, LPTIM5 can be used as single PWM, counter, trigger or timer. Signed-off-by: Fabrice Gasnier --- Changes in V2: - Adopt two compatibles: newly introduced "st,stm32mp25-..." compatible, and fallback "st,stm32-...". --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 177 +++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index f3c6cdfd7008..505176276e72 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -238,6 +238,78 @@ rifsc: bus@42080000 { #access-controller-cells =3D <1>; ranges; =20 + lptimer1: timer@40090000 { + compatible =3D "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg =3D <0x40090000 0x400>; + interrupts-extended =3D <&exti1 47 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc CK_KER_LPTIM1>; + clock-names =3D "mux"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 17>; + power-domains =3D <&RET_PD>; + wakeup-source; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-coun= ter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + + trigger@0 { + compatible =3D "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trig= ger"; + reg =3D <0>; + status =3D "disabled"; + }; + }; + + lptimer2: timer@400a0000 { + compatible =3D "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg =3D <0x400a0000 0x400>; + interrupts-extended =3D <&exti1 48 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc CK_KER_LPTIM2>; + clock-names =3D "mux"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 18>; + power-domains =3D <&RET_PD>; + wakeup-source; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-coun= ter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + + trigger@1 { + compatible =3D "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trig= ger"; + reg =3D <1>; + status =3D "disabled"; + }; + }; + i2s2: audio-controller@400b0000 { compatible =3D "st,stm32mp25-i2s"; reg =3D <0x400b0000 0x400>; @@ -799,6 +871,111 @@ i2c8: i2c@46040000 { status =3D "disabled"; }; =20 + lptimer3: timer@46050000 { + compatible =3D "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg =3D <0x46050000 0x400>; + interrupts-extended =3D <&exti2 29 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc CK_KER_LPTIM3>; + clock-names =3D "mux"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 19>; + wakeup-source; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-coun= ter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + + trigger@2 { + compatible =3D "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trig= ger"; + reg =3D <2>; + status =3D "disabled"; + }; + }; + + lptimer4: timer@46060000 { + compatible =3D "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg =3D <0x46060000 0x400>; + interrupts-extended =3D <&exti2 30 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc CK_KER_LPTIM4>; + clock-names =3D "mux"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 20>; + wakeup-source; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-coun= ter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + + trigger@3 { + compatible =3D "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trig= ger"; + reg =3D <3>; + status =3D "disabled"; + }; + }; + + lptimer5: timer@46070000 { + compatible =3D "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg =3D <0x46070000 0x400>; + interrupts-extended =3D <&exti2 31 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc CK_KER_LPTIM5>; + clock-names =3D "mux"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 21>; + wakeup-source; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-coun= ter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + + trigger@4 { + compatible =3D "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trig= ger"; + reg =3D <4>; + status =3D "disabled"; + }; + }; + csi: csi@48020000 { compatible =3D "st,stm32mp25-csi"; reg =3D <0x48020000 0x2000>; --=20 2.25.1 From nobody Wed Dec 17 19:04:12 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9B5C2D0279; Tue, 29 Apr 2025 12:54:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931274; cv=none; b=RTdwTHwbvwhfFpT9fPu2KQ2ljTxAEP/uuPC+TxHg/E/9YKBnP1H56l6NWJDN3N0RRrpthuOFgd/t0GAHYxk52nZ48KyapLa6PcmukbUiTUkcRVlBVYUy6IH7tGYykJZkH03bD1t4wG7nUAM68kQezxeZPegI2Sx0NWFW7xvv2zE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931274; c=relaxed/simple; bh=0UnlsJ/QMPp3en93prvQfDrfGSRGtCvMeCyLsWlTT+o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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charset="utf-8" During the low power modes the generic ARM timer is deactivated, so the the tick broadcast is used, based on LPTIMER3 which is clocked by LSE on STMicroelectronics boards. Signed-off-by: Patrick Delaunay Signed-off-by: Fabrice Gasnier --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 1b88485a62a1..242115863ab4 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -190,6 +190,14 @@ &i2c8 { status =3D "disabled"; }; =20 +/* use LPTIMER with tick broadcast for suspend mode */ +&lptimer3 { + status =3D "okay"; + timer { + status =3D "okay"; + }; +}; + &rtc { status =3D "okay"; }; --=20 2.25.1