From nobody Tue Feb 10 11:23:49 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 23B881519BF; Tue, 29 Apr 2025 12:51:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931070; cv=none; b=rR4AZj0EvUtPRZipEIWcahBJoUSCxsWPBWxWMYUqoRH73ux5kuo+o6iF9oodCAv/IdrFKcDwXPGNJWBaual7RyOb8iYBPjXbjFh7pJsRij0PEkadZ/eOv/e09hYrzAWoDuohgEUXlyRbjxgUTe8ozQYy1KjXolVuUUM13x56kRQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931070; c=relaxed/simple; bh=mM4p95qWMedy93GsBo6RLG89mYhHnvjJG/YR+8v70tA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Gnn6ZTGAoe39STLN9bjbSlMeQCs6g0Pk8iNpkLyRvGpa2yGsct3+u3/Ky4kMGEelUUSqhuvHeyr7P0OG4TwjOrqUWY7L3NQ2HP8Vrq901ohE+rv70PpvyaCkBtoicnok5pOGzk/ghXdtP5G69Lz54CxG/l0W5QngQE9FX91e5bk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=FdekN7RI; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="FdekN7RI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=iWqav UYMkk2zS0WkwPIhuLUNCIesDCmiLEI6YSb22XU=; b=FdekN7RI9979Rq/O7JK67 emzTfyUAJgnr+SrdsRBxhoZH9sBuujo2tjLNXgBn+b3lMa2SSNaWledHGyKu8HrE PF05zHF/GBi5mhDVvlo9ULxEmEv79z9b53W9CNPgPlWo+dMEP0++4om5tVXgi9+Y wbdCFawyh+25OnEp5YiEfM= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wC3DRQeyxBoOlBzDQ--.23007S6; Tue, 29 Apr 2025 20:50:42 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, kw@linux.com Cc: cassel@kernel.org, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v10 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Date: Tue, 29 Apr 2025 20:50:34 +0800 Message-Id: <20250429125036.88060-5-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125036.88060-1-18255117159@163.com> References: <20250429125036.88060-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wC3DRQeyxBoOlBzDQ--.23007S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxuryrJFW3WF4UXFW5AF4rGrg_yoWrXrWDpa yrAwn0yrW8Ar4aqa1DZFnIvF13AF9xAFyxZa97GwnavFy2krWjg340krWaqF1SkrZFgFy3 Gr4UJFyrCwn7tFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziID7hUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhQ+o2gQxspzYgABsX Content-Type: text/plain; charset="utf-8" Use the PCI core is now exposing generic macros for the host bridges to search for the PCIe capabilities, make use of them in the DWC driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v9: - Resolved [v9 4/6] compilation error. The latest 6.15 rc1 merge __dw_pcie_find_vsec_capability, which uses=20 dw_pcie_find_next_ext_capability. Changes since v8: - None Changes since v7: - Resolve compilation errors. Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-3-18255117159@163.c= om/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-3-18255117159@163.c= om/ - Kconfig add "select PCI_HOST_HELPERS" --- drivers/pci/controller/dwc/pcie-designware.c | 76 +++----------------- 1 file changed, 9 insertions(+), 67 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 97d76d3dc066..837188f579a2 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -205,83 +205,25 @@ void dw_pcie_version_detect(struct dw_pcie *pci) pci->type =3D ver; } =20 -/* - * These interfaces resemble the pci_find_*capability() interfaces, but th= ese - * are for configuring host controllers, which are bridges *to* PCI device= s but - * are not PCI devices themselves. - */ -static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, - u8 cap) +static int dw_pcie_read_cfg(void *priv, int where, int size, u32 *val) { - u8 cap_id, next_cap_ptr; - u16 reg; - - if (!cap_ptr) - return 0; - - reg =3D dw_pcie_readw_dbi(pci, cap_ptr); - cap_id =3D (reg & 0x00ff); - - if (cap_id > PCI_CAP_ID_MAX) - return 0; + struct dw_pcie *pci =3D priv; =20 - if (cap_id =3D=3D cap) - return cap_ptr; + *val =3D dw_pcie_read_dbi(pci, where, size); =20 - next_cap_ptr =3D (reg & 0xff00) >> 8; - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCIBIOS_SUCCESSFUL; } =20 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) { - u8 next_cap_ptr; - u16 reg; - - reg =3D dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); - next_cap_ptr =3D (reg & 0x00ff); - - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCI_FIND_NEXT_CAP_TTL(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, + pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); =20 -static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, - u8 cap) -{ - u32 header; - int ttl; - int pos =3D PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl =3D (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (start) - pos =3D start; - - header =3D dw_pcie_readl_dbi(pci, pos); - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header =3D=3D 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) =3D=3D cap && pos !=3D start) - return pos; - - pos =3D PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - header =3D dw_pcie_readl_dbi(pci, pos); - } - - return 0; -} - u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { - return dw_pcie_find_next_ext_capability(pci, 0, cap); + return PCI_FIND_NEXT_EXT_CAPABILITY(dw_pcie_read_cfg, 0, cap, pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); =20 @@ -294,8 +236,8 @@ static u16 __dw_pcie_find_vsec_capability(struct dw_pci= e *pci, u16 vendor_id, if (vendor_id !=3D dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) return 0; =20 - while ((vsec =3D dw_pcie_find_next_ext_capability(pci, vsec, - PCI_EXT_CAP_ID_VNDR))) { + while ((vsec =3D PCI_FIND_NEXT_EXT_CAPABILITY( + dw_pcie_read_cfg, vsec, PCI_EXT_CAP_ID_VNDR, pci))) { header =3D dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); if (PCI_VNDR_HEADER_ID(header) =3D=3D vsec_id) return vsec; --=20 2.25.1