From nobody Mon Feb 9 09:07:52 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E448A20E023; Tue, 29 Apr 2025 12:51:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931092; cv=none; b=YK7bY/nZjWxAs7Z9m6FHL64E1HvL4VkzIdIGYxhV5xcLfIBGFjcv9E9MDG4xjC922Hu5gZyKeys2bb0kUyIDikTicNRMm+gLs1fl3xI5j6mq+JLSOt75Im+kKF144MsQnjeNJE1ARaeRj/zFIFZ85a5hMIBxdHeRa1YyfIfsUgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931092; c=relaxed/simple; bh=J2jKQJBHaj6ec7/MlBjXVZ4a+VIqlvn1ACEf66l+0l0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Qqin4+eXogI3/HmXFnMVUEkKYzzz00/9Vnuag9CGnWsB+Z7miIkFk3txlGL9ZEbtB8X1k/Sg4i6pS1yV2eXmvmGecLZgDHIDRORg4xvlLtfWdswckjN9+O3CL3TodAceN+IyXKfaEBJkt2eHNCmIXEtv9JmXHXQDb5hFippuixM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=IyxRGzjy; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="IyxRGzjy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=haJr+ Ji0+AgbErl66drGXSA+m5yVDrg1sOKRRvEKpXg=; b=IyxRGzjyAlIUtn/onz47g vp1dpryZ5Iu8eAGZ7OAOe/EiP80LMzwHFhufy+AvLZIWCc8+/huY3eMZZbFdzzD2 CZHuFuXwxTpsJcfhqJ/+9xZ7kiLQOTZi0E254GxXRV6ii1TyRg1ze5l8ZuJJg9vA IoD7vD3TmbTyQwvYPMB3gY= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wC3DRQeyxBoOlBzDQ--.23007S3; Tue, 29 Apr 2025 20:50:40 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, kw@linux.com Cc: cassel@kernel.org, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v10 1/6] PCI: Introduce generic bus config read helper function Date: Tue, 29 Apr 2025 20:50:31 +0800 Message-Id: <20250429125036.88060-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125036.88060-1-18255117159@163.com> References: <20250429125036.88060-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wC3DRQeyxBoOlBzDQ--.23007S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7uF18WF13CFW8ZFyfAF4rAFb_yoW8tF43pF W5AF1fCr48JFy3Aan5Zay8GFy5GF97tFWUGrWxC3sxZF1akayjyasaga43Zry2grWDZr1I v395KFyUC3WkAFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zR1mhrUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhc+o2gQxspzIQABsX Content-Type: text/plain; charset="utf-8" The primary PCI config space accessors are tied to the size of the read (byte/word/dword). Upcoming refactoring of PCI capability discovery logic requires passing a config accessor function that must be able to perform read with different sizes. Add any size config space read accessor pci_bus_read_config() to allow giving it as the config space accessor to the upcoming PCI capability discovery macro. Reconstructs the PCI function discovery logic to prepare for unified configuration of access modes. No function changes are intended. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v9: - None Changes since v8: - The new split is patch 1/6. - The patch commit message were modified. --- drivers/pci/access.c | 17 +++++++++++++++++ drivers/pci/pci.h | 2 ++ 2 files changed, 19 insertions(+) diff --git a/drivers/pci/access.c b/drivers/pci/access.c index b123da16b63b..603332658ab3 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -85,6 +85,23 @@ EXPORT_SYMBOL(pci_bus_write_config_byte); EXPORT_SYMBOL(pci_bus_write_config_word); EXPORT_SYMBOL(pci_bus_write_config_dword); =20 +int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 siz= e, + u32 *val) +{ + struct pci_bus *bus =3D priv; + int ret; + + if (size =3D=3D 1) + ret =3D pci_bus_read_config_byte(bus, devfn, where, (u8 *)val); + else if (size =3D=3D 2) + ret =3D pci_bus_read_config_word(bus, devfn, where, (u16 *)val); + else + ret =3D pci_bus_read_config_dword(bus, devfn, where, val); + + return ret; +} +EXPORT_SYMBOL_GPL(pci_bus_read_config); + int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index b81e99cd4b62..5e1477d6e254 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -88,6 +88,8 @@ extern bool pci_early_dump; bool pcie_cap_has_lnkctl(const struct pci_dev *dev); bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); bool pcie_cap_has_rtctl(const struct pci_dev *dev); +int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 siz= e, + u32 *val); =20 /* Functions internal to the PCI core code */ =20 --=20 2.25.1 From nobody Mon Feb 9 09:07:52 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 21BE12D027F; Tue, 29 Apr 2025 12:51:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931077; cv=none; b=NZbCqWO20mHnAO466E4RDOYLC9Zd/RivwZ2I+bu/7O4zPAqZy34SKUzOC9KM25plco6I12GPY2M2VdKr0sH9cj9obzTSeyXjo08VEa36jWBr0UUm9XNsnR3kWedVtXndLqOScmD2K/+FLCVz6ebO6V9bNQrXS9/k9GpWTFAgl9A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931077; c=relaxed/simple; bh=GeVo1XDHDWysYKqXEPUFdiJKPWlA1aqifJcZbkM5QLk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RcNSjHmZbDBxTlU5QmoLXExXJCT7cp+xvLpIJPretsWKLt6tPwqGXlTeQpRRfnAniFGHME4rzyw66bvTn2bXWukGB6v7RazOQ4Wmncy+WDdZ4YAVtteQ1Ngo1w+izHwGMAr04kWcyddBuSY8mHZybs0cF0CtTgZGON5DcTUAKkw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Cf+xLs/Q; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Cf+xLs/Q" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=cBcr/ 3AXCJ2HUs1iKRmGu+NHILyOf7bAb1JgTi8RouA=; b=Cf+xLs/Q5tgc6bry51+SB WO7SWg2BDnPMJEEhgS2YkASmqJzMii3IqEu1q1h7UtJI1AUays3HcR+59e8GVg1e RYblMXlVjmc5lnM2UPm+70bCAasslaS32B72YuwAOamhRvcDV2XFHOf/SQKLd1Hx XGeRoxKjCT5UiHFn3N7nRo= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wC3DRQeyxBoOlBzDQ--.23007S4; Tue, 29 Apr 2025 20:50:41 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, kw@linux.com Cc: cassel@kernel.org, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v10 2/6] PCI: Clean up __pci_find_next_cap_ttl() readability Date: Tue, 29 Apr 2025 20:50:32 +0800 Message-Id: <20250429125036.88060-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125036.88060-1-18255117159@163.com> References: <20250429125036.88060-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wC3DRQeyxBoOlBzDQ--.23007S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7tFyUuF4Uur4kJr47Cw18uFg_yoW8trW5pF 98Ca47ArWrJF1UCws293W2yr13Xa4DCay8G3yFg3s8ZFy2yF1vqws29F1aqF17XrZ29F15 X3sIv395CFy5AaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zKhFxtUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxU+o2gQySUykgAAsn Content-Type: text/plain; charset="utf-8" Refactor the __pci_find_next_cap_ttl() to improve code clarity: - Replace magic number 0x40 with PCI_STD_HEADER_SIZEOF. - Use ALIGN_DOWN() for position alignment instead of manual bitmask. - Extract PCI capability fields via FIELD_GET() with standardized masks. - Add necessary headers (linux/align.h, uapi/linux/pci_regs.h). The changes are purely non-functional cleanups, ensuring behavior remains identical to the original implementation. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v9: - None Changes since v8: - Split into patch 1/6, patch 2/6. - The drivers/pci/pci.c | 10 ++++++---- include/uapi/linux/pci_regs.h | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4d7c9f64ea24..1c29e8f20cb5 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -9,6 +9,7 @@ */ =20 #include +#include #include #include #include @@ -30,6 +31,7 @@ #include #include #include +#include #include "pci.h" =20 DEFINE_MUTEX(pci_slot_mutex); @@ -432,17 +434,17 @@ static u8 __pci_find_next_cap_ttl(struct pci_bus *bus= , unsigned int devfn, pci_bus_read_config_byte(bus, devfn, pos, &pos); =20 while ((*ttl)--) { - if (pos < 0x40) + if (pos < PCI_STD_HEADER_SIZEOF) break; - pos &=3D ~3; + pos =3D ALIGN_DOWN(pos, 4); pci_bus_read_config_word(bus, devfn, pos, &ent); =20 - id =3D ent & 0xff; + id =3D FIELD_GET(PCI_CAP_ID_MASK, ent); if (id =3D=3D 0xff) break; if (id =3D=3D cap) return pos; - pos =3D (ent >> 8); + pos =3D FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent); } return 0; } diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index ba326710f9c8..b59179e1210a 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -206,6 +206,8 @@ /* 0x48-0x7f reserved */ =20 /* Capability lists */ +#define PCI_CAP_ID_MASK 0x00ff +#define PCI_CAP_LIST_NEXT_MASK 0xff00 =20 #define PCI_CAP_LIST_ID 0 /* Capability ID */ #define PCI_CAP_ID_PM 0x01 /* Power Management */ --=20 2.25.1 From nobody Mon Feb 9 09:07:52 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 966532C3778; Tue, 29 Apr 2025 12:51:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931093; cv=none; b=Y/DvpgGx68wQuE2KX3q5l48/ZGD9QF6AKJhSHVX/EIwr7fQSi1yqGZ1OYCCBc4ZWl4b8yAbq/OpvdTfCXHazER2galiXhT92O7qCDqgrA0Xo4jeokgcY9H6yUaJDdCLY2tGUWX7hujDnS/v/ncQiF2s4zu810AMOH+vDvNjm9Fk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931093; c=relaxed/simple; bh=UPLBPlOppJJDXgyiHM2y9/70vZJKWcPvsJgMvVUqDrc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JKDjdB0VcUoq4G5wW9dSkTbQxyU2XTsvIFKpQHlllcw/FWs7cjTjwKBv85UxaktH3uDFouzRHtHXkCn87Wqj3iK/FA363iD+BHA9UbbcHoQqcmZNmWNUjvKuiw6ue8ORr8Cev4EzwNlWw517qnm/gI6L1AGkq6F4Y2O9F7FcJnY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=OfXiXCYe; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="OfXiXCYe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=18/Yn qiL0fF2zD/2UOawbWw8VZS86sgMkrg3RxL8vwQ=; b=OfXiXCYeyqnSgX4AGP1rf MWGMPMnCroGTQrmTMF8Ekinw3Bhk7yydnvDN3Zpjgp9wY5FWFtOMXYLg8LcJTWMq Hty72iDoHicpqXUBK/v2gBApGfsWy+zFrgmoWTLY+QE+ijkaZbkATFldGq+Q1FKq zTI6n2XNfid5i//7BKycC0= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wC3DRQeyxBoOlBzDQ--.23007S5; Tue, 29 Apr 2025 20:50:41 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, kw@linux.com Cc: cassel@kernel.org, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v10 3/6] PCI: Refactor capability search into common macros Date: Tue, 29 Apr 2025 20:50:33 +0800 Message-Id: <20250429125036.88060-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125036.88060-1-18255117159@163.com> References: <20250429125036.88060-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wC3DRQeyxBoOlBzDQ--.23007S5 X-Coremail-Antispam: 1Uf129KBjvJXoW3XrW7ZF1fZF1ftFyxZFWkWFg_yoW3ury3pr y3A3WSyrW8J3W2qwsIva18tF1aga97Jay7urWxG3s8XFyqka4ktrySkF1aqFy7KrZ7uF13 Xws0qFWrC3ZIyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07UYApwUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwg+o2gQySUylQABs8 Content-Type: text/plain; charset="utf-8" The PCI Capability search functionality is duplicated across the PCI core and several controller drivers. The core's current implementation requires fully initialized PCI device and bus structures, which prevents controller drivers from using it during early initialization phases before these structures are available. Move the Capability search logic into a header-based macro that accepts a config space accessor function as an argument. This enables controller drivers to perform Capability discovery using their early access mechanisms prior to full device initialization while sharing the Capability search code. Convert the existing PCI core Capability search implementation to use this new macro. The macros now implement, parameterized by the config access method. The PCI core functions are converted to utilize these macros with the standard pci_bus_read_config accessors. Controller drivers can later use the same macros with their early access mechanisms while maintaining the existing protection against infinite loops through preserved TTL checks. The ttl parameter was originally an additional safeguard to prevent infinite loops in corrupted config space. However, the PCI_FIND_NEXT_CAP_TTL macro already enforces a TTL limit internally. Removing redundant ttl handling simplifies the interface while maintaining the safety guarantee. This aligns with the macro's design intent of encapsulating TTL management. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v9: - None Changes since v8: - The patch commit message were modified. --- drivers/pci/pci.c | 70 +++++--------------------------------- drivers/pci/pci.h | 86 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+), 61 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1c29e8f20cb5..8a1f47e8f5cc 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -9,7 +9,6 @@ */ =20 #include -#include #include #include #include @@ -31,7 +30,6 @@ #include #include #include -#include #include "pci.h" =20 DEFINE_MUTEX(pci_slot_mutex); @@ -426,35 +424,16 @@ static int pci_dev_str_match(struct pci_dev *dev, con= st char *p, } =20 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, - u8 pos, int cap, int *ttl) + u8 pos, int cap) { - u8 id; - u16 ent; - - pci_bus_read_config_byte(bus, devfn, pos, &pos); - - while ((*ttl)--) { - if (pos < PCI_STD_HEADER_SIZEOF) - break; - pos =3D ALIGN_DOWN(pos, 4); - pci_bus_read_config_word(bus, devfn, pos, &ent); - - id =3D FIELD_GET(PCI_CAP_ID_MASK, ent); - if (id =3D=3D 0xff) - break; - if (id =3D=3D cap) - return pos; - pos =3D FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent); - } - return 0; + return PCI_FIND_NEXT_CAP_TTL(pci_bus_read_config, pos, cap, bus, + devfn); } =20 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) { - int ttl =3D PCI_FIND_CAP_TTL; - - return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); + return __pci_find_next_cap_ttl(bus, devfn, pos, cap); } =20 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) @@ -555,42 +534,11 @@ EXPORT_SYMBOL(pci_bus_find_capability); */ u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) { - u32 header; - int ttl; - u16 pos =3D PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl =3D (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - if (dev->cfg_size <=3D PCI_CFG_SPACE_SIZE) return 0; =20 - if (start) - pos =3D start; - - if (pci_read_config_dword(dev, pos, &header) !=3D PCIBIOS_SUCCESSFUL) - return 0; - - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header =3D=3D 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) =3D=3D cap && pos !=3D start) - return pos; - - pos =3D PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - if (pci_read_config_dword(dev, pos, &header) !=3D PCIBIOS_SUCCESSFUL) - break; - } - - return 0; + return PCI_FIND_NEXT_EXT_CAPABILITY(pci_bus_read_config, start, cap, + dev->bus, dev->devfn); } EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); =20 @@ -650,7 +598,7 @@ EXPORT_SYMBOL_GPL(pci_get_dsn); =20 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) { - int rc, ttl =3D PCI_FIND_CAP_TTL; + int rc; u8 cap, mask; =20 if (ht_cap =3D=3D HT_CAPTYPE_SLAVE || ht_cap =3D=3D HT_CAPTYPE_HOST) @@ -659,7 +607,7 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u= 8 pos, int ht_cap) mask =3D HT_5BIT_CAP_MASK; =20 pos =3D __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, - PCI_CAP_ID_HT, &ttl); + PCI_CAP_ID_HT); while (pos) { rc =3D pci_read_config_byte(dev, pos + 3, &cap); if (rc !=3D PCIBIOS_SUCCESSFUL) @@ -670,7 +618,7 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u= 8 pos, int ht_cap) =20 pos =3D __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos + PCI_CAP_LIST_NEXT, - PCI_CAP_ID_HT, &ttl); + PCI_CAP_ID_HT); } =20 return 0; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 5e1477d6e254..79cd6402ba8d 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -2,7 +2,9 @@ #ifndef DRIVERS_PCI_H #define DRIVERS_PCI_H =20 +#include #include +#include =20 struct pcie_tlp_log; =20 @@ -91,6 +93,90 @@ bool pcie_cap_has_rtctl(const struct pci_dev *dev); int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 siz= e, u32 *val); =20 +/* Standard Capability finder */ +/** + * PCI_FIND_NEXT_CAP_TTL - Find a PCI standard capability + * @read_cfg: Function pointer for reading PCI config space + * @start: Starting position to begin search + * @cap: Capability ID to find + * @args: Arguments to pass to read_cfg function + * + * Iterates through the capability list in PCI config space to find + * the specified capability. Implements TTL (time-to-live) protection + * against infinite loops. + * + * Returns: Position of the capability if found, 0 otherwise. + */ +#define PCI_FIND_NEXT_CAP_TTL(read_cfg, start, cap, args...) \ +({ \ + int __ttl =3D PCI_FIND_CAP_TTL; \ + u8 __id, __found_pos =3D 0; \ + u8 __pos =3D (start); \ + u16 __ent; \ + \ + read_cfg(args, __pos, 1, (u32 *)&__pos); \ + \ + while (__ttl--) { \ + if (__pos < PCI_STD_HEADER_SIZEOF) \ + break; \ + \ + __pos =3D ALIGN_DOWN(__pos, 4); \ + read_cfg(args, __pos, 2, (u32 *)&__ent); \ + \ + __id =3D FIELD_GET(PCI_CAP_ID_MASK, __ent); \ + if (__id =3D=3D 0xff) \ + break; \ + \ + if (__id =3D=3D (cap)) { \ + __found_pos =3D __pos; \ + break; \ + } \ + \ + __pos =3D FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ + } \ + __found_pos; \ +}) + +/* Extended Capability finder */ +/** + * PCI_FIND_NEXT_EXT_CAPABILITY - Find a PCI extended capability + * @read_cfg: Function pointer for reading PCI config space + * @start: Starting position to begin search (0 for initial search) + * @cap: Extended capability ID to find + * @args: Arguments to pass to read_cfg function + * + * Searches the extended capability space in PCI config registers + * for the specified capability. Implements TTL protection against + * infinite loops using a calculated maximum search count. + * + * Returns: Position of the capability if found, 0 otherwise. + */ +#define PCI_FIND_NEXT_EXT_CAPABILITY(read_cfg, start, cap, args...) \ +({ \ + u16 __pos =3D (start) ?: PCI_CFG_SPACE_SIZE; \ + u16 __found_pos =3D 0; \ + int __ttl, __ret; \ + u32 __header; \ + \ + __ttl =3D (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ + while (__ttl-- > 0 && __pos >=3D PCI_CFG_SPACE_SIZE) { \ + __ret =3D read_cfg(args, __pos, 4, &__header); \ + if (__ret !=3D PCIBIOS_SUCCESSFUL) \ + break; \ + \ + if (__header =3D=3D 0) \ + break; \ + \ + if (PCI_EXT_CAP_ID(__header) =3D=3D (cap) && __pos !=3D start) { \ + __found_pos =3D __pos; \ + break; \ + } \ + \ + __pos =3D PCI_EXT_CAP_NEXT(__header); \ + } \ + __found_pos; \ +}) + /* Functions internal to the PCI core code */ =20 #ifdef CONFIG_DMI --=20 2.25.1 From nobody Mon Feb 9 09:07:52 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 23B881519BF; Tue, 29 Apr 2025 12:51:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931070; cv=none; b=rR4AZj0EvUtPRZipEIWcahBJoUSCxsWPBWxWMYUqoRH73ux5kuo+o6iF9oodCAv/IdrFKcDwXPGNJWBaual7RyOb8iYBPjXbjFh7pJsRij0PEkadZ/eOv/e09hYrzAWoDuohgEUXlyRbjxgUTe8ozQYy1KjXolVuUUM13x56kRQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931070; c=relaxed/simple; bh=mM4p95qWMedy93GsBo6RLG89mYhHnvjJG/YR+8v70tA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Gnn6ZTGAoe39STLN9bjbSlMeQCs6g0Pk8iNpkLyRvGpa2yGsct3+u3/Ky4kMGEelUUSqhuvHeyr7P0OG4TwjOrqUWY7L3NQ2HP8Vrq901ohE+rv70PpvyaCkBtoicnok5pOGzk/ghXdtP5G69Lz54CxG/l0W5QngQE9FX91e5bk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=FdekN7RI; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="FdekN7RI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=iWqav UYMkk2zS0WkwPIhuLUNCIesDCmiLEI6YSb22XU=; b=FdekN7RI9979Rq/O7JK67 emzTfyUAJgnr+SrdsRBxhoZH9sBuujo2tjLNXgBn+b3lMa2SSNaWledHGyKu8HrE PF05zHF/GBi5mhDVvlo9ULxEmEv79z9b53W9CNPgPlWo+dMEP0++4om5tVXgi9+Y wbdCFawyh+25OnEp5YiEfM= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wC3DRQeyxBoOlBzDQ--.23007S6; Tue, 29 Apr 2025 20:50:42 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, kw@linux.com Cc: cassel@kernel.org, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v10 4/6] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Date: Tue, 29 Apr 2025 20:50:34 +0800 Message-Id: <20250429125036.88060-5-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125036.88060-1-18255117159@163.com> References: <20250429125036.88060-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wC3DRQeyxBoOlBzDQ--.23007S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxuryrJFW3WF4UXFW5AF4rGrg_yoWrXrWDpa yrAwn0yrW8Ar4aqa1DZFnIvF13AF9xAFyxZa97GwnavFy2krWjg340krWaqF1SkrZFgFy3 Gr4UJFyrCwn7tFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziID7hUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhQ+o2gQxspzYgABsX Content-Type: text/plain; charset="utf-8" Use the PCI core is now exposing generic macros for the host bridges to search for the PCIe capabilities, make use of them in the DWC driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v9: - Resolved [v9 4/6] compilation error. The latest 6.15 rc1 merge __dw_pcie_find_vsec_capability, which uses=20 dw_pcie_find_next_ext_capability. Changes since v8: - None Changes since v7: - Resolve compilation errors. Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-3-18255117159@163.c= om/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-3-18255117159@163.c= om/ - Kconfig add "select PCI_HOST_HELPERS" --- drivers/pci/controller/dwc/pcie-designware.c | 76 +++----------------- 1 file changed, 9 insertions(+), 67 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 97d76d3dc066..837188f579a2 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -205,83 +205,25 @@ void dw_pcie_version_detect(struct dw_pcie *pci) pci->type =3D ver; } =20 -/* - * These interfaces resemble the pci_find_*capability() interfaces, but th= ese - * are for configuring host controllers, which are bridges *to* PCI device= s but - * are not PCI devices themselves. - */ -static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, - u8 cap) +static int dw_pcie_read_cfg(void *priv, int where, int size, u32 *val) { - u8 cap_id, next_cap_ptr; - u16 reg; - - if (!cap_ptr) - return 0; - - reg =3D dw_pcie_readw_dbi(pci, cap_ptr); - cap_id =3D (reg & 0x00ff); - - if (cap_id > PCI_CAP_ID_MAX) - return 0; + struct dw_pcie *pci =3D priv; =20 - if (cap_id =3D=3D cap) - return cap_ptr; + *val =3D dw_pcie_read_dbi(pci, where, size); =20 - next_cap_ptr =3D (reg & 0xff00) >> 8; - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCIBIOS_SUCCESSFUL; } =20 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) { - u8 next_cap_ptr; - u16 reg; - - reg =3D dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); - next_cap_ptr =3D (reg & 0x00ff); - - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCI_FIND_NEXT_CAP_TTL(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, + pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); =20 -static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, - u8 cap) -{ - u32 header; - int ttl; - int pos =3D PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl =3D (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (start) - pos =3D start; - - header =3D dw_pcie_readl_dbi(pci, pos); - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header =3D=3D 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) =3D=3D cap && pos !=3D start) - return pos; - - pos =3D PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - header =3D dw_pcie_readl_dbi(pci, pos); - } - - return 0; -} - u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { - return dw_pcie_find_next_ext_capability(pci, 0, cap); + return PCI_FIND_NEXT_EXT_CAPABILITY(dw_pcie_read_cfg, 0, cap, pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); =20 @@ -294,8 +236,8 @@ static u16 __dw_pcie_find_vsec_capability(struct dw_pci= e *pci, u16 vendor_id, if (vendor_id !=3D dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) return 0; =20 - while ((vsec =3D dw_pcie_find_next_ext_capability(pci, vsec, - PCI_EXT_CAP_ID_VNDR))) { + while ((vsec =3D PCI_FIND_NEXT_EXT_CAPABILITY( + dw_pcie_read_cfg, vsec, PCI_EXT_CAP_ID_VNDR, pci))) { header =3D dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); if (PCI_VNDR_HEADER_ID(header) =3D=3D vsec_id) return vsec; --=20 2.25.1 From nobody Mon Feb 9 09:07:52 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9A0E32C1E3C; Tue, 29 Apr 2025 12:51:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931096; cv=none; b=N1NGbSqmMxIDiEighMs2Ozqh+7pIJvoyTEDZdYuU3PUnXpXM0BQxSiNQKM+oqQHJaAFPVZTehNQRDwO+L0jY6pM1/XfGyJpUn6ZZhRBwvOCA4GMwWByAmTv7xcu3qc9h6nH4x7zna46MhySvfC31pSpe4lR8I7Ptmvcy3ly6VQE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931096; c=relaxed/simple; bh=k/VOt13OojSw7K+V+NfpXrHAjT5wm6azQdPmLAshz9E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jLKuTu//+Z2+ZswGGxS6lKwdtiwLRQKcg+hISHpSDcFKv53Q1FQCLT9ntYZ/ZWXYIO8p2A6H12DgXfecqn6r0wm2RHvJHRrbAlCdmPLV8HUT0wyMeGKsun1WDUBhEJAg9xJC02vHmDxGnDlWLWuHJfzuBrbGh95Vu/EzJUpF4MA= ARC-Authentication-Results: i=1; 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Tue, 29 Apr 2025 20:50:43 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, kw@linux.com Cc: cassel@kernel.org, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v10 5/6] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities Date: Tue, 29 Apr 2025 20:50:35 +0800 Message-Id: <20250429125036.88060-6-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125036.88060-1-18255117159@163.com> References: <20250429125036.88060-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wC3DRQeyxBoOlBzDQ--.23007S7 X-Coremail-Antispam: 1Uf129KBjvJXoWxuryrAr48Cw4rur1kCF4UJwb_yoW5ZF48pF WDGFyfCa1rJFW3uFs3A3W5Xr15tFnak347ta92kw12vF17Cr1UGF12gFy3Kr9xKrs7Wr13 X3yDtFykKrn0yFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziID7hUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwY+o2gQySUy1wAAsx Content-Type: text/plain; charset="utf-8" Use the PCI core is now exposing generic macros for the host bridges to search for the PCIe capabilities, make use of them in the CDNS driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v8 ~ v9: - None Changes since v7: - Resolve compilation errors. Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.c= om/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.c= om - Kconfig add "select PCI_HOST_HELPERS" --- drivers/pci/controller/cadence/pcie-cadence.c | 28 +++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 13 +++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 204e045aed8c..ca4a1a809fcb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -7,6 +7,34 @@ #include =20 #include "pcie-cadence.h" +#include "../../pci.h" + +static int cdns_pcie_read_cfg(void *priv, int where, int size, u32 *val) +{ + struct cdns_pcie *pcie =3D priv; + + if (size =3D=3D 4) + *val =3D cdns_pcie_readl(pcie, where); + else if (size =3D=3D 2) + *val =3D cdns_pcie_readw(pcie, where); + else if (size =3D=3D 1) + *val =3D cdns_pcie_readb(pcie, where); + + return PCIBIOS_SUCCESSFUL; +} + +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap) +{ + return PCI_FIND_NEXT_CAP_TTL(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST, + cap, pcie); +} +EXPORT_SYMBOL_GPL(cdns_pcie_find_capability); + +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) +{ + return PCI_FIND_NEXT_EXT_CAPABILITY(cdns_pcie_read_cfg, 0, cap, pcie); +} +EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability); =20 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 39ee9945c903..56d6a0e73eb7 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -398,6 +398,16 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pc= ie, u32 reg) return readl(pcie->reg_base + reg); } =20 +static inline u32 cdns_pcie_readw(struct cdns_pcie *pcie, u32 reg) +{ + return readw(pcie->reg_base + reg); +} + +static inline u32 cdns_pcie_readb(struct cdns_pcie *pcie, u32 reg) +{ + return readb(pcie->reg_base + reg); +} + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { void __iomem *aligned_addr =3D PTR_ALIGN_DOWN(addr, 0x4); @@ -557,6 +567,9 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_e= p *ep) } #endif =20 +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); =20 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, --=20 2.25.1 From nobody Mon Feb 9 09:07:52 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 929801519BF; Tue, 29 Apr 2025 12:51:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931092; cv=none; b=Svzl7dt83qSgqIVPFjP/8ucMGBhG1iKGM/HDvz+iCp4PFRJBJSF2TnDf4BfXuQy8NfEkguy3cfqKRlzIn66neNnpnnrlr0IYnJEEFLfiovri9eEzDzNAk9heKE2IE5W3nQMDnGGU/qOxAY6RIvt7y/glibAx26C4OvtDyUZvPIk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931092; c=relaxed/simple; bh=LIFvWrRgHAp8WcXL1C9H9Su9AiITghjQgzuYTMVeNJE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XEojg0oCx6LJlrV/D42vyXGfHi6c5UvZWqI3AWx748i/SFiZC1PubNobAOCImDAxfwdQk50Y6tAT2IahCRMFmZs/o62DJHJo4Avxktnss4N+AkCWqWmEK7yJRFm1inCDlSFTRKQBWY3gMWtx3M0X5+eIBvYN2ObRTOBU/Afg+xs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=EK4w4Ahm; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="EK4w4Ahm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=itPj+ LGgFAWjOeDppIeKmgGh662fQ4SAHW3lPD5DKco=; b=EK4w4AhmlT43pD5JD3xrt QSA5FacSeXwTyrtE3LLL2URDsAE+8XALd9TTgV08p7MUx9RIngxEBn/jipO3em4r vNFIfdIAGrGkPkLRlj+xHxoRQ/G6KVnrrD6Euz7k0QIFeEplObAppVac5KQ4XYI9 PypBcL548R15RVY/HAje/U= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wC3DRQeyxBoOlBzDQ--.23007S8; Tue, 29 Apr 2025 20:50:44 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, manivannan.sadhasivam@linaro.org, ilpo.jarvinen@linux.intel.com, kw@linux.com Cc: cassel@kernel.org, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v10 6/6] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode. Date: Tue, 29 Apr 2025 20:50:36 +0800 Message-Id: <20250429125036.88060-7-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125036.88060-1-18255117159@163.com> References: <20250429125036.88060-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wC3DRQeyxBoOlBzDQ--.23007S8 X-Coremail-Antispam: 1Uf129KBjvJXoW3JF1xKr1kGFyxJF47AFW7XFb_yoWxZFWxpF Z8ua4SkF40qrW7uFsrAa15ZrnxtFnIv347Aa92kw13uF129FyUGFyIva43KF1akrs7uF17 XrWDtrsa93W3trUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zisYFZUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwY+o2gQySUy7QAAsL Content-Type: text/plain; charset="utf-8" The PCIe capability/extended capability offsets are not guaranteed to be the same across all SoCs integrating the Cadence PCIe IP. Hence, use the cdns_pcie_find_{ext}_capability() APIs for finding them. This avoids hardcoding the offsets in the driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v8 ~ v9: - None Changes since v7: - Resolve compilation errors. Changes since v6: https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.c= om/ - The patch commit message were modified. Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.c= om - Kconfig add "select PCI_HOST_HELPERS" --- .../pci/controller/cadence/pcie-cadence-ep.c | 40 +++++++++++-------- drivers/pci/controller/cadence/pcie-cadence.h | 5 --- 2 files changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index 599ec4b1223e..5c4b2151d181 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -19,12 +19,13 @@ =20 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) { - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 first_vf_offset, stride; + u16 cap; =20 if (vfn =3D=3D 0) return fn; =20 + cap =3D cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); fn =3D fn + first_vf_offset + ((vfn - 1) * stride); @@ -36,10 +37,11 @@ static int cdns_pcie_ep_write_header(struct pci_epc *ep= c, u8 fn, u8 vfn, struct pci_epf_header *hdr) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; struct cdns_pcie *pcie =3D &ep->pcie; u32 reg; + u16 cap; =20 + cap =3D cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); if (vfn > 1) { dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); return -EINVAL; @@ -224,9 +226,10 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u= 8 fn, u8 vfn, u8 mmc) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* @@ -246,9 +249,10 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u= 8 fn, u8 vfn) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Validate that the MSI feature is actually enabled. */ @@ -269,9 +273,10 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, = u8 func_no, u8 vfunc_no) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); =20 reg =3D cap + PCI_MSIX_FLAGS; @@ -290,9 +295,10 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, = u8 fn, u8 vfn, { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 reg =3D cap + PCI_MSIX_FLAGS; @@ -378,11 +384,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie= _ep *ep, u8 fn, u8 vfn, u8 interrupt_num) { struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme, data, data_mask; - u8 msi_count; u64 pci_addr, pci_addr_mask =3D 0xff; + u8 msi_count, cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -430,14 +436,14 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *e= pc, u8 fn, u8 vfn, u32 *msi_addr_offset) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; struct cdns_pcie *pcie =3D &ep->pcie; u64 pci_addr, pci_addr_mask =3D 0xff; u16 flags, mme, data, data_mask; - u8 msi_count; + u8 msi_count, cap; int ret; int i; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -480,16 +486,16 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *e= pc, u8 fn, u8 vfn, static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 v= fn, u16 interrupt_num) { - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 tbl_offset, msg_data, reg; struct cdns_pcie *pcie =3D &ep->pcie; struct pci_epf_msix_tbl *msix_tbl; struct cdns_pcie_epf *epf; u64 pci_addr_mask =3D 0xff; u64 msg_addr; + u8 bir, cap; u16 flags; - u8 bir; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); epf =3D &ep->epf[fn]; if (vfn > 0) epf =3D &epf->epf[vfn - 1]; @@ -563,7 +569,9 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) int max_epfs =3D sizeof(epc->function_num_map) * 8; int ret, epf, last_fn; u32 reg, value; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP); /* * BIT(0) is hardwired to 1, hence function 0 is always enabled * and can't be disabled anyway. @@ -587,12 +595,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; =20 value =3D cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + cap + PCI_EXP_DEVCAP); value &=3D ~PCI_EXP_DEVCAP_FLR; - cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + cdns_pcie_ep_fn_writel(pcie, epf, cap + PCI_EXP_DEVCAP, + value); } } =20 diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 56d6a0e73eb7..08491275349d 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -125,11 +125,6 @@ */ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) =20 -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - /* * Endpoint PF Registers */ --=20 2.25.1