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[210.61.187.174]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f8597e0bsm8550119a12.44.2025.04.29.01.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 01:51:45 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr, heikki.krogerus@linux.intel.com Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v3 3/6] riscv: dts: spacemit: add PWM support for K1 SoC Date: Tue, 29 Apr 2025 16:50:45 +0800 Message-ID: <20250429085048.1310409-4-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429085048.1310409-1-guodong@riscstar.com> References: <20250429085048.1310409-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT K1 SoC features a PWM controller with 20 independent channels. Add the corresponding 20 PWM nodes to the device tree. Signed-off-by: Guodong Xu --- v3: Changed #pwm-cells from <1> to <3> v2: Changed compatible string with the fallback marvell,pxa910-pwm arch/riscv/boot/dts/spacemit/k1.dtsi | 180 +++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index f4afb35dc6bc..99bf7a3f5458 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -580,5 +580,185 @@ sec_uart1: serial@f0612000 { reg-io-width =3D <4>; status =3D "reserved"; /* for TEE usage */ }; + + pwm0: pwm@d401a000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401a000 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM0>; + resets =3D <&syscon_apbc RESET_PWM0>; + status =3D "disabled"; + }; + + pwm1: pwm@d401a400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401a400 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM1>; + resets =3D <&syscon_apbc RESET_PWM1>; + status =3D "disabled"; + }; + + pwm2: pwm@d401a800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401a800 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM2>; + resets =3D <&syscon_apbc RESET_PWM2>; + status =3D "disabled"; + }; + + pwm3: pwm@d401ac00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401ac00 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM3>; + resets =3D <&syscon_apbc RESET_PWM3>; + status =3D "disabled"; + }; + + pwm4: pwm@d401b000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401b000 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM4>; + resets =3D <&syscon_apbc RESET_PWM4>; + status =3D "disabled"; + }; + + pwm5: pwm@d401b400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401b400 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM5>; + resets =3D <&syscon_apbc RESET_PWM5>; + status =3D "disabled"; + }; + + pwm6: pwm@d401b800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401b800 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM6>; + resets =3D <&syscon_apbc RESET_PWM6>; + status =3D "disabled"; + }; + + pwm7: pwm@d401bc00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401bc00 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM7>; + resets =3D <&syscon_apbc RESET_PWM7>; + status =3D "disabled"; + }; + + pwm8: pwm@d4020000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020000 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM8>; + resets =3D <&syscon_apbc RESET_PWM8>; + status =3D "disabled"; + }; + + pwm9: pwm@d4020400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020400 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM9>; + resets =3D <&syscon_apbc RESET_PWM9>; + status =3D "disabled"; + }; + + pwm10: pwm@d4020800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020800 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM10>; + resets =3D <&syscon_apbc RESET_PWM10>; + status =3D "disabled"; + }; + + pwm11: pwm@d4020c00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020c00 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM11>; + resets =3D <&syscon_apbc RESET_PWM11>; + status =3D "disabled"; + }; + + pwm12: pwm@d4021000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021000 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM12>; + resets =3D <&syscon_apbc RESET_PWM12>; + status =3D "disabled"; + }; + + pwm13: pwm@d4021400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021400 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM13>; + resets =3D <&syscon_apbc RESET_PWM13>; + status =3D "disabled"; + }; + + pwm14: pwm@d4021800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021800 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM14>; + resets =3D <&syscon_apbc RESET_PWM14>; + status =3D "disabled"; + }; + + pwm15: pwm@d4021c00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021c00 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM15>; + resets =3D <&syscon_apbc RESET_PWM15>; + status =3D "disabled"; + }; + + pwm16: pwm@d4022000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4022000 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM16>; + resets =3D <&syscon_apbc RESET_PWM16>; + status =3D "disabled"; + }; + + pwm17: pwm@d4022400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4022400 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM17>; + resets =3D <&syscon_apbc RESET_PWM17>; + status =3D "disabled"; + }; + + pwm18: pwm@d4022800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4022800 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM18>; + resets =3D <&syscon_apbc RESET_PWM18>; + status =3D "disabled"; + }; + + pwm19: pwm@d4022c00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4022c00 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM19>; + resets =3D <&syscon_apbc RESET_PWM19>; + status =3D "disabled"; + }; }; }; --=20 2.43.0