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[210.61.187.174]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f8597e0bsm8550119a12.44.2025.04.29.01.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 01:51:21 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr, heikki.krogerus@linux.intel.com Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v3 1/6] dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K1 PWM support Date: Tue, 29 Apr 2025 16:50:43 +0800 Message-ID: <20250429085048.1310409-2-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429085048.1310409-1-guodong@riscstar.com> References: <20250429085048.1310409-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT K1 SoC reuses the Marvell PXA910-compatible PWM controller with one notable difference: the addition of a resets property. To make the device tree pass schema validation (make dtbs_check W=3D3), this patch updates the binding to accept spacemit,k1-pwm as a compatible string, when used in conjunction with the fallback marvell,pxa910-pwm. Support for the optional resets property is also added, as it is required by the K1 integration but was not present in the original Marvell bindings. Since the PWM reset line may be deasserted during the early bootloader stage, making the resets property optional avoids potential double-deassertion, which could otherwise cause flickering on displays that use PWM for backlight control. Additionally, this patch adjusts the required value of the #pwm-cells property for the new compatible string: - For "spacemit,k1-pwm", #pwm-cells must be set to 3. - For existing Marvell compatibles, #pwm-cells remains 1. Background of #pwm-cells change is by an ongoing community discussion about increasing the #pwm-cells value from 1 to 3 for all Marvell PXA PWM devices. These devices are currently the only ones whose bindings do not pass the line index as the first argument. See [1] for further details. [1] https://lore.kernel.org/all/cover.1738842938.git.u.kleine-koenig@baylib= re.com/ Reviewed-by: Rob Herring (Arm) # v2 Signed-off-by: Guodong Xu --- v3: When compatible string contains "spacemit,k1-pwm", #pwm-cells must be 3 Added Reviewed-by: Rob Herring (Arm) # v2 v2: Accept spacemit,k1-pwm as a compatible string, when used in conjunction with the fallback marvell,pxa910-pwm .../bindings/pwm/marvell,pxa-pwm.yaml | 35 +++++++++++++++---- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/D= ocumentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml index 9ee1946dc2e1..8df327e52810 100644 --- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml @@ -11,26 +11,47 @@ maintainers: =20 allOf: - $ref: pwm.yaml# + - if: + properties: + compatible: + contains: + const: spacemit,k1-pwm + then: + properties: + "#pwm-cells": + const: 3 + else: + properties: + "#pwm-cells": + const: 1 + description: | + Used for specifying the period length in nanoseconds. =20 properties: compatible: - enum: - - marvell,pxa250-pwm - - marvell,pxa270-pwm - - marvell,pxa168-pwm - - marvell,pxa910-pwm + oneOf: + - enum: + - marvell,pxa250-pwm + - marvell,pxa270-pwm + - marvell,pxa168-pwm + - marvell,pxa910-pwm + - items: + - const: spacemit,k1-pwm + - const: marvell,pxa910-pwm =20 reg: # Length should be 0x10 maxItems: 1 =20 "#pwm-cells": - # Used for specifying the period length in nanoseconds - const: 1 + description: Number of cells in a pwm specifier. =20 clocks: maxItems: 1 =20 + resets: + maxItems: 1 + required: - compatible - reg --=20 2.43.0 From nobody Fri Dec 19 09:46:05 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B4B828C5B9 for ; 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[210.61.187.174]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f8597e0bsm8550119a12.44.2025.04.29.01.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 01:51:34 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr, heikki.krogerus@linux.intel.com Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v3 2/6] pwm: pxa: add optional reset control Date: Tue, 29 Apr 2025 16:50:44 +0800 Message-ID: <20250429085048.1310409-3-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429085048.1310409-1-guodong@riscstar.com> References: <20250429085048.1310409-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support optional reset control for the PWM PXA driver. During the probe, it acquires the reset controller using devm_reset_control_get_optional_exclusive_deasserted() to get and deassert the reset controller to enable the PWM channel. Signed-off-by: Guodong Xu --- v3: Dropped the addition of a reset_control field to the struct pxa_pwm_chip Using a local variable for reset in pwm_probe() instead v2: No change drivers/pwm/pwm-pxa.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c index 430bd6a709e9..f6a862531601 100644 --- a/drivers/pwm/pwm-pxa.c +++ b/drivers/pwm/pwm-pxa.c @@ -25,6 +25,7 @@ #include #include #include +#include =20 #include =20 @@ -160,6 +161,7 @@ static int pwm_probe(struct platform_device *pdev) const struct platform_device_id *id =3D platform_get_device_id(pdev); struct pwm_chip *chip; struct pxa_pwm_chip *pc; + struct reset_control *rst; int ret =3D 0; =20 if (IS_ENABLED(CONFIG_OF) && id =3D=3D NULL) @@ -179,6 +181,11 @@ static int pwm_probe(struct platform_device *pdev) if (IS_ERR(pc->clk)) return PTR_ERR(pc->clk); =20 + rst =3D devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, + NULL); + if (IS_ERR(rst)) + return PTR_ERR(rst); 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[210.61.187.174]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f8597e0bsm8550119a12.44.2025.04.29.01.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 01:51:45 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr, heikki.krogerus@linux.intel.com Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v3 3/6] riscv: dts: spacemit: add PWM support for K1 SoC Date: Tue, 29 Apr 2025 16:50:45 +0800 Message-ID: <20250429085048.1310409-4-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429085048.1310409-1-guodong@riscstar.com> References: <20250429085048.1310409-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT K1 SoC features a PWM controller with 20 independent channels. Add the corresponding 20 PWM nodes to the device tree. Signed-off-by: Guodong Xu --- v3: Changed #pwm-cells from <1> to <3> v2: Changed compatible string with the fallback marvell,pxa910-pwm arch/riscv/boot/dts/spacemit/k1.dtsi | 180 +++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index f4afb35dc6bc..99bf7a3f5458 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -580,5 +580,185 @@ sec_uart1: serial@f0612000 { reg-io-width =3D <4>; status =3D "reserved"; /* for TEE usage */ }; + + pwm0: pwm@d401a000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401a000 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM0>; + resets =3D <&syscon_apbc RESET_PWM0>; + status =3D "disabled"; + }; + + pwm1: pwm@d401a400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401a400 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM1>; + resets =3D <&syscon_apbc RESET_PWM1>; + status =3D "disabled"; + }; + + pwm2: pwm@d401a800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401a800 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM2>; + resets =3D <&syscon_apbc RESET_PWM2>; + status =3D "disabled"; + }; + + pwm3: pwm@d401ac00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401ac00 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM3>; + resets =3D <&syscon_apbc RESET_PWM3>; + status =3D "disabled"; + }; + + pwm4: pwm@d401b000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401b000 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM4>; + resets =3D <&syscon_apbc RESET_PWM4>; + status =3D "disabled"; + }; + + pwm5: pwm@d401b400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401b400 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM5>; + resets =3D <&syscon_apbc RESET_PWM5>; + status =3D "disabled"; + }; + + pwm6: pwm@d401b800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401b800 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM6>; + resets =3D <&syscon_apbc RESET_PWM6>; + status =3D "disabled"; + }; + + pwm7: pwm@d401bc00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd401bc00 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM7>; + resets =3D <&syscon_apbc RESET_PWM7>; + status =3D "disabled"; + }; + + pwm8: pwm@d4020000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020000 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM8>; + resets =3D <&syscon_apbc RESET_PWM8>; + status =3D "disabled"; + }; + + pwm9: pwm@d4020400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020400 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM9>; + resets =3D <&syscon_apbc RESET_PWM9>; + status =3D "disabled"; + }; + + pwm10: pwm@d4020800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020800 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM10>; + resets =3D <&syscon_apbc RESET_PWM10>; + status =3D "disabled"; + }; + + pwm11: pwm@d4020c00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4020c00 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM11>; + resets =3D <&syscon_apbc RESET_PWM11>; + status =3D "disabled"; + }; + + pwm12: pwm@d4021000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021000 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM12>; + resets =3D <&syscon_apbc RESET_PWM12>; + status =3D "disabled"; + }; + + pwm13: pwm@d4021400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021400 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM13>; + resets =3D <&syscon_apbc RESET_PWM13>; + status =3D "disabled"; + }; + + pwm14: pwm@d4021800 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021800 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM14>; + resets =3D <&syscon_apbc RESET_PWM14>; + status =3D "disabled"; + }; + + pwm15: pwm@d4021c00 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4021c00 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM15>; + resets =3D <&syscon_apbc RESET_PWM15>; + status =3D "disabled"; + }; + + pwm16: pwm@d4022000 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4022000 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM16>; + resets =3D <&syscon_apbc RESET_PWM16>; + status =3D "disabled"; + }; + + pwm17: pwm@d4022400 { + compatible =3D "spacemit,k1-pwm", "marvell,pxa910-pwm"; + reg =3D <0x0 0xd4022400 0x0 0x10>; + #pwm-cells =3D <3>; + clocks =3D <&syscon_apbc CLK_PWM17>; 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[210.61.187.174]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f8597e0bsm8550119a12.44.2025.04.29.01.51.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 01:51:57 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr, heikki.krogerus@linux.intel.com Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v3 4/6] riscv: dts: spacemit: add pwm14_1 pinctrl setting Date: Tue, 29 Apr 2025 16:50:46 +0800 Message-ID: <20250429085048.1310409-5-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429085048.1310409-1-guodong@riscstar.com> References: <20250429085048.1310409-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds the option 1 (hence the name pwm14_1) pinctrl configuration for PWM14 on the SpacemiT K1 SoC. PWM14 option 1 is used for PWM-based backlight control on MIPI displays. This configuration is present on all existing K1 development boards, such as the Banana Pi BPI-F3 and the Milk-V Jupiter. For reference, a more complete list of PWM0-PWM19 pinctrl configurations including all options can be found in [1]. Note: Since the corresponding functionality for other pins is not yet in use or ready for upstreaming, this patch includes only the pwm14_1 setting. [1] https://lore.kernel.org/all/20250411131423.3802611-7-guodong@riscstar.c= om/ Signed-off-by: Guodong Xu --- v3: No change v2: Discard pwm0-pwm19 pinctrl configurations, and adds only pwm14_1_cfg arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot= /dts/spacemit/k1-pinctrl.dtsi index 283663647a86..195eb8874f3c 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -20,4 +20,11 @@ uart0-2-pins { drive-strength =3D <32>; }; }; + pwm14_1_cfg: pwm14-1-cfg { + pwm14-1-pins { + pinmux =3D ; + bias-pull-up =3D <0>; + drive-strength =3D <32>; + }; + }; }; --=20 2.43.0 From nobody Fri Dec 19 09:46:06 2025 Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A33F6297A40 for ; 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[210.61.187.174]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f8597e0bsm8550119a12.44.2025.04.29.01.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 01:52:07 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr, heikki.krogerus@linux.intel.com Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v3 5/6] pwm: Kconfig: add depends on ARCH_SPACEMIT to PWM_PXA Date: Tue, 29 Apr 2025 16:50:47 +0800 Message-ID: <20250429085048.1310409-6-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429085048.1310409-1-guodong@riscstar.com> References: <20250429085048.1310409-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT K1 SoC uses PWM_PXA driver. Update the Kconfig file for the PWM_PXA driver to allow the SpacemiT K1 SoC to use it. Signed-off-by: Guodong Xu --- v3: No change v2: No change drivers/pwm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 4731d5b90d7e..6731669e724e 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -493,7 +493,7 @@ config PWM_PCA9685 =20 config PWM_PXA tristate "PXA PWM support" - depends on ARCH_PXA || ARCH_MMP || COMPILE_TEST + depends on ARCH_PXA || ARCH_MMP || ARCH_SPACEMIT || COMPILE_TEST depends on HAS_IOMEM help Generic PWM framework driver for PXA. --=20 2.43.0 From nobody Fri Dec 19 09:46:06 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B22D527CB18 for ; Tue, 29 Apr 2025 08:52:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745916762; cv=none; b=GL6T7JsWE4mQzrBJtorIDX1iOZNP+yhSxH/ETyg2FXO0kTmL8XViTRf/M6GE7R0eO+STCJ2+CrpN6q9+KIsAq3gqWuqXcDF8QCg9pfJ9BUVyCr/aEYDvHD4mUfY7LdYDjOAtHC/ow3I+0J6+1nX8ovSftq6haVFNmsQYz86pAiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745916762; c=relaxed/simple; bh=snO5UlRxqymfMmKvVew8ZDq0Uh+aBwp66nsHilnsiK4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bqRmxZKewkG4SFtuyHiPsZxlv7C2KitFZWXyQZ5Bku9T34t1nsJGahQFZyHM9dZbGOIbp4gGngtEhhIrnFydNxmKcYuV+6PAO+Gq4uprkWZSm6k0nmtQShP0dqMW8qPGkDHFLz+eRezGLu+hdveKFI5gTFESG80WzgfzkCqNiJY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com; spf=pass smtp.mailfrom=riscstar.com; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b=SCRRoWfe; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riscstar.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b="SCRRoWfe" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-227b828de00so57021025ad.1 for ; Tue, 29 Apr 2025 01:52:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1745916760; x=1746521560; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2mEqVehBRCDyoxu9q2vBqacMHsZUXwyFpRPZVYhXUX8=; b=SCRRoWfedbJL16NYxzyE8b4wtFlqY+PhCtRsg9BMzyqBc0SP7X0aAgB2Ovr4QF3vGE K6XhrgoT+/iiL4CFUsNoUkMUyw2gdLDw/4tu7l/BGk7tg+dm2zHDnjcKB83LYceZNIxB 73vZG66nl44xhHJLJcoZcZNGVCTGXIukd+lynH2uAPkrR0ofw16DgFLrHBcZNvAhFuAw CjmLGkh28N6YLXYW2qbk/43Au2eQe7fmvZ1aycQquA5UniCWtvlZECoXMG3nCdI/x+HZ uI5Uh5YSbVxtw3frS2Ac3CcPWfJPhqlEHhTUUzWh5oEgeP5hCrKWRIxnabJ+dDPFCKAV T1Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745916760; x=1746521560; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2mEqVehBRCDyoxu9q2vBqacMHsZUXwyFpRPZVYhXUX8=; b=aGITa26GaCmv12e/cVUpEGRexRrjO0v3c0F9cr1gNfPXjeWvrLq1SRTeee97NuM0uV EJB5hE+Ud/5zbyDDpa+jIhZtcU7/eWxkSfns+d8063XxMpQr9trNZ4kBB2E1cs1cXoXH hoool3CXiW01rHQw33ytMOuCfb6ubN9aG91GmNNfQnflPxXKHiy8DAtBdWodJtqSMQzj mB54CmG+Mxmfa/2oArYIWLAjNOBFw43c3JdEUybcpJmWkoO8U8DBsmmA10caNN+ywo4n Qq4Ue4qCAvrQFVmEbNnPy6rbfagvJqL5UU/Xb3NOF5h6+A8cmbzyhBQDUMBOVE+P7HkK cLzg== X-Forwarded-Encrypted: i=1; AJvYcCWxN5ssb0PXtfMsuEQQB2z0uB8n5alwMRrkqv+dTcMPLBvOsUeFRwRCj/k7dFExNYTYUcZAhzHSDLMLtPM=@vger.kernel.org X-Gm-Message-State: AOJu0YwCyYHQaB4IGqlXLGj5JT5YexYK/YzqX9tS2E6JoMxieVP+0ZKZ M6Elov4RSxIzgty761TSXtIt1udBoa185OwG4Q+yzWtm6b3h+wEimWTGkrvEPHM= X-Gm-Gg: ASbGncsZ5fWwFJ4EPH3UFX/m0m9YO0FcEOfoC+DK7W6G9AwFOo/6Ww5b8NhATPpc8wB gMlU95xexMCCK+qUPTu3k5sV9F4huWT/TI7I+HbWsiEfBZ+4VOnebMC5nuX3ODcdnqoxwTiPcJY BjHaQVTi+zbgpExXhlmaE1bMXCWiMeHPGT38DaFSW/6Iwl5xOuhflQqA9YdAJNIxCFL2vRUtK00 khnMijEUvuDbZ7DYhKwnx61BYfq0VQiQdIyyRT8AUbIKJ5L36d/T/4doq8Qyu8d/5Emi0lzkzG5 pz4d0SftDeJxddhtVYyFDPFlnm24v/728OZZJ5yJ5krZqwPyX+af64kSW2pImD6/cT2Cob8fZoO t4J3PZHEAKuCbQSomj0NluFXSVw== X-Google-Smtp-Source: AGHT+IGnvzbUWhLI/YOaGHPG2HlwGVUVLczRsChSXyhLNMaAX1vRU5+feyFIpxGpmIkb1IMqyytUCA== X-Received: by 2002:a17:902:e5cd:b0:220:fe50:5b44 with SMTP id d9443c01a7336-22de7037cb5mr28009905ad.31.1745916760002; Tue, 29 Apr 2025 01:52:40 -0700 (PDT) Received: from localhost.localdomain (210-61-187-174.hinet-ip.hinet.net. [210.61.187.174]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f8597e0bsm8550119a12.44.2025.04.29.01.52.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 01:52:39 -0700 (PDT) From: Guodong Xu To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org, p.zabel@pengutronix.de, drew@pdp7.com, inochiama@gmail.com, geert+renesas@glider.be, heylenay@4d2.org, tglx@linutronix.de, hal.feng@starfivetech.com, unicorn_wang@outlook.com, duje.mihanovic@skole.hr, heikki.krogerus@linux.intel.com Cc: elder@riscstar.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, guodong@riscstar.com Subject: [PATCH v3 6/6] riscv: defconfig: Enable PWM support for SpacemiT K1 SoC Date: Tue, 29 Apr 2025 16:50:48 +0800 Message-ID: <20250429085048.1310409-7-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429085048.1310409-1-guodong@riscstar.com> References: <20250429085048.1310409-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable CONFIG_PWM and CONFIG_PWM_PXA in the defconfig to support the PWM controller used on the SpacemiT K1 SoC. Signed-off-by: Guodong Xu Reviewed-by: Yixun Lan --- v3: No change v2: Changed PWM_PXA from built-in to a loadable module (=3Dm) arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 3c8e16d71e17..3c4d9bb8f01e 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -257,6 +257,8 @@ CONFIG_RPMSG_CTRL=3Dy CONFIG_RPMSG_VIRTIO=3Dy CONFIG_PM_DEVFREQ=3Dy CONFIG_IIO=3Dy +CONFIG_PWM=3Dy +CONFIG_PWM_PXA=3Dm CONFIG_THEAD_C900_ACLINT_SSWI=3Dy CONFIG_PHY_SUN4I_USB=3Dm CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=3Dm --=20 2.43.0