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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2025 06:13:33.1021 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49fbc694-bbb5-4938-7bb1-08dd86e4f836 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7347 Content-Type: text/plain; charset="utf-8" Add update_vector() callback to set/clear ALLOWED_IRR field in a vCPU's APIC backing page for vectors which are emulated by the hypervisor. The ALLOWED_IRR field indicates the interrupt vectors which the guest allows the hypervisor to inject (typically for emulated devices). Interrupt vectors used exclusively by the guest itself and the vectors which are not emulated by the hypervisor, such as IPI vectors, should not be set by the guest in the ALLOWED_IRR fields. As clearing/setting state of a vector will also be used in subsequent commits for other APIC regs (such as APIC_IRR update for sending IPI), add a common update_vector() in Secure AVIC driver. Co-developed-by: Kishon Vijay Abraham I Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- Changes since v4: - Moved Secure AVIC driver update_vector() addition to this patch. - Commit log updates. arch/x86/kernel/apic/x2apic_savic.c | 35 +++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2a= pic_savic.c index 81d932061b7b..9d2e93656037 100644 --- a/arch/x86/kernel/apic/x2apic_savic.c +++ b/arch/x86/kernel/apic/x2apic_savic.c @@ -43,6 +43,34 @@ static __always_inline void set_reg(unsigned int offset,= u32 val) WRITE_ONCE(this_cpu_ptr(apic_page)->regs[offset >> 2], val); } =20 +static inline unsigned long *get_reg_bitmap(unsigned int cpu, unsigned int= offset) +{ + struct apic_page *ap =3D per_cpu_ptr(apic_page, cpu); + + return (unsigned long *) &ap->bytes[offset]; +} + +static inline unsigned int get_vec_bit(unsigned int vector) +{ + /* + * The registers are 32-bit wide and 16-byte aligned. + * Compensate for the resulting bit number spacing. + */ + return vector + 96 * (vector / 32); +} + +static inline void update_vector(unsigned int cpu, unsigned int offset, + unsigned int vector, bool set) +{ + unsigned long *reg =3D get_reg_bitmap(cpu, offset); + unsigned int bit =3D get_vec_bit(vector); + + if (set) + set_bit(bit, reg); + else + clear_bit(bit, reg); +} + #define SAVIC_ALLOWED_IRR 0x204 =20 static u32 savic_read(u32 reg) @@ -144,6 +172,11 @@ static void savic_write(u32 reg, u32 data) } } =20 +static void savic_update_vector(unsigned int cpu, unsigned int vector, boo= l set) +{ + update_vector(cpu, SAVIC_ALLOWED_IRR, vector, set); +} + static void init_apic_page(void) { u32 apic_id; @@ -225,6 +258,8 @@ static struct apic apic_x2apic_savic __ro_after_init = =3D { .eoi =3D native_apic_msr_eoi, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, + + .update_vector =3D savic_update_vector, }; =20 apic_driver(apic_x2apic_savic); --=20 2.34.1