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Mon, 28 Apr 2025 22:59:48 -0700 From: "Sheetal ." To: , , , , CC: , , , , , , , , , , Sheetal Subject: [PATCH v2 08/11] ASoC: tegra: AMX: Add Tegra264 support Date: Tue, 29 Apr 2025 05:59:38 +0000 Message-ID: <20250429055941.901511-9-sheetal@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250429055941.901511-1-sheetal@nvidia.com> References: <20250429055941.901511-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|DS0PR12MB7748:EE_ X-MS-Office365-Filtering-Correlation-Id: 99fcc99c-0cab-49c1-eff7-08dd86e31961 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?7XO5poxIlVXUm6Z/VK4tlJy2IhZVzV0xfkGCTD2ZWaFOEW7Wip84ED6qC2w5?= =?us-ascii?Q?rAaEiKF+nvJPrUMBKc3H9rVxj7EGK4/8JC7bKgyhfRaTC1WqZlkK3/HJjxj9?= =?us-ascii?Q?3X0vES8BTHqZCb4Yj6Z3PPctlmTlYDB4T/R6asXbYzuys+lsJcmz5i0fk3Bp?= =?us-ascii?Q?5DMR/99Klm35qP4XbJyyexlGXJAyzDZBlk2TQNOaeOklLQgZPcyN0df7oqWy?= =?us-ascii?Q?nEQfM78DliFZ+CzJFthtn94hgilh6DDrx6VGS2GsIub60w/6cMz5Dz84GNdS?= =?us-ascii?Q?SmUoDf1Oe89HFijLVWbZTcHSdPnte9M8GdlcamzAevJwVUxURtkiq+bZ9E13?= =?us-ascii?Q?9tzZ3SSfuE42varMOF3B9oqWtBKtJW1nMrzQf+DMBaIkQZA2d3quBxS0x9WR?= =?us-ascii?Q?ykhVoJwqmFsQxrhUaQr82q4anLGRqdYc53DdwLzmD22YJncb4sQUSAlc8TOS?= =?us-ascii?Q?jObwJHisNNkGprlOhpHLwKYB/GZ76AQv4meR+h1vmdkRi8y8n9K4z7v3eWSo?= =?us-ascii?Q?3ucRfbLwfhaAxf6lU+LUc3DZuUrPRxA5getT2ixe8w0/lNPTUogejA26lqR7?= =?us-ascii?Q?iBeaXI/Y6cfBXtRpvfKLC8yP+IuS0Oe+DUnGAsL21a/93Wg4NBD1pMZAHL8H?= =?us-ascii?Q?IWOVp0I2lfmjvxsMfRlKq7rWWmT9XDtbcoqi5UgVX5pYtNm/V8H9sFaJedTu?= =?us-ascii?Q?wqVljiw3yILQf8NB1rE6G7M3i8l3A/NWLcEYHQKQvPGj/ppz6+K9IgK2LC4E?= =?us-ascii?Q?e6I90eYKfF1B5fIvXkVTJkvNoD9gLD+UkNBCEjuJS28DTirPoggrut11/GMK?= =?us-ascii?Q?hSZqx94N79nwG3rs9tQxFrDfe0oV1Uag7aZila9NwTNplhHf7fBEuoqIWh2k?= =?us-ascii?Q?GTlpIfCpmt94nZ5AAKu/8KgR0pCsyQvll73nA5vOFPhPJ2iZVV9fz7NP0UXA?= =?us-ascii?Q?ZUmyRQQ4d5In7G39FRGWqsmy0mzDJbk/pQqd51U9cv/Uqpv9xAjRqTjzwSR2?= =?us-ascii?Q?tAJhAZ6P1JuussKmZC1qdoVTlf7qBy1Quzft9xWjxYhXplufK+sOQpJORf2d?= =?us-ascii?Q?hbZEPgJQelvxHVtWNtAOFffJMPThYox1ifOh5M+l7k71WJfiSlwN3RthgU0/?= =?us-ascii?Q?pN8YfgREsXgFXt7Oly2i3WGlRliafdcSlQQFh93wXMk2d64ucEW1E5ZZDren?= =?us-ascii?Q?cbEem4HVLmYzkEtHZYLkgJR7/9rFM8MhhxD3hz8CwkoRHAG5OfjbdjX1eBnO?= =?us-ascii?Q?YfBHU+1xUnwCYfLdOVgFn6FuX1p7B2/ujENu6yn7WbcZFSgTHHLiLlsrRLRd?= =?us-ascii?Q?SAEihTCe2x/tIixKzAeQXbVED9hpLFfQF+rwFPLSMAhPdaqg0JPb9IQeVX0L?= =?us-ascii?Q?jZ/l0rVKhtPDSshXLei3gIDck5a4wcGCg4894ngKMusHXKKBuPSwMWcaId3U?= =?us-ascii?Q?7NJ3AdomOBjB5k0i7fVdahOM6Y/maIHHEDVrK1mnimKPf6zUIaG8sP5BhZo6?= =?us-ascii?Q?WZLc8M2nIGDpl8NHjq0GyN++4cTNpgGdGgF5?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2025 06:00:09.5641 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99fcc99c-0cab-49c1-eff7-08dd86e31961 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7748 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sheetal Add Tegra264 AMX support with following changes: - Add soc_data for Tegra264-specific variations - Tegra264 AMX supports 32 output channels, hence update the capture DAI channels_max parameter and CIF configuration API. - Register offsets and default values are updated to align with Tegra264. - Add 128 byte map controls for Tegra264 to accommodate each byte per channel (32channels x 32bits). Signed-off-by: Sheetal --- sound/soc/tegra/tegra210_amx.c | 229 ++++++++++++++++++++++++++++++--- sound/soc/tegra/tegra210_amx.h | 34 ++++- 2 files changed, 241 insertions(+), 22 deletions(-) diff --git a/sound/soc/tegra/tegra210_amx.c b/sound/soc/tegra/tegra210_amx.c index 1981b94009cf..7f558c40e097 100644 --- a/sound/soc/tegra/tegra210_amx.c +++ b/sound/soc/tegra/tegra210_amx.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AF= FILIATES. +// SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AF= FILIATES. // All rights reserved. // // tegra210_amx.c - Tegra210 AMX driver @@ -46,21 +46,35 @@ static const struct reg_default tegra210_amx_reg_defaul= ts[] =3D { { TEGRA210_AMX_CFG_RAM_CTRL, 0x00004000}, }; =20 +static const struct reg_default tegra264_amx_reg_defaults[] =3D { + { TEGRA210_AMX_RX_INT_MASK, 0x0000000f}, + { TEGRA210_AMX_RX1_CIF_CTRL, 0x00003800}, + { TEGRA210_AMX_RX2_CIF_CTRL, 0x00003800}, + { TEGRA210_AMX_RX3_CIF_CTRL, 0x00003800}, + { TEGRA210_AMX_RX4_CIF_CTRL, 0x00003800}, + { TEGRA210_AMX_TX_INT_MASK, 0x00000001}, + { TEGRA210_AMX_TX_CIF_CTRL, 0x00003800}, + { TEGRA210_AMX_CG, 0x1}, + { TEGRA264_AMX_CFG_RAM_CTRL, 0x00004000}, +}; + static void tegra210_amx_write_map_ram(struct tegra210_amx *amx) { int i; =20 - regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL, + regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL + amx->soc_data->reg_= offset, TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN | TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN | TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE); =20 - for (i =3D 0; i < TEGRA210_AMX_RAM_DEPTH; i++) - regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA, + for (i =3D 0; i < amx->soc_data->ram_depth; i++) + regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA + amx->soc_data->reg= _offset, amx->map[i]); =20 - regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN0, amx->byte_mask[0]); - regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN1, amx->byte_mask[1]); + for (i =3D 0; i < amx->soc_data->byte_mask_size; i++) + regmap_write(amx->regmap, + TEGRA210_AMX_OUT_BYTE_EN0 + (i * TEGRA210_AMX_AUDIOCIF_CH_STRIDE), + amx->byte_mask[i]); } =20 static int tegra210_amx_startup(struct snd_pcm_substream *substream, @@ -157,7 +171,10 @@ static int tegra210_amx_set_audio_cif(struct snd_soc_d= ai *dai, cif_conf.audio_bits =3D audio_bits; cif_conf.client_bits =3D audio_bits; =20 - tegra_set_cif(amx->regmap, reg, &cif_conf); + if (amx->soc_data->max_ch =3D=3D TEGRA264_AMX_MAX_CHANNEL) + tegra264_set_cif(amx->regmap, reg, &cif_conf); + else + tegra_set_cif(amx->regmap, reg, &cif_conf); =20 return 0; } @@ -170,9 +187,10 @@ static int tegra210_amx_in_hw_params(struct snd_pcm_su= bstream *substream, =20 if (amx->soc_data->auto_disable) { regmap_write(amx->regmap, - AMX_CH_REG(dai->id, TEGRA194_AMX_RX1_FRAME_PERIOD), + AMX_CH_REG(dai->id, TEGRA194_AMX_RX1_FRAME_PERIOD + + amx->soc_data->reg_offset), TEGRA194_MAX_FRAME_IDLE_COUNT); - regmap_write(amx->regmap, TEGRA210_AMX_CYA, 1); + regmap_write(amx->regmap, TEGRA210_AMX_CYA + amx->soc_data->reg_offset, = 1); } =20 return tegra210_amx_set_audio_cif(dai, params, @@ -194,14 +212,11 @@ static int tegra210_amx_get_byte_map(struct snd_kcont= rol *kcontrol, struct soc_mixer_control *mc =3D (struct soc_mixer_control *)kcontrol->private_value; struct tegra210_amx *amx =3D snd_soc_component_get_drvdata(cmpnt); - unsigned char *bytes_map =3D (unsigned char *)&amx->map; + unsigned char *bytes_map =3D (unsigned char *)amx->map; int reg =3D mc->reg; int enabled; =20 - if (reg > 31) - enabled =3D amx->byte_mask[1] & (1 << (reg - 32)); - else - enabled =3D amx->byte_mask[0] & (1 << reg); + enabled =3D amx->byte_mask[reg / 32] & (1 << (reg % 32)); =20 /* * TODO: Simplify this logic to just return from bytes_map[] @@ -228,7 +243,7 @@ static int tegra210_amx_put_byte_map(struct snd_kcontro= l *kcontrol, (struct soc_mixer_control *)kcontrol->private_value; struct snd_soc_component *cmpnt =3D snd_soc_kcontrol_component(kcontrol); struct tegra210_amx *amx =3D snd_soc_component_get_drvdata(cmpnt); - unsigned char *bytes_map =3D (unsigned char *)&amx->map; + unsigned char *bytes_map =3D (unsigned char *)amx->map; int reg =3D mc->reg; int value =3D ucontrol->value.integer.value[0]; unsigned int mask_val =3D amx->byte_mask[reg / 32]; @@ -418,7 +433,90 @@ static struct snd_kcontrol_new tegra210_amx_controls[]= =3D { TEGRA210_AMX_BYTE_MAP_CTRL(63), }; =20 +static struct snd_kcontrol_new tegra264_amx_controls[] =3D { + TEGRA210_AMX_BYTE_MAP_CTRL(64), + TEGRA210_AMX_BYTE_MAP_CTRL(65), + TEGRA210_AMX_BYTE_MAP_CTRL(66), + TEGRA210_AMX_BYTE_MAP_CTRL(67), + TEGRA210_AMX_BYTE_MAP_CTRL(68), + TEGRA210_AMX_BYTE_MAP_CTRL(69), + TEGRA210_AMX_BYTE_MAP_CTRL(70), + TEGRA210_AMX_BYTE_MAP_CTRL(71), + TEGRA210_AMX_BYTE_MAP_CTRL(72), + TEGRA210_AMX_BYTE_MAP_CTRL(73), + TEGRA210_AMX_BYTE_MAP_CTRL(74), + TEGRA210_AMX_BYTE_MAP_CTRL(75), + TEGRA210_AMX_BYTE_MAP_CTRL(76), + TEGRA210_AMX_BYTE_MAP_CTRL(77), + TEGRA210_AMX_BYTE_MAP_CTRL(78), + TEGRA210_AMX_BYTE_MAP_CTRL(79), + TEGRA210_AMX_BYTE_MAP_CTRL(80), + TEGRA210_AMX_BYTE_MAP_CTRL(81), + TEGRA210_AMX_BYTE_MAP_CTRL(82), + TEGRA210_AMX_BYTE_MAP_CTRL(83), + TEGRA210_AMX_BYTE_MAP_CTRL(84), + TEGRA210_AMX_BYTE_MAP_CTRL(85), + TEGRA210_AMX_BYTE_MAP_CTRL(86), + TEGRA210_AMX_BYTE_MAP_CTRL(87), + TEGRA210_AMX_BYTE_MAP_CTRL(88), + TEGRA210_AMX_BYTE_MAP_CTRL(89), + TEGRA210_AMX_BYTE_MAP_CTRL(90), + TEGRA210_AMX_BYTE_MAP_CTRL(91), + TEGRA210_AMX_BYTE_MAP_CTRL(92), + TEGRA210_AMX_BYTE_MAP_CTRL(93), + TEGRA210_AMX_BYTE_MAP_CTRL(94), + TEGRA210_AMX_BYTE_MAP_CTRL(95), + TEGRA210_AMX_BYTE_MAP_CTRL(96), + TEGRA210_AMX_BYTE_MAP_CTRL(97), + TEGRA210_AMX_BYTE_MAP_CTRL(98), + TEGRA210_AMX_BYTE_MAP_CTRL(99), + TEGRA210_AMX_BYTE_MAP_CTRL(100), + TEGRA210_AMX_BYTE_MAP_CTRL(101), + TEGRA210_AMX_BYTE_MAP_CTRL(102), + TEGRA210_AMX_BYTE_MAP_CTRL(103), + TEGRA210_AMX_BYTE_MAP_CTRL(104), + TEGRA210_AMX_BYTE_MAP_CTRL(105), + TEGRA210_AMX_BYTE_MAP_CTRL(106), + TEGRA210_AMX_BYTE_MAP_CTRL(107), + TEGRA210_AMX_BYTE_MAP_CTRL(108), + TEGRA210_AMX_BYTE_MAP_CTRL(109), + TEGRA210_AMX_BYTE_MAP_CTRL(110), + TEGRA210_AMX_BYTE_MAP_CTRL(111), + TEGRA210_AMX_BYTE_MAP_CTRL(112), + TEGRA210_AMX_BYTE_MAP_CTRL(113), + TEGRA210_AMX_BYTE_MAP_CTRL(114), + TEGRA210_AMX_BYTE_MAP_CTRL(115), + TEGRA210_AMX_BYTE_MAP_CTRL(116), + TEGRA210_AMX_BYTE_MAP_CTRL(117), + TEGRA210_AMX_BYTE_MAP_CTRL(118), + TEGRA210_AMX_BYTE_MAP_CTRL(119), + TEGRA210_AMX_BYTE_MAP_CTRL(120), + TEGRA210_AMX_BYTE_MAP_CTRL(121), + TEGRA210_AMX_BYTE_MAP_CTRL(122), + TEGRA210_AMX_BYTE_MAP_CTRL(123), + TEGRA210_AMX_BYTE_MAP_CTRL(124), + TEGRA210_AMX_BYTE_MAP_CTRL(125), + TEGRA210_AMX_BYTE_MAP_CTRL(126), + TEGRA210_AMX_BYTE_MAP_CTRL(127), +}; + +static int tegra210_amx_component_probe(struct snd_soc_component *componen= t) +{ + struct tegra210_amx *amx =3D snd_soc_component_get_drvdata(component); + int err =3D 0; + + if (amx->soc_data->num_controls) { + err =3D snd_soc_add_component_controls(component, amx->soc_data->control= s, + amx->soc_data->num_controls); + if (err) + dev_err(component->dev, "can't add AMX controls, err: %d\n", err); + } + + return err; +} + static const struct snd_soc_component_driver tegra210_amx_cmpnt =3D { + .probe =3D tegra210_amx_component_probe, .dapm_widgets =3D tegra210_amx_widgets, .num_dapm_widgets =3D ARRAY_SIZE(tegra210_amx_widgets), .dapm_routes =3D tegra210_amx_routes, @@ -450,6 +548,22 @@ static bool tegra194_amx_wr_reg(struct device *dev, un= signed int reg) } } =20 +static bool tegra264_amx_wr_reg(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case TEGRA210_AMX_RX_INT_MASK ... TEGRA210_AMX_RX4_CIF_CTRL: + case TEGRA210_AMX_TX_INT_MASK ... TEGRA210_AMX_TX_CIF_CTRL: + case TEGRA210_AMX_ENABLE ... TEGRA210_AMX_CG: + case TEGRA210_AMX_CTRL ... TEGRA264_AMX_STREAMS_AUTO_DISABLE: + case TEGRA264_AMX_CFG_RAM_CTRL ... TEGRA264_AMX_CFG_RAM_DATA: + case TEGRA264_AMX_RX1_FRAME_PERIOD ... TEGRA264_AMX_RX4_FRAME_PERIOD: + return true; + default: + return false; + } +} + static bool tegra210_amx_rd_reg(struct device *dev, unsigned int reg) { switch (reg) { @@ -470,6 +584,21 @@ static bool tegra194_amx_rd_reg(struct device *dev, un= signed int reg) } } =20 +static bool tegra264_amx_rd_reg(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case TEGRA210_AMX_RX_STATUS ... TEGRA210_AMX_RX4_CIF_CTRL: + case TEGRA210_AMX_TX_STATUS ... TEGRA210_AMX_TX_CIF_CTRL: + case TEGRA210_AMX_ENABLE ... TEGRA210_AMX_INT_STATUS: + case TEGRA210_AMX_CTRL ... TEGRA264_AMX_CFG_RAM_DATA: + case TEGRA264_AMX_RX1_FRAME_PERIOD ... TEGRA264_AMX_RX4_FRAME_PERIOD: + return true; + default: + return false; + } +} + static bool tegra210_amx_volatile_reg(struct device *dev, unsigned int reg) { switch (reg) { @@ -492,6 +621,29 @@ static bool tegra210_amx_volatile_reg(struct device *d= ev, unsigned int reg) return false; } =20 +static bool tegra264_amx_volatile_reg(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case TEGRA210_AMX_RX_STATUS: + case TEGRA210_AMX_RX_INT_STATUS: + case TEGRA210_AMX_RX_INT_SET: + case TEGRA210_AMX_TX_STATUS: + case TEGRA210_AMX_TX_INT_STATUS: + case TEGRA210_AMX_TX_INT_SET: + case TEGRA210_AMX_SOFT_RESET: + case TEGRA210_AMX_STATUS: + case TEGRA210_AMX_INT_STATUS: + case TEGRA264_AMX_CFG_RAM_CTRL: + case TEGRA264_AMX_CFG_RAM_DATA: + return true; + default: + break; + } + + return false; +} + static const struct regmap_config tegra210_amx_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -518,18 +670,51 @@ static const struct regmap_config tegra194_amx_regmap= _config =3D { .cache_type =3D REGCACHE_FLAT, }; =20 +static const struct regmap_config tegra264_amx_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D TEGRA264_AMX_RX4_LAST_FRAME_PERIOD, + .writeable_reg =3D tegra264_amx_wr_reg, + .readable_reg =3D tegra264_amx_rd_reg, + .volatile_reg =3D tegra264_amx_volatile_reg, + .reg_defaults =3D tegra264_amx_reg_defaults, + .num_reg_defaults =3D ARRAY_SIZE(tegra264_amx_reg_defaults), + .cache_type =3D REGCACHE_FLAT, +}; + static const struct tegra210_amx_soc_data soc_data_tegra210 =3D { .regmap_conf =3D &tegra210_amx_regmap_config, + .max_ch =3D TEGRA210_AMX_MAX_CHANNEL, + .ram_depth =3D TEGRA210_AMX_RAM_DEPTH, + .byte_mask_size =3D TEGRA210_AMX_BYTE_MASK_COUNT, + .reg_offset =3D TEGRA210_AMX_AUTO_DISABLE_OFFSET, }; =20 static const struct tegra210_amx_soc_data soc_data_tegra194 =3D { .regmap_conf =3D &tegra194_amx_regmap_config, .auto_disable =3D true, + .max_ch =3D TEGRA210_AMX_MAX_CHANNEL, + .ram_depth =3D TEGRA210_AMX_RAM_DEPTH, + .byte_mask_size =3D TEGRA210_AMX_BYTE_MASK_COUNT, + .reg_offset =3D TEGRA210_AMX_AUTO_DISABLE_OFFSET, +}; + +static const struct tegra210_amx_soc_data soc_data_tegra264 =3D { + .regmap_conf =3D &tegra264_amx_regmap_config, + .auto_disable =3D true, + .max_ch =3D TEGRA264_AMX_MAX_CHANNEL, + .ram_depth =3D TEGRA264_AMX_RAM_DEPTH, + .byte_mask_size =3D TEGRA264_AMX_BYTE_MASK_COUNT, + .reg_offset =3D TEGRA264_AMX_AUTO_DISABLE_OFFSET, + .controls =3D tegra264_amx_controls, + .num_controls =3D ARRAY_SIZE(tegra264_amx_controls), }; =20 static const struct of_device_id tegra210_amx_of_match[] =3D { { .compatible =3D "nvidia,tegra210-amx", .data =3D &soc_data_tegra210 }, { .compatible =3D "nvidia,tegra194-amx", .data =3D &soc_data_tegra194 }, + { .compatible =3D "nvidia,tegra264-amx", .data =3D &soc_data_tegra264 }, {}, }; MODULE_DEVICE_TABLE(of, tegra210_amx_of_match); @@ -562,6 +747,20 @@ static int tegra210_amx_platform_probe(struct platform= _device *pdev) =20 regcache_cache_only(amx->regmap, true); =20 + amx->map =3D devm_kzalloc(dev, amx->soc_data->ram_depth * sizeof(*amx->ma= p), + GFP_KERNEL); + if (!amx->map) + return -ENOMEM; + + amx->byte_mask =3D devm_kzalloc(dev, + amx->soc_data->byte_mask_size * sizeof(*amx->byte_mask), + GFP_KERNEL); + if (!amx->byte_mask) + return -ENOMEM; + + tegra210_amx_dais[TEGRA_AMX_OUT_DAI_ID].capture.channels_max =3D + amx->soc_data->max_ch; + err =3D devm_snd_soc_register_component(dev, &tegra210_amx_cmpnt, tegra210_amx_dais, ARRAY_SIZE(tegra210_amx_dais)); diff --git a/sound/soc/tegra/tegra210_amx.h b/sound/soc/tegra/tegra210_amx.h index e277741e4258..50a237b197ba 100644 --- a/sound/soc/tegra/tegra210_amx.h +++ b/sound/soc/tegra/tegra210_amx.h @@ -1,8 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * tegra210_amx.h - Definitions for Tegra210 AMX driver +/* SPDX-License-Identifier: GPL-2.0-only + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION. All= rights reserved. * - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * tegra210_amx.h - Definitions for Tegra210 AMX driver * */ =20 @@ -32,7 +31,6 @@ #define TEGRA210_AMX_INT_STATUS 0x90 #define TEGRA210_AMX_CTRL 0xa4 #define TEGRA210_AMX_OUT_BYTE_EN0 0xa8 -#define TEGRA210_AMX_OUT_BYTE_EN1 0xac #define TEGRA210_AMX_CYA 0xb0 #define TEGRA210_AMX_CFG_RAM_CTRL 0xb8 #define TEGRA210_AMX_CFG_RAM_DATA 0xbc @@ -41,6 +39,13 @@ #define TEGRA194_AMX_RX4_FRAME_PERIOD 0xcc #define TEGRA194_AMX_RX4_LAST_FRAME_PERIOD 0xdc =20 +#define TEGRA264_AMX_STREAMS_AUTO_DISABLE 0xb8 +#define TEGRA264_AMX_CFG_RAM_CTRL 0xc0 +#define TEGRA264_AMX_CFG_RAM_DATA 0xc4 +#define TEGRA264_AMX_RX1_FRAME_PERIOD 0xc8 +#define TEGRA264_AMX_RX4_FRAME_PERIOD 0xd4 +#define TEGRA264_AMX_RX4_LAST_FRAME_PERIOD 0xe4 + /* Fields in TEGRA210_AMX_ENABLE */ #define TEGRA210_AMX_ENABLE_SHIFT 0 =20 @@ -72,6 +77,15 @@ #define TEGRA210_AMX_MAP_STREAM_NUM_SHIFT 6 #define TEGRA210_AMX_MAP_WORD_NUM_SHIFT 2 #define TEGRA210_AMX_MAP_BYTE_NUM_SHIFT 0 +#define TEGRA210_AMX_BYTE_MASK_COUNT 2 +#define TEGRA210_AMX_MAX_CHANNEL 16 +#define TEGRA210_AMX_AUTO_DISABLE_OFFSET 0 + +#define TEGRA264_AMX_RAM_DEPTH 32 +#define TEGRA264_AMX_BYTE_MASK_COUNT 4 +#define TEGRA264_AMX_MAX_CHANNEL 32 +#define TEGRA264_AMX_AUTO_DISABLE_OFFSET 8 +#define TEGRA_AMX_OUT_DAI_ID 4 =20 enum { TEGRA210_AMX_WAIT_ON_ALL, @@ -81,13 +95,19 @@ enum { struct tegra210_amx_soc_data { const struct regmap_config *regmap_conf; bool auto_disable; + const struct snd_kcontrol_new *controls; + unsigned int num_controls; + unsigned int max_ch; + unsigned int ram_depth; + unsigned int byte_mask_size; + unsigned int reg_offset; }; =20 struct tegra210_amx { const struct tegra210_amx_soc_data *soc_data; - unsigned int map[TEGRA210_AMX_RAM_DEPTH]; + unsigned int *map; + unsigned int *byte_mask; struct regmap *regmap; - unsigned int byte_mask[2]; }; =20 #endif --=20 2.17.1