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Mon, 28 Apr 2025 22:59:49 -0700 From: "Sheetal ." To: , , , , CC: , , , , , , , , , , Sheetal Subject: [PATCH v2 09/11] ASoC: tegra: ADX: Add Tegra264 support Date: Tue, 29 Apr 2025 05:59:39 +0000 Message-ID: <20250429055941.901511-10-sheetal@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250429055941.901511-1-sheetal@nvidia.com> References: <20250429055941.901511-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004684:EE_|SA0PR12MB7002:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d94ab58-c3e5-43ff-ec3d-08dd86e3195d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?fGkGiOrs5GOq7bDXi3sFnSwvKXY6jTD0txBcRguujOR0OSOCAWNRit5D7aHK?= =?us-ascii?Q?++ShaVekhbnFxZZ2dsPjNEIUPG2/ge3hzLEwpMbl3LnDrzWo0sCCo1L+/3SA?= =?us-ascii?Q?XSNSY/GOL0ACd4R9ynVIBAM0sZbe3KjW4m87kTYg+A0GXxy+cInEipJACA5q?= =?us-ascii?Q?xTnqOhTpzvfDwa9eoBqgWrMyqH9/gqRmsUgetHHl2ColLr5PPga/HrGVER+l?= =?us-ascii?Q?cDnb0x9KrHUSthtzuT3gEuYR30ZWhqG6aLzitypl4Es9W2LI+e7w9bVCwTal?= =?us-ascii?Q?PwqdW9p4DBvlZygLtkVezq5csJ4BWfd+Vi/wk0XaltOAGGn1dUrgpmagHDj6?= =?us-ascii?Q?sD3keBjLRsWb7/GXkUqPMt527WyPxK4HydyKE7dSTjJLgI/x9hcn5sQoFG/G?= =?us-ascii?Q?ic/pr2wxkwfduBm7FUdzl60fcDMuSq/th615pzpLa0nsFyA82Fs7hFkA8Fh0?= =?us-ascii?Q?Y4VNEfXzMoxsl5YYnys8zfFq3xtUQJZ1MfmoGpvGQ5w+9sV9LBXFCDf0QdCy?= =?us-ascii?Q?lu9yUiZ73VKA4mRgJi8R83i1PYiTilPPNzbq7Ae8wTuPndENzzJv5/qOV8Ot?= =?us-ascii?Q?wTJH6zsxk2XhR2UOB47SEcKGpS0zH6vfBg/jnJ16m1+PUd9iRBzUIHJvJ1vH?= =?us-ascii?Q?o96FwOjh7zaxUgmI2Esgi9p0cFZ8ZFYbU/5zfmkNigCJE93WYHH0Vu+eakmz?= =?us-ascii?Q?G4sJUhBwwB0CRpv57u7hEeUPb15mRwRTMUpy1zkjXkcNcRd62DTq350JevBL?= =?us-ascii?Q?oWEPBb7ksuyFH6TQXoQr2zrGTOCl5Nd6INT9QvG4WFmL8I0YEdiQ8xP0pBI5?= =?us-ascii?Q?F0bPjCvjVNQoBDsIOmg2DTG48LdpXVrcY/fH/mD7BYa3pJtP3//nNClKAdYK?= =?us-ascii?Q?ozRTbNy/SthY5eL0eA2e9tdE/myY8Ph5ZBjkYqqGZDoXrxNv+hhrts68mPBr?= =?us-ascii?Q?KmSN64EiS9qhTKgXFjrpe2MpITwUYm2IQm5G+pyToenbdALj5BUDGeiuVLUK?= =?us-ascii?Q?LWW/nfuhnuxq4vfqZg1NXWhDho/7J8CYMXjZegwhY3bK4igy4bRuMNYcAAW3?= =?us-ascii?Q?EBYMte59sOgetLkPZ7seiuzzZ3kLcO0T2xTIl3x0ACznmhPClVhGOECvok4B?= =?us-ascii?Q?0FVrIWUnLKscz2itVDo8aBaXCr+Ny5RcaST8Kxsh2nrsD5r1cWgghnhYYxPR?= =?us-ascii?Q?3slF7MOBhQdfLzxXOaDZF4k8wMiZYQ8fRmMgDrC4jsSJ5y4rcyTLc5IxDrd/?= =?us-ascii?Q?oCXsWM1rI7DkFzHAWWxqG51mcSPUmIAeT+Kzfvrrp9Wx2PqTmK0Ke7KkteO4?= =?us-ascii?Q?q8K2WykD6lODtzki16AvvXpG+4EqnUuRxNOCE071IB2DR/TyhDWlIhh1S94h?= =?us-ascii?Q?4u2gE5NAHK+e0QWlQezi3XmrfN5gNybutzPfxSuQBYfxcKFbkgpBKRQJq4ht?= =?us-ascii?Q?/PbZmxUcZLEqYB0mX968k0lISlmoecUl7QS11Xvj2DMvghmGmsPT75L5BNvm?= =?us-ascii?Q?22I0iJzPbX8SdgYpcjpa+IJRMj1jcgJ4F0D6?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2025 06:00:09.5775 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d94ab58-c3e5-43ff-ec3d-08dd86e3195d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004684.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sheetal Add Tegra264 ADX support with following changes: - Add soc_data for Tegra264-specific variations - Tegra264 ADX supports 32 input channels, hence update the playback DAI channels_max parameter and CIF configuration API. - Register offsets and default values are updated to align with Tegra264. - Add 128 byte map controls for Tegra264 to accommodate each byte per channel (32channels x 32bits). Signed-off-by: Sheetal --- sound/soc/tegra/tegra210_adx.c | 229 +++++++++++++++++++++++++++++++-- sound/soc/tegra/tegra210_adx.h | 36 +++++- 2 files changed, 248 insertions(+), 17 deletions(-) diff --git a/sound/soc/tegra/tegra210_adx.c b/sound/soc/tegra/tegra210_adx.c index b6c798baedea..ad7cd8655047 100644 --- a/sound/soc/tegra/tegra210_adx.c +++ b/sound/soc/tegra/tegra210_adx.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -32,21 +33,37 @@ static const struct reg_default tegra210_adx_reg_defaul= ts[] =3D { { TEGRA210_ADX_CFG_RAM_CTRL, 0x00004000}, }; =20 +static const struct reg_default tegra264_adx_reg_defaults[] =3D { + { TEGRA210_ADX_RX_INT_MASK, 0x00000001}, + { TEGRA210_ADX_RX_CIF_CTRL, 0x00003800}, + { TEGRA210_ADX_TX_INT_MASK, 0x0000000f }, + { TEGRA210_ADX_TX1_CIF_CTRL, 0x00003800}, + { TEGRA210_ADX_TX2_CIF_CTRL, 0x00003800}, + { TEGRA210_ADX_TX3_CIF_CTRL, 0x00003800}, + { TEGRA210_ADX_TX4_CIF_CTRL, 0x00003800}, + { TEGRA210_ADX_CG, 0x1}, + { TEGRA264_ADX_CFG_RAM_CTRL, 0x00004000}, +}; + static void tegra210_adx_write_map_ram(struct tegra210_adx *adx) { int i; =20 - regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL, + regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL + + adx->soc_data->cya_offset, TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN | TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN | TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE); =20 - for (i =3D 0; i < TEGRA210_ADX_RAM_DEPTH; i++) - regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_DATA, + for (i =3D 0; i < adx->soc_data->ram_depth; i++) + regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_DATA + + adx->soc_data->cya_offset, adx->map[i]); =20 - regmap_write(adx->regmap, TEGRA210_ADX_IN_BYTE_EN0, adx->byte_mask[0]); - regmap_write(adx->regmap, TEGRA210_ADX_IN_BYTE_EN1, adx->byte_mask[1]); + for (i =3D 0; i < adx->soc_data->byte_mask_size; i++) + regmap_write(adx->regmap, + TEGRA210_ADX_IN_BYTE_EN0 + (i * TEGRA210_ADX_AUDIOCIF_CH_STRIDE), + adx->byte_mask[i]); } =20 static int tegra210_adx_startup(struct snd_pcm_substream *substream, @@ -117,7 +134,7 @@ static int tegra210_adx_set_audio_cif(struct snd_soc_da= i *dai, =20 memset(&cif_conf, 0, sizeof(struct tegra_cif_conf)); =20 - if (channels < 1 || channels > 16) + if (channels < 1 || channels > adx->soc_data->max_ch) return -EINVAL; =20 switch (format) { @@ -140,7 +157,10 @@ static int tegra210_adx_set_audio_cif(struct snd_soc_d= ai *dai, cif_conf.audio_bits =3D audio_bits; cif_conf.client_bits =3D audio_bits; =20 - tegra_set_cif(adx->regmap, reg, &cif_conf); + if (adx->soc_data->max_ch =3D=3D 32) + tegra264_set_cif(adx->regmap, reg, &cif_conf); + else + tegra_set_cif(adx->regmap, reg, &cif_conf); =20 return 0; } @@ -169,7 +189,7 @@ static int tegra210_adx_get_byte_map(struct snd_kcontro= l *kcontrol, struct snd_soc_component *cmpnt =3D snd_soc_kcontrol_component(kcontrol); struct tegra210_adx *adx =3D snd_soc_component_get_drvdata(cmpnt); struct soc_mixer_control *mc; - unsigned char *bytes_map =3D (unsigned char *)&adx->map; + unsigned char *bytes_map =3D (unsigned char *)adx->map; int enabled; =20 mc =3D (struct soc_mixer_control *)kcontrol->private_value; @@ -198,7 +218,7 @@ static int tegra210_adx_put_byte_map(struct snd_kcontro= l *kcontrol, { struct snd_soc_component *cmpnt =3D snd_soc_kcontrol_component(kcontrol); struct tegra210_adx *adx =3D snd_soc_component_get_drvdata(cmpnt); - unsigned char *bytes_map =3D (unsigned char *)&adx->map; + unsigned char *bytes_map =3D (unsigned char *)adx->map; int value =3D ucontrol->value.integer.value[0]; struct soc_mixer_control *mc =3D (struct soc_mixer_control *)kcontrol->private_value; @@ -402,7 +422,90 @@ static struct snd_kcontrol_new tegra210_adx_controls[]= =3D { TEGRA210_ADX_BYTE_MAP_CTRL(63), }; =20 +static struct snd_kcontrol_new tegra264_adx_controls[] =3D { + TEGRA210_ADX_BYTE_MAP_CTRL(64), + TEGRA210_ADX_BYTE_MAP_CTRL(65), + TEGRA210_ADX_BYTE_MAP_CTRL(66), + TEGRA210_ADX_BYTE_MAP_CTRL(67), + TEGRA210_ADX_BYTE_MAP_CTRL(68), + TEGRA210_ADX_BYTE_MAP_CTRL(69), + TEGRA210_ADX_BYTE_MAP_CTRL(70), + TEGRA210_ADX_BYTE_MAP_CTRL(71), + TEGRA210_ADX_BYTE_MAP_CTRL(72), + TEGRA210_ADX_BYTE_MAP_CTRL(73), + TEGRA210_ADX_BYTE_MAP_CTRL(74), + TEGRA210_ADX_BYTE_MAP_CTRL(75), + TEGRA210_ADX_BYTE_MAP_CTRL(76), + TEGRA210_ADX_BYTE_MAP_CTRL(77), + TEGRA210_ADX_BYTE_MAP_CTRL(78), + TEGRA210_ADX_BYTE_MAP_CTRL(79), + TEGRA210_ADX_BYTE_MAP_CTRL(80), + TEGRA210_ADX_BYTE_MAP_CTRL(81), + TEGRA210_ADX_BYTE_MAP_CTRL(82), + TEGRA210_ADX_BYTE_MAP_CTRL(83), + TEGRA210_ADX_BYTE_MAP_CTRL(84), + TEGRA210_ADX_BYTE_MAP_CTRL(85), + TEGRA210_ADX_BYTE_MAP_CTRL(86), + TEGRA210_ADX_BYTE_MAP_CTRL(87), + TEGRA210_ADX_BYTE_MAP_CTRL(88), + TEGRA210_ADX_BYTE_MAP_CTRL(89), + TEGRA210_ADX_BYTE_MAP_CTRL(90), + TEGRA210_ADX_BYTE_MAP_CTRL(91), + TEGRA210_ADX_BYTE_MAP_CTRL(92), + TEGRA210_ADX_BYTE_MAP_CTRL(93), + TEGRA210_ADX_BYTE_MAP_CTRL(94), + TEGRA210_ADX_BYTE_MAP_CTRL(95), + TEGRA210_ADX_BYTE_MAP_CTRL(96), + TEGRA210_ADX_BYTE_MAP_CTRL(97), + TEGRA210_ADX_BYTE_MAP_CTRL(98), + TEGRA210_ADX_BYTE_MAP_CTRL(99), + TEGRA210_ADX_BYTE_MAP_CTRL(100), + TEGRA210_ADX_BYTE_MAP_CTRL(101), + TEGRA210_ADX_BYTE_MAP_CTRL(102), + TEGRA210_ADX_BYTE_MAP_CTRL(103), + TEGRA210_ADX_BYTE_MAP_CTRL(104), + TEGRA210_ADX_BYTE_MAP_CTRL(105), + TEGRA210_ADX_BYTE_MAP_CTRL(106), + TEGRA210_ADX_BYTE_MAP_CTRL(107), + TEGRA210_ADX_BYTE_MAP_CTRL(108), + TEGRA210_ADX_BYTE_MAP_CTRL(109), + TEGRA210_ADX_BYTE_MAP_CTRL(110), + TEGRA210_ADX_BYTE_MAP_CTRL(111), + TEGRA210_ADX_BYTE_MAP_CTRL(112), + TEGRA210_ADX_BYTE_MAP_CTRL(113), + TEGRA210_ADX_BYTE_MAP_CTRL(114), + TEGRA210_ADX_BYTE_MAP_CTRL(115), + TEGRA210_ADX_BYTE_MAP_CTRL(116), + TEGRA210_ADX_BYTE_MAP_CTRL(117), + TEGRA210_ADX_BYTE_MAP_CTRL(118), + TEGRA210_ADX_BYTE_MAP_CTRL(119), + TEGRA210_ADX_BYTE_MAP_CTRL(120), + TEGRA210_ADX_BYTE_MAP_CTRL(121), + TEGRA210_ADX_BYTE_MAP_CTRL(122), + TEGRA210_ADX_BYTE_MAP_CTRL(123), + TEGRA210_ADX_BYTE_MAP_CTRL(124), + TEGRA210_ADX_BYTE_MAP_CTRL(125), + TEGRA210_ADX_BYTE_MAP_CTRL(126), + TEGRA210_ADX_BYTE_MAP_CTRL(127), +}; + +static int tegra210_adx_component_probe(struct snd_soc_component *componen= t) +{ + struct tegra210_adx *adx =3D snd_soc_component_get_drvdata(component); + int err =3D 0; + + if (adx->soc_data->num_controls) { + err =3D snd_soc_add_component_controls(component, adx->soc_data->control= s, + adx->soc_data->num_controls); + if (err) + dev_err(component->dev, "can't add ADX controls, err: %d\n", err); + } + + return err; +} + static const struct snd_soc_component_driver tegra210_adx_cmpnt =3D { + .probe =3D tegra210_adx_component_probe, .dapm_widgets =3D tegra210_adx_widgets, .num_dapm_widgets =3D ARRAY_SIZE(tegra210_adx_widgets), .dapm_routes =3D tegra210_adx_routes, @@ -460,6 +563,58 @@ static bool tegra210_adx_volatile_reg(struct device *d= ev, return false; } =20 +static bool tegra264_adx_wr_reg(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case TEGRA210_ADX_TX_INT_MASK ... TEGRA210_ADX_TX4_CIF_CTRL: + case TEGRA210_ADX_RX_INT_MASK ... TEGRA210_ADX_RX_CIF_CTRL: + case TEGRA210_ADX_ENABLE ... TEGRA210_ADX_CG: + case TEGRA210_ADX_CTRL ... TEGRA264_ADX_CYA: + case TEGRA264_ADX_CFG_RAM_CTRL ... TEGRA264_ADX_CFG_RAM_DATA: + return true; + default: + return false; + } +} + +static bool tegra264_adx_rd_reg(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case TEGRA210_ADX_RX_STATUS ... TEGRA210_ADX_RX_CIF_CTRL: + case TEGRA210_ADX_TX_STATUS ... TEGRA210_ADX_TX4_CIF_CTRL: + case TEGRA210_ADX_ENABLE ... TEGRA210_ADX_INT_STATUS: + case TEGRA210_ADX_CTRL ... TEGRA264_ADX_CFG_RAM_DATA: + return true; + default: + return false; + } +} + +static bool tegra264_adx_volatile_reg(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case TEGRA210_ADX_RX_STATUS: + case TEGRA210_ADX_RX_INT_STATUS: + case TEGRA210_ADX_RX_INT_SET: + case TEGRA210_ADX_TX_STATUS: + case TEGRA210_ADX_TX_INT_STATUS: + case TEGRA210_ADX_TX_INT_SET: + case TEGRA210_ADX_SOFT_RESET: + case TEGRA210_ADX_STATUS: + case TEGRA210_ADX_INT_STATUS: + case TEGRA264_ADX_CFG_RAM_CTRL: + case TEGRA264_ADX_CFG_RAM_DATA: + return true; + default: + break; + } + + return false; +} + static const struct regmap_config tegra210_adx_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -473,8 +628,40 @@ static const struct regmap_config tegra210_adx_regmap_= config =3D { .cache_type =3D REGCACHE_FLAT, }; =20 +static const struct regmap_config tegra264_adx_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D TEGRA264_ADX_CFG_RAM_DATA, + .writeable_reg =3D tegra264_adx_wr_reg, + .readable_reg =3D tegra264_adx_rd_reg, + .volatile_reg =3D tegra264_adx_volatile_reg, + .reg_defaults =3D tegra264_adx_reg_defaults, + .num_reg_defaults =3D ARRAY_SIZE(tegra264_adx_reg_defaults), + .cache_type =3D REGCACHE_FLAT, +}; + +static const struct tegra210_adx_soc_data soc_data_tegra210 =3D { + .regmap_conf =3D &tegra210_adx_regmap_config, + .max_ch =3D TEGRA210_ADX_MAX_CHANNEL, + .ram_depth =3D TEGRA210_ADX_RAM_DEPTH, + .byte_mask_size =3D TEGRA210_ADX_BYTE_MASK_COUNT, + .cya_offset =3D TEGRA210_ADX_CYA_OFFSET, +}; + +static const struct tegra210_adx_soc_data soc_data_tegra264 =3D { + .regmap_conf =3D &tegra264_adx_regmap_config, + .max_ch =3D TEGRA264_ADX_MAX_CHANNEL, + .ram_depth =3D TEGRA264_ADX_RAM_DEPTH, + .byte_mask_size =3D TEGRA264_ADX_BYTE_MASK_COUNT, + .cya_offset =3D TEGRA264_ADX_CYA_OFFSET, + .controls =3D tegra264_adx_controls, + .num_controls =3D ARRAY_SIZE(tegra264_adx_controls), +}; + static const struct of_device_id tegra210_adx_of_match[] =3D { - { .compatible =3D "nvidia,tegra210-adx" }, + { .compatible =3D "nvidia,tegra210-adx", .data =3D &soc_data_tegra210 }, + { .compatible =3D "nvidia,tegra264-adx", .data =3D &soc_data_tegra264 }, {}, }; MODULE_DEVICE_TABLE(of, tegra210_adx_of_match); @@ -483,6 +670,8 @@ static int tegra210_adx_platform_probe(struct platform_= device *pdev) { struct device *dev =3D &pdev->dev; struct tegra210_adx *adx; + const struct of_device_id *match; + struct tegra210_adx_soc_data *soc_data; void __iomem *regs; int err; =20 @@ -490,6 +679,10 @@ static int tegra210_adx_platform_probe(struct platform= _device *pdev) if (!adx) return -ENOMEM; =20 + match =3D of_match_device(tegra210_adx_of_match, dev); + soc_data =3D (struct tegra210_adx_soc_data *)match->data; + adx->soc_data =3D soc_data; + dev_set_drvdata(dev, adx); =20 regs =3D devm_platform_ioremap_resource(pdev, 0); @@ -497,7 +690,7 @@ static int tegra210_adx_platform_probe(struct platform_= device *pdev) return PTR_ERR(regs); =20 adx->regmap =3D devm_regmap_init_mmio(dev, regs, - &tegra210_adx_regmap_config); + soc_data->regmap_conf); if (IS_ERR(adx->regmap)) { dev_err(dev, "regmap init failed\n"); return PTR_ERR(adx->regmap); @@ -505,6 +698,20 @@ static int tegra210_adx_platform_probe(struct platform= _device *pdev) =20 regcache_cache_only(adx->regmap, true); =20 + adx->map =3D devm_kzalloc(dev, soc_data->ram_depth * sizeof(*adx->map), + GFP_KERNEL); + if (!adx->map) + return -ENOMEM; + + adx->byte_mask =3D devm_kzalloc(dev, + soc_data->byte_mask_size * sizeof(*adx->byte_mask), + GFP_KERNEL); + if (!adx->byte_mask) + return -ENOMEM; + + tegra210_adx_dais[TEGRA_ADX_IN_DAI_ID].playback.channels_max =3D + adx->soc_data->max_ch; + err =3D devm_snd_soc_register_component(dev, &tegra210_adx_cmpnt, tegra210_adx_dais, ARRAY_SIZE(tegra210_adx_dais)); diff --git a/sound/soc/tegra/tegra210_adx.h b/sound/soc/tegra/tegra210_adx.h index d7dcb6497978..176a4e40de0a 100644 --- a/sound/soc/tegra/tegra210_adx.h +++ b/sound/soc/tegra/tegra210_adx.h @@ -1,8 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * tegra210_adx.h - Definitions for Tegra210 ADX driver +/* SPDX-License-Identifier: GPL-2.0-only + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION. All= rights reserved. * - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * tegra210_adx.h - Definitions for Tegra210 ADX driver * */ =20 @@ -36,6 +35,10 @@ #define TEGRA210_ADX_CFG_RAM_CTRL 0xb8 #define TEGRA210_ADX_CFG_RAM_DATA 0xbc =20 +#define TEGRA264_ADX_CYA 0xb8 +#define TEGRA264_ADX_CFG_RAM_CTRL 0xc0 +#define TEGRA264_ADX_CFG_RAM_DATA 0xc4 + /* Fields in TEGRA210_ADX_ENABLE */ #define TEGRA210_ADX_ENABLE_SHIFT 0 =20 @@ -62,11 +65,32 @@ #define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 6 #define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2 #define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0 +#define TEGRA210_ADX_BYTE_MASK_COUNT 2 +#define TEGRA210_ADX_MAX_CHANNEL 16 +#define TEGRA210_ADX_CYA_OFFSET 0 + +#define TEGRA264_ADX_RAM_DEPTH 32 +#define TEGRA264_ADX_BYTE_MASK_COUNT 4 +#define TEGRA264_ADX_MAX_CHANNEL 32 +#define TEGRA264_ADX_CYA_OFFSET 8 + +#define TEGRA_ADX_IN_DAI_ID 4 + +struct tegra210_adx_soc_data { + const struct regmap_config *regmap_conf; + const struct snd_kcontrol_new *controls; + unsigned int num_controls; + unsigned int max_ch; + unsigned int ram_depth; + unsigned int byte_mask_size; + unsigned int cya_offset; +}; =20 struct tegra210_adx { struct regmap *regmap; - unsigned int map[TEGRA210_ADX_RAM_DEPTH]; - unsigned int byte_mask[2]; + unsigned int *map; + unsigned int *byte_mask; + const struct tegra210_adx_soc_data *soc_data; }; =20 #endif --=20 2.17.1