From nobody Fri Dec 19 00:33:14 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4736314D2A0 for ; Tue, 29 Apr 2025 05:05:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745903125; cv=none; b=eaV8sPMDpBYkgtdg9kxIpvx5fJQhcYQuodrkt9ZCQGPpk4CRr3B3g2WiMkm1NUEDS3C6lKAnwWXUOwkyYe52Wl0FAJrJavutEppZ0LeqwuGp+Aj3eNE+v7I0qS/tt9KwTDmHR5cDcnM9/p2Lhm1Tdi6O3Nogk/5vPGXoZ8E6+cs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745903125; c=relaxed/simple; bh=/nFJ5WgjPCXfN8LVYjdrRcQI3IDn0JLngTTI5cKg1OI=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=h+svS84X1vkc6uMn0wjfgsEWkmNLiR1OY3d85mzIP60skb6ALYAU3psmjfZj2Er2Dz8cMP/nUzzBKUWM5Dv1ZmIGCx9L3NzJ6rFR8T7mpDIosyuF05tLfZZfeAfDXXgZ6TqtBT07T36h2898VRrDhoDoSSqZE7A0Q9seCDvCiNA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 96D361515; Mon, 28 Apr 2025 22:05:15 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.52.122]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5F3693F5A1; Mon, 28 Apr 2025 22:05:18 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mark Rutland , Ard Biesheuvel , Ryan Roberts , linux-kernel@vger.kernel.org Subject: [PATCH V3] arm64/mm: Re-organise setting up FEAT_S1PIE registers PIRE0_EL1 and PIR_EL1 Date: Tue, 29 Apr 2025 10:35:11 +0530 Message-Id: <20250429050511.1663235-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mov_q cannot really move PIE_E[0|1] macros into a general purpose register as expected if those macro constants contain some 128 bit layout elements, that are required for D128 page tables. The primary issue is that for D128, PIE_E[0|1] are defined in terms of 128-bit types with shifting and masking, which the assembler can't accommodate. Instead pre-calculate these PIRE0_EL1/PIR_EL1 constants into asm-offsets.h based PIE_E0_ASM/PIE_E1_ASM which can then be used in arch/arm64/mm/proc.S. While here also drop PTE_MAYBE_NG/PTE_MAYBE_SHARED assembly overrides which are not required any longer, as the compiler toolchains are smart enough to compute both the PIE_[E0|E1]_ASM constants in all scenarios. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: Ard Biesheuvel Cc: Ryan Roberts Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Ryan Roberts --- This patch applies on v6.15-rc4 Changes in V3: - Dropped off macros PTE_MAYBE_NG and PTE_MAYBE_SHARED as per Ryan Changes in V2: https://lore.kernel.org/all/20250416035604.2717188-1-anshuman.khandual@arm.= com/ - Added asm-offsets.c based PIE_E0_ASM and PIE_E1_ASM symbols as per Ard - Moved PTE_MAYBE_NG and PTE_MAYBE_SHARED overrides inside asm-offsets.c along with the corresponding comment as per Ard Changes in V1: https://lore.kernel.org/linux-arm-kernel/20250410074024.1545768-1-anshuman.= khandual@arm.com/ arch/arm64/kernel/asm-offsets.c | 2 ++ arch/arm64/mm/proc.S | 19 ++----------------- 2 files changed, 4 insertions(+), 17 deletions(-) diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offset= s.c index eb1a840e4110..30d4bbe68661 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -182,5 +182,7 @@ int main(void) #ifdef CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS DEFINE(FTRACE_OPS_DIRECT_CALL, offsetof(struct ftrace_ops, direct_call)); #endif + DEFINE(PIE_E0_ASM, PIE_E0); + DEFINE(PIE_E1_ASM, PIE_E1); return 0; } diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index fb30c8804f87..80d470aa469d 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -512,26 +512,11 @@ alternative_else_nop_endif ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 cbz x1, .Lskip_indirection =20 - /* - * The PROT_* macros describing the various memory types may resolve to - * C expressions if they include the PTE_MAYBE_* macros, and so they - * can only be used from C code. The PIE_E* constants below are also - * defined in terms of those macros, but will mask out those - * PTE_MAYBE_* constants, whether they are set or not. So #define them - * as 0x0 here so we can evaluate the PIE_E* constants in asm context. - */ - -#define PTE_MAYBE_NG 0 -#define PTE_MAYBE_SHARED 0 - - mov_q x0, PIE_E0 + mov_q x0, PIE_E0_ASM msr REG_PIRE0_EL1, x0 - mov_q x0, PIE_E1 + mov_q x0, PIE_E1_ASM msr REG_PIR_EL1, x0 =20 -#undef PTE_MAYBE_NG -#undef PTE_MAYBE_SHARED - orr tcr2, tcr2, TCR2_EL1_PIE msr REG_TCR2_EL1, x0 =20 --=20 2.25.1