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Reviewed-by: David Lechner Signed-off-by: Kim Seer Paller --- Documentation/ABI/testing/sysfs-bus-iio | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index 33c09c4ac60a4feec82308461643134f5ba84b66..190bfcc1e836b69622692d7c056= c0092e00f1a9b 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -741,7 +741,9 @@ Description: 1kohm_to_gnd: connected to ground via an 1kOhm resistor, 2.5kohm_to_gnd: connected to ground via a 2.5kOhm resistor, 6kohm_to_gnd: connected to ground via a 6kOhm resistor, + 7.7kohm_to_gnd: connected to ground via a 7.7kOhm resistor, 20kohm_to_gnd: connected to ground via a 20kOhm resistor, + 32kohm_to_gnd: connected to ground via a 32kOhm resistor, 42kohm_to_gnd: connected to ground via a 42kOhm resistor, 90kohm_to_gnd: connected to ground via a 90kOhm resistor, 100kohm_to_gnd: connected to ground via an 100kOhm resistor, --=20 2.34.1 From nobody Sun Dec 14 19:32:31 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11B1F29C32A; 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Mon, 28 Apr 2025 22:19:50 -0400 From: Kim Seer Paller Date: Tue, 29 Apr 2025 10:19:17 +0800 Subject: [PATCH v7 2/3] dt-bindings: iio: dac: Add adi,ad3530r.yaml Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250429-togreg-v7-2-0af9c543b545@analog.com> References: <20250429-togreg-v7-0-0af9c543b545@analog.com> In-Reply-To: <20250429-togreg-v7-0-0af9c543b545@analog.com> To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko CC: , , , Kim Seer Paller , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745893165; l=4981; i=kimseer.paller@analog.com; s=20250213; h=from:subject:message-id; bh=iWjl6l/so/q4SkT0NIpF43RFCXqWNXX4a/8xgOMrJ8Y=; b=Kja8yJFpPjIFHwyK0OdqD9YL+eg4Zl7X4JKAW7iTO3nZ9J2t3x34uOpSoWFpls6Pj7KDLS15j iWTIw7Q9SqxCGkp13w6L6ZtOJTwbhmH3DSylktNacg3eZufKhgWFaxj X-Developer-Key: i=kimseer.paller@analog.com; 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They provide full-scale output spans of 2.5V or 5V for reference voltages of 2.5V. These devices operate on a single 2.7V to 5.5V supply and are guaranteed to be monotonic by design. The "R" variants include a 2.5V, 5ppm/=C2=B0C internal reference, which is disabled by default. Reviewed-by: Krzysztof Kozlowski Reviewed-by: David Lechner Signed-off-by: Kim Seer Paller --- .../devicetree/bindings/iio/dac/adi,ad3530r.yaml | 100 +++++++++++++++++= ++++ MAINTAINERS | 7 ++ 2 files changed, 107 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml b/D= ocumentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a355d52a9d641e488fe291b97bc= 95ed115e96afd --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad3530r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD3530R and Similar DACs + +maintainers: + - Kim Seer Paller + +description: | + The AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) are low-po= wer, + 16-bit, buffered voltage output digital-to-analog converters (DACs) with + software-programmable gain controls, providing full-scale output spans o= f 2.5V + or 5V for reference voltages of 2.5V. These devices operate from a singl= e 2.7V + to 5.5V supply and are guaranteed monotonic by design. The "R" variants + include a 2.5V, 5ppm/=C2=B0C internal reference, which is disabled by de= fault. + Datasheet can be found here: + https://www.analog.com/media/en/technical-documentation/data-sheets/ad35= 30_ad530r.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad35= 31-ad3531r.pdf + +properties: + compatible: + enum: + - adi,ad3530 + - adi,ad3530r + - adi,ad3531 + - adi,ad3531r + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 50000000 + + vdd-supply: + description: Power Supply Input. + + iovdd-supply: + description: Digital Power Supply Input. + + io-channels: + description: + ADC channel used to monitor internal die temperature, output voltage= s, and + current of a selected channel via the MUXOUT pin. + maxItems: 1 + + ref-supply: + description: + Reference Input/Output. The voltage at the REF pin sets the full-sca= le + range of all channels. If not provided the internal reference is use= d and + also provided on the VREF pin. + + reset-gpios: + description: + Active low signal that is falling edge sensitive. When it is deasser= ted, + the digital core initialization is performed and all DAC registers e= xcept + the Interface Configuration A register are reset to their default va= lues. + maxItems: 1 + + ldac-gpios: + description: + LDAC pin to be used as a hardware trigger to update the DAC channels= . If + not present, the DAC channels are updated by Software LDAC. + maxItems: 1 + + adi,range-double: + description: + Configure the output range for all channels. If the property is pres= ent, + the output will range from 0V to 2Vref. If the property is not prese= nt, + the output will range from 0V to Vref. + type: boolean + +required: + - compatible + - reg + - vdd-supply + - iovdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + dac@0 { + compatible =3D "adi,ad3530r"; + reg =3D <0>; + spi-max-frequency =3D <1000000>; + + vdd-supply =3D <&vdd>; + iovdd-supply =3D <&iovdd>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 01079a189c93697c1db6b0ca4e54212d25589974..4ca59fc1bf25aa49fecf78a90b2= e1b73f25a2c05 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1300,6 +1300,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git= /netdev/net.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git F: drivers/net/amt.c =20 +ANALOG DEVICES INC AD3530R DRIVER +M: Kim Seer Paller +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml + ANALOG DEVICES INC AD3552R DRIVER M: Nuno S=C3=A1 L: linux-iio@vger.kernel.org --=20 2.34.1 From nobody Sun Dec 14 19:32:31 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8514529B788; 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Mon, 28 Apr 2025 22:19:59 -0400 From: Kim Seer Paller Date: Tue, 29 Apr 2025 10:19:18 +0800 Subject: [PATCH v7 3/3] iio: dac: ad3530r: Add driver for AD3530R and AD3531R Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250429-togreg-v7-3-0af9c543b545@analog.com> References: <20250429-togreg-v7-0-0af9c543b545@analog.com> In-Reply-To: <20250429-togreg-v7-0-0af9c543b545@analog.com> To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko CC: , , , Kim Seer Paller X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745893165; l=17633; i=kimseer.paller@analog.com; s=20250213; h=from:subject:message-id; bh=ZovHC5jv5GQMcDxvWroM85bywaF5dPZO+hKtP+o1L5U=; b=ZsLaje7PMuvNt+IaTQ13VgLWhHHG5ekYlrdigSMnW4RblcAVtqlIed1MYgHgXcF8j8iNIBfq0 PynbulSH/vUC/ZzzqwojffHSuZc3wIrseiQfLl+MVu8QIR9QOE1NNNz X-Developer-Key: i=kimseer.paller@analog.com; a=ed25519; pk=SPXIwGLg4GFKUNfuAavY+YhSDsx+Q+NwGLceiKwm8Ac= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: tGA05eNkwxKSLLOyHK1_y8amCPuA9Kce X-Authority-Analysis: v=2.4 cv=BOuzrEQG c=1 sm=1 tr=0 ts=6810375e cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=gAnH3GRIAAAA:8 a=IpJZQVW2AAAA:8 a=VwQbUJbxAAAA:8 a=TVtP5Seg8tfCNS8ahcEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-GUID: tGA05eNkwxKSLLOyHK1_y8amCPuA9Kce X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI5MDAxNSBTYWx0ZWRfX0MHH9aWqbe3S fT5W7LD9hNjTmiGUei6j58B+v304XJo+NACkQCszkYkxIbo6X1yrFj36j4O/AvNREkJLJnUe6N7 u8WXgmdlZpf2tOfUL4iUlTX/C+TdwwVGCWPZebbVcx5oEzKqLHOaQkWiI3UcvgN9ebgQIBKk8gY kVWz3yIv3b/hyOFeofqA6tdEXfnzm9ZK1nObrWhwib9uCmawQHKk2np+7/0vdl63epsHGwS/jj1 2J7q7waTciD4r1zCpJV8AmzLrIEps3tK9ZIqrazSiIAr8y1OPwgfU58NA1OQsB2CNJkDGKKBpuL v3+fFK4uholT97mAcdmerPU0xlbVK5KVGCk8kzbsM76jrcxfnDkA7EZB1kiiOeXtv3p4E2yPa7O +MxD3zqkKZBQ5dFFGmUBEWn+5guWskyEvQHCiAJ5M0LyULMgiMVVE+50jgWdROkkZv5W3DUQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-29_01,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 mlxscore=0 clxscore=1015 adultscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504290015 The AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) are low-power, 16-bit, buffered voltage output DACs with software- programmable gain controls, providing full-scale output spans of 2.5V or 5V for reference voltages of 2.5V. These devices operate from a single 2.7V to 5.5V supply and are guaranteed monotonic by design. The "R" variants include a 2.5V, 5ppm/=C2=B0C internal reference, which is disabled by default. Support for monitoring internal die temperature, output voltages, and current of a selected channel via the MUXOUT pin using an external ADC is currently not implemented. Reviewed-by: David Lechner Signed-off-by: Kim Seer Paller Reviewed-by: Andy Shevchenko --- MAINTAINERS | 1 + drivers/iio/dac/Kconfig | 11 + drivers/iio/dac/Makefile | 1 + drivers/iio/dac/ad3530r.c | 517 ++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 530 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4ca59fc1bf25aa49fecf78a90b2e1b73f25a2c05..25356d5a1a09e5ff6e7ed8eaa98= a8ea990e79d8e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1306,6 +1306,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml +F: drivers/iio/dac/ad3530r.c =20 ANALOG DEVICES INC AD3552R DRIVER M: Nuno S=C3=A1 diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index 4811ea973125a0dea1f8a9cdee1e0c045bc21981..e0996dc014a3d538ab6b4e0d50f= f54ede50f1527 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -6,6 +6,17 @@ =20 menu "Digital to analog converters" =20 +config AD3530R + tristate "Analog Devices AD3530R and Similar DACs driver" + depends on SPI + select REGMAP_SPI + help + Say yes here to build support for Analog Devices AD3530R, AD3531R + Digital to Analog Converter. + + To compile this driver as a module, choose M here: the + module will be called ad3530r. + config AD3552R_HS tristate "Analog Devices AD3552R DAC High Speed driver" select AD3552R_LIB diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index 8dd6cce81ed1152be4cf0af9ef877b5482ceb347..3684cd52b7fa9bc0ad9f855323d= cbb2e4965c404 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -4,6 +4,7 @@ # =20 # When adding new entries keep the list in alphabetical order +obj-$(CONFIG_AD3530R) +=3D ad3530r.o obj-$(CONFIG_AD3552R_HS) +=3D ad3552r-hs.o obj-$(CONFIG_AD3552R_LIB) +=3D ad3552r-common.o obj-$(CONFIG_AD3552R) +=3D ad3552r.o diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c new file mode 100644 index 0000000000000000000000000000000000000000..f9752a571aa53ca0d7e199ed6a7= 8550358185bf9 --- /dev/null +++ b/drivers/iio/dac/ad3530r.c @@ -0,0 +1,517 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AD3530R/AD3530 8-channel, 16-bit Voltage Output DAC Driver + * AD3531R/AD3531 4-channel, 16-bit Voltage Output DAC Driver + * + * Copyright 2025 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AD3530R_INTERFACE_CONFIG_A 0x00 +#define AD3530R_OUTPUT_OPERATING_MODE_0 0x20 +#define AD3530R_OUTPUT_OPERATING_MODE_1 0x21 +#define AD3530R_OUTPUT_CONTROL_0 0x2A +#define AD3530R_REFERENCE_CONTROL_0 0x3C +#define AD3530R_SW_LDAC_TRIG_A 0xE5 +#define AD3530R_INPUT_CH 0xEB +#define AD3530R_MAX_REG_ADDR 0xF9 + +#define AD3531R_SW_LDAC_TRIG_A 0xDD +#define AD3531R_INPUT_CH 0xE3 + +#define AD3530R_SLD_TRIG_A BIT(7) +#define AD3530R_OUTPUT_CONTROL_RANGE BIT(2) +#define AD3530R_REFERENCE_CONTROL_SEL BIT(0) +#define AD3530R_REG_VAL_MASK GENMASK(15, 0) +#define AD3530R_OP_MODE_CHAN_MSK(chan) (GENMASK(1, 0) << 2 * (chan)) + +#define AD3530R_SW_RESET (BIT(7) | BIT(0)) +#define AD3530R_INTERNAL_VREF_mV 2500 +#define AD3530R_LDAC_PULSE_US 100 + +#define AD3530R_DAC_MAX_VAL GENMASK(15, 0) +#define AD3530R_MAX_CHANNELS 8 +#define AD3531R_MAX_CHANNELS 4 + +/* Non-constant mask variant of FIELD_PREP() */ +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +enum ad3530r_mode { + AD3530R_NORMAL_OP, + AD3530R_POWERDOWN_1K, + AD3530R_POWERDOWN_7K7, + AD3530R_POWERDOWN_32K, +}; + +struct ad3530r_chan { + enum ad3530r_mode powerdown_mode; + bool powerdown; +}; + +struct ad3530r_chip_info { + const char *name; + const struct iio_chan_spec *channels; + int (*input_ch_reg)(unsigned int channel); + unsigned int num_channels; + unsigned int sw_ldac_trig_reg; + bool internal_ref_support; +}; + +struct ad3530r_state { + struct regmap *regmap; + /* lock to protect against multiple access to the device and shared data = */ + struct mutex lock; + struct ad3530r_chan chan[AD3530R_MAX_CHANNELS]; + const struct ad3530r_chip_info *chip_info; + struct gpio_desc *ldac_gpio; + int vref_mV; + /* + * DMA (thus cache coherency maintenance) may require the transfer + * buffers to live in their own cache lines. + */ + __be16 buf __aligned(IIO_DMA_MINALIGN); +}; + +static int ad3530r_input_ch_reg(unsigned int channel) +{ + return 2 * channel + AD3530R_INPUT_CH; +} + +static int ad3531r_input_ch_reg(unsigned int channel) +{ + return 2 * channel + AD3531R_INPUT_CH; +} + +static const char * const ad3530r_powerdown_modes[] =3D { + "1kohm_to_gnd", + "7.7kohm_to_gnd", + "32kohm_to_gnd", +}; + +static int ad3530r_get_powerdown_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + return st->chan[chan->channel].powerdown_mode - 1; +} + +static int ad3530r_set_powerdown_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + st->chan[chan->channel].powerdown_mode =3D mode + 1; + + return 0; +} + +static const struct iio_enum ad3530r_powerdown_mode_enum =3D { + .items =3D ad3530r_powerdown_modes, + .num_items =3D ARRAY_SIZE(ad3530r_powerdown_modes), + .get =3D ad3530r_get_powerdown_mode, + .set =3D ad3530r_set_powerdown_mode, +}; + +static ssize_t ad3530r_get_dac_powerdown(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + return sysfs_emit(buf, "%d\n", st->chan[chan->channel].powerdown); +} + +static ssize_t ad3530r_set_dac_powerdown(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + int ret; + unsigned int reg, pdmode, mask, val; + bool powerdown; + + ret =3D kstrtobool(buf, &powerdown); + if (ret) + return ret; + + guard(mutex)(&st->lock); + reg =3D chan->channel < AD3531R_MAX_CHANNELS ? + AD3530R_OUTPUT_OPERATING_MODE_0 : + AD3530R_OUTPUT_OPERATING_MODE_1; + pdmode =3D powerdown ? st->chan[chan->channel].powerdown_mode : 0; + mask =3D AD3530R_OP_MODE_CHAN_MSK(chan->channel); + val =3D field_prep(mask, pdmode); + + ret =3D regmap_update_bits(st->regmap, reg, mask, val); + if (ret) + return ret; + + st->chan[chan->channel].powerdown =3D powerdown; + + return len; +} + +static int ad3530r_trigger_hw_ldac(struct gpio_desc *ldac_gpio) +{ + gpiod_set_value_cansleep(ldac_gpio, 1); + fsleep(AD3530R_LDAC_PULSE_US); + gpiod_set_value_cansleep(ldac_gpio, 0); + + return 0; +} + +static int ad3530r_dac_write(struct ad3530r_state *st, unsigned int chan, + unsigned int val) +{ + int ret; + + guard(mutex)(&st->lock); + st->buf =3D cpu_to_be16(val); + + ret =3D regmap_bulk_write(st->regmap, st->chip_info->input_ch_reg(chan), + &st->buf, sizeof(st->buf)); + if (ret) + return ret; + + if (st->ldac_gpio) + return ad3530r_trigger_hw_ldac(st->ldac_gpio); + + return regmap_set_bits(st->regmap, st->chip_info->sw_ldac_trig_reg, + AD3530R_SLD_TRIG_A); +} + +static int ad3530r_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + int ret; + + guard(mutex)(&st->lock); + switch (info) { + case IIO_CHAN_INFO_RAW: + ret =3D regmap_bulk_read(st->regmap, + st->chip_info->input_ch_reg(chan->channel), + &st->buf, sizeof(st->buf)); + if (ret) + return ret; + + *val =3D FIELD_GET(AD3530R_REG_VAL_MASK, be16_to_cpu(st->buf)); + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + *val =3D st->vref_mV; + *val2 =3D 16; + + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static int ad3530r_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_RAW: + if (val < 0 || val > AD3530R_DAC_MAX_VAL) + return -EINVAL; + + return ad3530r_dac_write(st, chan->channel, val); + default: + return -EINVAL; + } +} + +static int ad3530r_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static const struct iio_chan_spec_ext_info ad3530r_ext_info[] =3D { + { + .name =3D "powerdown", + .shared =3D IIO_SEPARATE, + .read =3D ad3530r_get_dac_powerdown, + .write =3D ad3530r_set_dac_powerdown, + }, + IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad3530r_powerdown_mode_enum), + IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, + &ad3530r_powerdown_mode_enum), + { } +}; + +#define AD3530R_CHAN(_chan) \ +{ \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D _chan, \ + .output =3D 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .ext_info =3D ad3530r_ext_info, \ +} + +static const struct iio_chan_spec ad3530r_channels[] =3D { + AD3530R_CHAN(0), + AD3530R_CHAN(1), + AD3530R_CHAN(2), + AD3530R_CHAN(3), + AD3530R_CHAN(4), + AD3530R_CHAN(5), + AD3530R_CHAN(6), + AD3530R_CHAN(7), +}; + +static const struct iio_chan_spec ad3531r_channels[] =3D { + AD3530R_CHAN(0), + AD3530R_CHAN(1), + AD3530R_CHAN(2), + AD3530R_CHAN(3), +}; + +static const struct ad3530r_chip_info ad3530_chip =3D { + .name =3D "ad3530", + .channels =3D ad3530r_channels, + .num_channels =3D ARRAY_SIZE(ad3530r_channels), + .sw_ldac_trig_reg =3D AD3530R_SW_LDAC_TRIG_A, + .input_ch_reg =3D ad3530r_input_ch_reg, + .internal_ref_support =3D false, +}; + +static const struct ad3530r_chip_info ad3530r_chip =3D { + .name =3D "ad3530r", + .channels =3D ad3530r_channels, + .num_channels =3D ARRAY_SIZE(ad3530r_channels), + .sw_ldac_trig_reg =3D AD3530R_SW_LDAC_TRIG_A, + .input_ch_reg =3D ad3530r_input_ch_reg, + .internal_ref_support =3D true, +}; + +static const struct ad3530r_chip_info ad3531_chip =3D { + .name =3D "ad3531", + .channels =3D ad3531r_channels, + .num_channels =3D ARRAY_SIZE(ad3531r_channels), + .sw_ldac_trig_reg =3D AD3531R_SW_LDAC_TRIG_A, + .input_ch_reg =3D ad3531r_input_ch_reg, + .internal_ref_support =3D false, +}; + +static const struct ad3530r_chip_info ad3531r_chip =3D { + .name =3D "ad3531r", + .channels =3D ad3531r_channels, + .num_channels =3D ARRAY_SIZE(ad3531r_channels), + .sw_ldac_trig_reg =3D AD3531R_SW_LDAC_TRIG_A, + .input_ch_reg =3D ad3531r_input_ch_reg, + .internal_ref_support =3D true, +}; + +static int ad3530r_setup(struct ad3530r_state *st, int external_vref_uV) +{ + struct device *dev =3D regmap_get_device(st->regmap); + struct gpio_desc *reset_gpio; + int i, ret; + u8 range_multiplier, val; + + reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(reset_gpio)) + return dev_err_probe(dev, PTR_ERR(reset_gpio), + "Failed to get reset GPIO\n"); + + if (reset_gpio) { + /* Perform hardware reset */ + fsleep(1 * USEC_PER_MSEC); + gpiod_set_value_cansleep(reset_gpio, 0); + } else { + /* Perform software reset */ + ret =3D regmap_update_bits(st->regmap, AD3530R_INTERFACE_CONFIG_A, + AD3530R_SW_RESET, AD3530R_SW_RESET); + if (ret) + return ret; + } + + fsleep(10 * USEC_PER_MSEC); + + range_multiplier =3D 1; + if (device_property_read_bool(dev, "adi,range-double")) { + ret =3D regmap_set_bits(st->regmap, AD3530R_OUTPUT_CONTROL_0, + AD3530R_OUTPUT_CONTROL_RANGE); + if (ret) + return ret; + + range_multiplier =3D 2; + } + + if (external_vref_uV) { + st->vref_mV =3D range_multiplier * external_vref_uV / MILLI; + } else { + ret =3D regmap_set_bits(st->regmap, AD3530R_REFERENCE_CONTROL_0, + AD3530R_REFERENCE_CONTROL_SEL); + if (ret) + return ret; + + st->vref_mV =3D range_multiplier * AD3530R_INTERNAL_VREF_mV; + } + + /* Set normal operating mode for all channels */ + val =3D FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(0), AD3530R_NORMAL_OP) | + FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(1), AD3530R_NORMAL_OP) | + FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(2), AD3530R_NORMAL_OP) | + FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(3), AD3530R_NORMAL_OP); + + ret =3D regmap_write(st->regmap, AD3530R_OUTPUT_OPERATING_MODE_0, val); + if (ret) + return ret; + + if (st->chip_info->num_channels > 4) { + ret =3D regmap_write(st->regmap, AD3530R_OUTPUT_OPERATING_MODE_1, + val); + if (ret) + return ret; + } + + for (i =3D 0; i < st->chip_info->num_channels; i++) + st->chan[i].powerdown_mode =3D AD3530R_POWERDOWN_32K; + + st->ldac_gpio =3D devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_LOW); + if (IS_ERR(st->ldac_gpio)) + return dev_err_probe(dev, PTR_ERR(st->ldac_gpio), + "Failed to get ldac GPIO\n"); + + return 0; +} + +static const struct regmap_config ad3530r_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D AD3530R_MAX_REG_ADDR, +}; + +static const struct iio_info ad3530r_info =3D { + .read_raw =3D ad3530r_read_raw, + .write_raw =3D ad3530r_write_raw, + .debugfs_reg_access =3D ad3530r_reg_access, +}; + +static int ad3530r_probe(struct spi_device *spi) +{ + static const char * const regulators[] =3D { "vdd", "iovdd" }; + struct device *dev =3D &spi->dev; + struct iio_dev *indio_dev; + struct ad3530r_state *st; + int ret, external_vref_uV; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + + st->regmap =3D devm_regmap_init_spi(spi, &ad3530r_regmap_config); + if (IS_ERR(st->regmap)) + return dev_err_probe(dev, PTR_ERR(st->regmap), + "Failed to init regmap"); + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + st->chip_info =3D spi_get_device_match_data(spi); + if (!st->chip_info) + return -ENODEV; + + ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators), + regulators); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable regulators\n"); + + external_vref_uV =3D devm_regulator_get_enable_read_voltage(dev, "ref"); + if (external_vref_uV < 0 && external_vref_uV !=3D -ENODEV) + return external_vref_uV; + + if (external_vref_uV =3D=3D -ENODEV) + external_vref_uV =3D 0; + + if (!st->chip_info->internal_ref_support && external_vref_uV =3D=3D 0) + return -ENODEV; + + ret =3D ad3530r_setup(st, external_vref_uV); + if (ret) + return ret; + + indio_dev->name =3D st->chip_info->name; + indio_dev->info =3D &ad3530r_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D st->chip_info->channels; + indio_dev->num_channels =3D st->chip_info->num_channels; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct spi_device_id ad3530r_id[] =3D { + { "ad3530", (kernel_ulong_t)&ad3530_chip }, + { "ad3530r", (kernel_ulong_t)&ad3530r_chip }, + { "ad3531", (kernel_ulong_t)&ad3531_chip }, + { "ad3531r", (kernel_ulong_t)&ad3531r_chip }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad3530r_id); + +static const struct of_device_id ad3530r_of_match[] =3D { + { .compatible =3D "adi,ad3530", .data =3D &ad3530_chip }, + { .compatible =3D "adi,ad3530r", .data =3D &ad3530r_chip }, + { .compatible =3D "adi,ad3531", .data =3D &ad3531_chip }, + { .compatible =3D "adi,ad3531r", .data =3D &ad3531r_chip }, + { } +}; +MODULE_DEVICE_TABLE(of, ad3530r_of_match); + +static struct spi_driver ad3530r_driver =3D { + .driver =3D { + .name =3D "ad3530r", + .of_match_table =3D ad3530r_of_match, + }, + .probe =3D ad3530r_probe, + .id_table =3D ad3530r_id, +}; +module_spi_driver(ad3530r_driver); + +MODULE_AUTHOR("Kim Seer Paller "); +MODULE_DESCRIPTION("Analog Devices AD3530R and Similar DACs Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1