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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5f7ec0e6331sm3546619a12.78.2025.04.29.01.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 01:49:27 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 29 Apr 2025 09:49:24 +0100 Subject: [PATCH 1/2] phy: exynos5-usbdrd: fix setting LINKSYSTEM_FLADJ on exynos7870 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-exynos5-phy-field-prep-v1-1-39eb279a3e0e@linaro.org> References: <20250429-exynos5-phy-field-prep-v1-0-39eb279a3e0e@linaro.org> In-Reply-To: <20250429-exynos5-phy-field-prep-v1-0-39eb279a3e0e@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Kaustabh Chakraborty , Sam Protsenko Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The code here is trying to set the FLADJ field to 0x20, so it should clear any previous value in that field before or'ing-in the new value. Fixes: 588d5d20ca8d ("phy: exynos5-usbdrd: add exynos7870 USBDRD support") Signed-off-by: Andr=C3=A9 Draszik --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index 634c4310c660a50e5d0869645506ab1b64fffd4b..4ea1fabd4d6f9c9fe412f17d4d2= 6be07724b6361 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1186,6 +1186,7 @@ static void exynos7870_usbdrd_utmi_init(struct exynos= 5_usbdrd_phy *phy_drd) * See xHCI 1.0 spec, 5.2.4 */ reg |=3D LINKSYSTEM_XHCI_VERSION_CONTROL; + reg &=3D ~LINKSYSTEM_FLADJ; reg |=3D FIELD_PREP_CONST(LINKSYSTEM_FLADJ, 0x20); /* Set VBUSVALID signal as the VBUS pad is not used */ reg |=3D LINKSYSTEM_FORCE_BVALID; --=20 2.49.0.901.g37484f566f-goog From nobody Mon Feb 9 16:53:19 2026 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3723D274656 for ; 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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5f7ec0e6331sm3546619a12.78.2025.04.29.01.49.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 01:49:28 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 29 Apr 2025 09:49:25 +0100 Subject: [PATCH 2/2] phy: exynos5-usbdrd: s/FIELD_PREP_CONST/FIELD_PREP where appropriate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-exynos5-phy-field-prep-v1-2-39eb279a3e0e@linaro.org> References: <20250429-exynos5-phy-field-prep-v1-0-39eb279a3e0e@linaro.org> In-Reply-To: <20250429-exynos5-phy-field-prep-v1-0-39eb279a3e0e@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Kaustabh Chakraborty , Sam Protsenko Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Commit 9b6662a0f715 ("phy: exynos5-usbdrd: use GENMASK and FIELD_PREP for Exynos5 PHY registers") added FIELD_PREP_CONST() in many cases where FIELD_PREP() would have been more appropriate. It also switched existing uses of FIELD_PREP() to FIELD_PREP_CONST(). FIELD_PREP() is the preferred macro to use whenever possible while FIELD_PREP_CONST() is meant to be used in constant initialisers. Switch (back) to FIELD_PREP(). Fixes: 7e6c2ffe6c22 ("phy: exynos5-usbdrd: convert some FIELD_PREP_CONST() = to FIELD_PREP()") Signed-off-by: Andr=C3=A9 Draszik --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 62 +++++++++++++++-------------= ---- 1 file changed, 28 insertions(+), 34 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index 4ea1fabd4d6f9c9fe412f17d4d26be07724b6361..6cbe563a7bd0449248d6b41c4f6= 785c91ccc47ba 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -540,8 +540,7 @@ exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance= *inst) =20 /* Use EXTREFCLK as ref clock */ reg &=3D ~PHYCLKRST_REFCLKSEL; - reg |=3D FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, - PHYCLKRST_REFCLKSEL_EXT_REFCLK); + reg |=3D FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_EXT_REFCLK); =20 /* FSEL settings corresponding to reference clock */ reg &=3D ~(PHYCLKRST_FSEL_PIPE | @@ -549,24 +548,24 @@ exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instan= ce *inst) PHYCLKRST_SSC_REFCLKSEL); switch (phy_drd->extrefclk) { case EXYNOS5_FSEL_50MHZ: - reg |=3D (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x00) | - FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, - PHYCLKRST_MPLL_MULTIPLIER_50M_REF)); + reg |=3D (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x00) | + FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, + PHYCLKRST_MPLL_MULTIPLIER_50M_REF)); break; case EXYNOS5_FSEL_24MHZ: - reg |=3D (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x88) | - FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, - PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF)); + reg |=3D (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x88) | + FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, + PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF)); break; case EXYNOS5_FSEL_20MHZ: - reg |=3D (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x00) | - FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, - PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF)); + reg |=3D (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x00) | + FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, + PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF)); break; case EXYNOS5_FSEL_19MHZ2: - reg |=3D (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x88) | - FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, - PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF)); + reg |=3D (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x88) | + FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, + PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF)); break; default: dev_dbg(phy_drd->dev, "unsupported ref clk\n"); @@ -590,8 +589,7 @@ exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance = *inst) reg =3D readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); =20 reg &=3D ~PHYCLKRST_REFCLKSEL; - reg |=3D FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, - PHYCLKRST_REFCLKSEL_EXT_REFCLK); + reg |=3D FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_EXT_REFCLK); =20 reg &=3D ~(PHYCLKRST_FSEL_UTMI | PHYCLKRST_MPLL_MULTIPLIER | @@ -647,8 +645,7 @@ static void exynos5_usbdrd_pipe3_init(struct exynos5_us= bdrd_phy *phy_drd) reg =3D readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); /* Set Tx De-Emphasis level */ reg &=3D ~PHYPARAM1_PCS_TXDEEMPH; - reg |=3D FIELD_PREP_CONST(PHYPARAM1_PCS_TXDEEMPH, - PHYPARAM1_PCS_TXDEEMPH_VAL); + reg |=3D FIELD_PREP(PHYPARAM1_PCS_TXDEEMPH, PHYPARAM1_PCS_TXDEEMPH_VAL); writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); =20 reg =3D readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); @@ -669,7 +666,7 @@ exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready(struct exynos= 5_usbdrd_phy *phy_drd) =20 reg =3D readl(regs_base + EXYNOS850_DRD_SECPMACTL); reg &=3D ~SECPMACTL_PMA_REF_FREQ_SEL; - reg |=3D FIELD_PREP_CONST(SECPMACTL_PMA_REF_FREQ_SEL, 1); + reg |=3D FIELD_PREP(SECPMACTL_PMA_REF_FREQ_SEL, 1); /* SFR reset */ reg |=3D (SECPMACTL_PMA_LOW_PWR | SECPMACTL_PMA_APB_SW_RST); reg &=3D ~(SECPMACTL_PMA_ROPLL_REF_CLK_SEL | @@ -799,15 +796,13 @@ static void exynos5_usbdrd_utmi_init(struct exynos5_u= sbdrd_phy *phy_drd) reg =3D readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); /* Set Loss-of-Signal Detector sensitivity */ reg &=3D ~PHYPARAM0_REF_LOSLEVEL; - reg |=3D FIELD_PREP_CONST(PHYPARAM0_REF_LOSLEVEL, - PHYPARAM0_REF_LOSLEVEL_VAL); + reg |=3D FIELD_PREP(PHYPARAM0_REF_LOSLEVEL, PHYPARAM0_REF_LOSLEVEL_VAL); writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); =20 reg =3D readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); /* Set Tx De-Emphasis level */ reg &=3D ~PHYPARAM1_PCS_TXDEEMPH; - reg |=3D FIELD_PREP_CONST(PHYPARAM1_PCS_TXDEEMPH, - PHYPARAM1_PCS_TXDEEMPH_VAL); + reg |=3D FIELD_PREP(PHYPARAM1_PCS_TXDEEMPH, PHYPARAM1_PCS_TXDEEMPH_VAL); writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); =20 /* UTMI Power Control */ @@ -838,7 +833,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy) * See xHCI 1.0 spec, 5.2.4 */ reg =3D LINKSYSTEM_XHCI_VERSION_CONTROL | - FIELD_PREP_CONST(LINKSYSTEM_FLADJ, 0x20); + FIELD_PREP(LINKSYSTEM_FLADJ, 0x20); writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); =20 reg =3D readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); @@ -1145,8 +1140,7 @@ static void exynos7870_usbdrd_utmi_init(struct exynos= 5_usbdrd_phy *phy_drd) reg =3D readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); /* Use PADREFCLK as ref clock */ reg &=3D ~PHYCLKRST_REFCLKSEL; - reg |=3D FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, - PHYCLKRST_REFCLKSEL_PAD_REFCLK); + reg |=3D FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_PAD_REFCLK); /* Select ref clock rate */ reg &=3D ~PHYCLKRST_FSEL_UTMI; reg &=3D ~PHYCLKRST_FSEL_PIPE; @@ -1169,7 +1163,7 @@ static void exynos7870_usbdrd_utmi_init(struct exynos= 5_usbdrd_phy *phy_drd) else reg &=3D ~HSPHYPLLTUNE_PLL_B_TUNE; reg &=3D ~HSPHYPLLTUNE_PLL_P_TUNE; - reg |=3D FIELD_PREP_CONST(HSPHYPLLTUNE_PLL_P_TUNE, 14); + reg |=3D FIELD_PREP(HSPHYPLLTUNE_PLL_P_TUNE, 14); writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYPLLTUNE); =20 /* High-Speed PHY control */ @@ -1187,7 +1181,7 @@ static void exynos7870_usbdrd_utmi_init(struct exynos= 5_usbdrd_phy *phy_drd) */ reg |=3D LINKSYSTEM_XHCI_VERSION_CONTROL; reg &=3D ~LINKSYSTEM_FLADJ; - reg |=3D FIELD_PREP_CONST(LINKSYSTEM_FLADJ, 0x20); + reg |=3D FIELD_PREP(LINKSYSTEM_FLADJ, 0x20); /* Set VBUSVALID signal as the VBUS pad is not used */ reg |=3D LINKSYSTEM_FORCE_BVALID; reg |=3D LINKSYSTEM_FORCE_VBUSVALID; @@ -1350,7 +1344,7 @@ static void exynos850_usbdrd_utmi_init(struct exynos5= _usbdrd_phy *phy_drd) =20 /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ reg =3D readl(regs_base + EXYNOS850_DRD_LINKCTRL); - reg |=3D FIELD_PREP_CONST(LINKCTRL_BUS_FILTER_BYPASS, 0xf); + reg |=3D FIELD_PREP(LINKCTRL_BUS_FILTER_BYPASS, 0xf); writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); =20 if (!phy_drd->sw) { @@ -1367,19 +1361,19 @@ static void exynos850_usbdrd_utmi_init(struct exyno= s5_usbdrd_phy *phy_drd) reg &=3D ~SSPPLLCTL_FSEL; switch (phy_drd->extrefclk) { case EXYNOS5_FSEL_50MHZ: - reg |=3D FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); + reg |=3D FIELD_PREP(SSPPLLCTL_FSEL, 7); break; case EXYNOS5_FSEL_26MHZ: - reg |=3D FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6); + reg |=3D FIELD_PREP(SSPPLLCTL_FSEL, 6); break; case EXYNOS5_FSEL_24MHZ: - reg |=3D FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2); + reg |=3D FIELD_PREP(SSPPLLCTL_FSEL, 2); break; case EXYNOS5_FSEL_20MHZ: - reg |=3D FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1); + reg |=3D FIELD_PREP(SSPPLLCTL_FSEL, 1); break; case EXYNOS5_FSEL_19MHZ2: - reg |=3D FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0); + reg |=3D FIELD_PREP(SSPPLLCTL_FSEL, 0); break; default: dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", --=20 2.49.0.901.g37484f566f-goog